diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 19:43:31 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:07:00 -0400 |
commit | 1ab0eec6eae303fa2b2f7cc97b78aed4a9f895e5 (patch) | |
tree | f2f2c234e20f8a7ff863b7da0bc3726ec306f4fe /drivers | |
parent | 29b688960fcf6279f58d95f7e17f31ef15129a80 (diff) |
gpu: nvgpu: add resume_single_sm gr ops
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: If8805bcc042c75ea70c1689306feb3c8bf011655
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512216
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 |
5 files changed, 9 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index f94be010..aae54cc2 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -375,6 +375,8 @@ struct gpu_ops { | |||
375 | u32 global_esr_mask, bool check_errors); | 375 | u32 global_esr_mask, bool check_errors); |
376 | void (*suspend_all_sms)(struct gk20a *g, | 376 | void (*suspend_all_sms)(struct gk20a *g, |
377 | u32 global_esr_mask, bool check_errors); | 377 | u32 global_esr_mask, bool check_errors); |
378 | void (*resume_single_sm)(struct gk20a *g, | ||
379 | u32 gpc, u32 tpc, u32 sm); | ||
378 | } gr; | 380 | } gr; |
379 | struct { | 381 | struct { |
380 | void (*init_hw)(struct gk20a *g); | 382 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index f6857b66..70abef78 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8088,13 +8088,11 @@ void gk20a_gr_suspend_all_sms(struct gk20a *g, | |||
8088 | } | 8088 | } |
8089 | } | 8089 | } |
8090 | 8090 | ||
8091 | void gk20a_resume_single_sm(struct gk20a *g, | 8091 | void gk20a_gr_resume_single_sm(struct gk20a *g, |
8092 | u32 gpc, u32 tpc) | 8092 | u32 gpc, u32 tpc, u32 sm) |
8093 | { | 8093 | { |
8094 | u32 dbgr_control0; | 8094 | u32 dbgr_control0; |
8095 | u32 offset; | 8095 | u32 offset; |
8096 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | ||
8097 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
8098 | /* | 8096 | /* |
8099 | * The following requires some clarification. Despite the fact that both | 8097 | * The following requires some clarification. Despite the fact that both |
8100 | * RUN_TRIGGER and STOP_TRIGGER have the word "TRIGGER" in their | 8098 | * RUN_TRIGGER and STOP_TRIGGER have the word "TRIGGER" in their |
@@ -8108,7 +8106,7 @@ void gk20a_resume_single_sm(struct gk20a *g, | |||
8108 | * effect, before enabling the run trigger. | 8106 | * effect, before enabling the run trigger. |
8109 | */ | 8107 | */ |
8110 | 8108 | ||
8111 | offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | 8109 | offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); |
8112 | 8110 | ||
8113 | /*De-assert stop trigger */ | 8111 | /*De-assert stop trigger */ |
8114 | dbgr_control0 = | 8112 | dbgr_control0 = |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 90abcf22..659b37a6 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -612,8 +612,8 @@ void gr_gk20a_load_ctxsw_ucode_boot(struct gk20a *g, u64 addr_base, | |||
612 | void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c); | 612 | void gr_gk20a_free_tsg_gr_ctx(struct tsg_gk20a *c); |
613 | int gr_gk20a_disable_ctxsw(struct gk20a *g); | 613 | int gr_gk20a_disable_ctxsw(struct gk20a *g); |
614 | int gr_gk20a_enable_ctxsw(struct gk20a *g); | 614 | int gr_gk20a_enable_ctxsw(struct gk20a *g); |
615 | void gk20a_resume_single_sm(struct gk20a *g, | 615 | void gk20a_gr_resume_single_sm(struct gk20a *g, |
616 | u32 gpc, u32 tpc); | 616 | u32 gpc, u32 tpc, u32 sm); |
617 | void gk20a_resume_all_sms(struct gk20a *g); | 617 | void gk20a_resume_all_sms(struct gk20a *g); |
618 | void gk20a_gr_suspend_single_sm(struct gk20a *g, | 618 | void gk20a_gr_suspend_single_sm(struct gk20a *g, |
619 | u32 gpc, u32 tpc, u32 sm, | 619 | u32 gpc, u32 tpc, u32 sm, |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 4cabf214..04c8824b 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1633,4 +1633,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1633 | gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached; | 1633 | gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached; |
1634 | gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm; | 1634 | gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm; |
1635 | gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms; | 1635 | gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms; |
1636 | gops->gr.resume_single_sm = gk20a_gr_resume_single_sm; | ||
1636 | } | 1637 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index afd3750b..a1be22df 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1860,7 +1860,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1860 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1860 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1861 | "CILP: resume for gpc %d tpc %d\n", | 1861 | "CILP: resume for gpc %d tpc %d\n", |
1862 | gpc, tpc); | 1862 | gpc, tpc); |
1863 | gk20a_resume_single_sm(g, gpc, tpc); | 1863 | g->ops.gr.resume_single_sm(g, gpc, tpc, sm); |
1864 | 1864 | ||
1865 | *ignore_debugger = true; | 1865 | *ignore_debugger = true; |
1866 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); | 1866 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, "CILP: All done on gpc %d, tpc %d\n", gpc, tpc); |