diff options
author | Cory Perry <cperry@nvidia.com> | 2016-07-26 14:57:24 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-08-01 12:17:07 -0400 |
commit | 1933eb7d18c43cc70a0dbe94d3382d918f853383 (patch) | |
tree | 6a0873a7f29c11e537fd9ba91cbb3c198e90bd42 /drivers | |
parent | 38a59acc776c8ad5b7b5506d13a60712af7d5318 (diff) |
gpu: nvgpu: Remove early exit from mmu fault
Disabling / enabling of PFIFO must stay inside the isr. It cannot be held
disabled outside the isr -- this causes any kind of preemption mechanism to
fail in the presence of an MMU fault until the channel resets the engine.
Bug 1791696
Change-Id: I16600a8571f6555262a75deb305c1d67eb29581a
Signed-off-by: Cory Perry <cperry@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1191026
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 3dd7cb02..23a014d7 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -1407,6 +1407,9 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1407 | 1407 | ||
1408 | /* handled during channel free */ | 1408 | /* handled during channel free */ |
1409 | g->fifo.deferred_reset_pending = true; | 1409 | g->fifo.deferred_reset_pending = true; |
1410 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, | ||
1411 | "sm debugger attached," | ||
1412 | " deferring channel recovery to channel free"); | ||
1410 | } else if (engine_id != ~0) { | 1413 | } else if (engine_id != ~0) { |
1411 | was_reset = mutex_is_locked(&g->fifo.gr_reset_mutex); | 1414 | was_reset = mutex_is_locked(&g->fifo.gr_reset_mutex); |
1412 | mutex_lock(&g->fifo.gr_reset_mutex); | 1415 | mutex_lock(&g->fifo.gr_reset_mutex); |
@@ -1456,14 +1459,6 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1456 | gk20a_err(dev_from_gk20a(g), "couldn't locate channel for mmu fault"); | 1459 | gk20a_err(dev_from_gk20a(g), "couldn't locate channel for mmu fault"); |
1457 | } | 1460 | } |
1458 | 1461 | ||
1459 | if (g->fifo.deferred_reset_pending) { | ||
1460 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "sm debugger attached," | ||
1461 | " deferring channel recovery to channel free"); | ||
1462 | /* clear interrupt */ | ||
1463 | gk20a_writel(g, fifo_intr_mmu_fault_id_r(), fault_id); | ||
1464 | goto exit_enable; | ||
1465 | } | ||
1466 | |||
1467 | /* clear interrupt */ | 1462 | /* clear interrupt */ |
1468 | gk20a_writel(g, fifo_intr_mmu_fault_id_r(), fault_id); | 1463 | gk20a_writel(g, fifo_intr_mmu_fault_id_r(), fault_id); |
1469 | 1464 | ||
@@ -1476,7 +1471,6 @@ static bool gk20a_fifo_handle_mmu_fault( | |||
1476 | gr_gpfifo_ctl_access_enabled_f() | | 1471 | gr_gpfifo_ctl_access_enabled_f() | |
1477 | gr_gpfifo_ctl_semaphore_access_enabled_f()); | 1472 | gr_gpfifo_ctl_semaphore_access_enabled_f()); |
1478 | 1473 | ||
1479 | exit_enable: | ||
1480 | /* It is safe to enable ELPG again. */ | 1474 | /* It is safe to enable ELPG again. */ |
1481 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) | 1475 | if (support_gk20a_pmu(g->dev) && g->elpg_enabled) |
1482 | gk20a_pmu_enable_elpg(g); | 1476 | gk20a_pmu_enable_elpg(g); |