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authorMahantesh Kumbar <mkumbar@nvidia.com>2016-09-19 01:37:46 -0400
committerDeepak Nibade <dnibade@nvidia.com>2016-12-27 04:56:50 -0500
commit173bdefc92e2e4ef8f1e7e6ead7f86e746bee935 (patch)
tree69d9a43a453e988c54927ade2f5ce04457eaf312 /drivers
parentdb529935a5f50e9e683d44d2eb01d0d76a915792 (diff)
gpu: nvgpu: add support for voltage config
- changes to read voltage tables from VBIOS & create boardobj then send to pmu - Rail, Device & Policy objects are read from VBIOS & created boardobjs - RPC support to load, Set & get voltage. JIRA DNVGPU-122 Change-Id: I61621a514eef9c081a64c4ab066f01dfc28f8402 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1222774 (cherry picked from commit 9da86d8c2c547623cf5f38c89afeb3f5bb1667ac) Reviewed-on: http://git-master/r/1244656 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/Makefile.nvgpu-t18x7
-rw-r--r--drivers/gpu/nvgpu/include/bios.h132
-rw-r--r--drivers/gpu/nvgpu/perf/perf.h2
-rw-r--r--drivers/gpu/nvgpu/volt/volt.h30
-rw-r--r--drivers/gpu/nvgpu/volt/volt_dev.c582
-rw-r--r--drivers/gpu/nvgpu/volt/volt_dev.h69
-rw-r--r--drivers/gpu/nvgpu/volt/volt_pmu.c243
-rw-r--r--drivers/gpu/nvgpu/volt/volt_pmu.h22
-rw-r--r--drivers/gpu/nvgpu/volt/volt_policy.c360
-rw-r--r--drivers/gpu/nvgpu/volt/volt_policy.h64
-rw-r--r--drivers/gpu/nvgpu/volt/volt_rail.c438
-rw-r--r--drivers/gpu/nvgpu/volt/volt_rail.h77
12 files changed, 2025 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x
index d5162332..ea770e43 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu-t18x
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu-t18x
@@ -43,13 +43,18 @@ nvgpu-y += \
43 $(nvgpu-t18x)/clk/clk.o \ 43 $(nvgpu-t18x)/clk/clk.o \
44 $(nvgpu-t18x)/gp106/clk_gp106.o \ 44 $(nvgpu-t18x)/gp106/clk_gp106.o \
45 $(nvgpu-t18x)/gp106/gp106_gating_reglist.o \ 45 $(nvgpu-t18x)/gp106/gp106_gating_reglist.o \
46 $(nvgpu-t18x)/gp106/xve_gp106.o \
46 $(nvgpu-t18x)/gp106/therm_gp106.o \ 47 $(nvgpu-t18x)/gp106/therm_gp106.o \
47 $(nvgpu-t18x)/gp106/xve_gp106.o \ 48 $(nvgpu-t18x)/gp106/xve_gp106.o \
48 $(nvgpu-t18x)/pmgr/pwrdev.o \ 49 $(nvgpu-t18x)/pmgr/pwrdev.o \
49 $(nvgpu-t18x)/pmgr/pmgr.o \ 50 $(nvgpu-t18x)/pmgr/pmgr.o \
50 $(nvgpu-t18x)/pmgr/pmgrpmu.o \ 51 $(nvgpu-t18x)/pmgr/pmgrpmu.o \
51 $(nvgpu-t18x)/pmgr/pwrmonitor.o \ 52 $(nvgpu-t18x)/pmgr/pwrmonitor.o \
52 $(nvgpu-t18x)/pmgr/pwrpolicy.o 53 $(nvgpu-t18x)/pmgr/pwrpolicy.o \
54 $(nvgpu-t18x)/volt/volt_rail.o \
55 $(nvgpu-t18x)/volt/volt_dev.o \
56 $(nvgpu-t18x)/volt/volt_policy.o \
57 $(nvgpu-t18x)/volt/volt_pmu.o
53 58
54nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o 59nvgpu-$(CONFIG_TEGRA_GK20A) += $(nvgpu-t18x)/gp10b/platform_gp10b_tegra.o
55 60
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/bios.h
index d3a677f8..fb1e1f46 100644
--- a/drivers/gpu/nvgpu/include/bios.h
+++ b/drivers/gpu/nvgpu/include/bios.h
@@ -656,4 +656,136 @@ struct pwr_policy_3x_entry_struct {
656#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF 656#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_MASK 0xFFFF
657#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0 657#define NV_VBIOS_POWER_POLICY_3X_ENTRY_PARAM1_HW_THRESHOLD_LOW_THRESHOLD_VAL_SHIFT 0
658 658
659/* Voltage Rail Table */
660struct vbios_voltage_rail_table_1x_header {
661 u8 version;
662 u8 header_size;
663 u8 table_entry_size;
664 u8 num_table_entries;
665 u8 volt_domain_hal;
666} __packed;
667
668#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_07 0X00000007
669#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08 0X00000008
670#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09 0X00000009
671#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A 0X0000000A
672#define NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B 0X0000000B
673
674struct vbios_voltage_rail_table_1x_entry {
675 u32 boot_voltage_uv;
676 u8 rel_limit_vfe_equ_idx;
677 u8 alt_rel_limit_vfe_equidx;
678 u8 ov_limit_vfe_equ_idx;
679 u8 pwr_equ_idx;
680 u8 boot_volt_vfe_equ_idx;
681 u8 vmin_limit_vfe_equ_idx;
682 u8 volt_margin_limit_vfe_equ_idx;
683} __packed;
684
685/* Voltage Device Table */
686struct vbios_voltage_device_table_1x_header {
687 u8 version;
688 u8 header_size;
689 u8 table_entry_size;
690 u8 num_table_entries;
691};
692
693struct vbios_voltage_device_table_1x_entry {
694 u8 type;
695 u8 volt_domain;
696 u16 settle_time_us;
697 u32 param0;
698 u32 param1;
699 u32 param2;
700 u32 param3;
701 u32 param4;
702};
703
704#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_INVALID 0x00
705#define NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV 0x02
706
707#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_MASK \
708 GENMASK(23, 0)
709#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY_SHIFT 0
710#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_MASK \
711 GENMASK(31, 24)
712#define NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX_SHIFT 24
713
714#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_MASK \
715 GENMASK(23, 0)
716#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM_SHIFT 0
717#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_MASK \
718 GENMASK(31, 24)
719#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_SHIFT 24
720#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT 0x00
721#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE \
722 0x01
723#define NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE \
724 0x02
725#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_MASK \
726 GENMASK(23, 0)
727#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM_SHIFT 0
728#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_MASK \
729 GENMASK(31, 24)
730#define NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_RSVD_SHIFT 24
731
732#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_MASK \
733 GENMASK(23, 0)
734#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE_SHIFT 0
735#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_MASK \
736 GENMASK(31, 24)
737#define NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS_SHIFT 24
738
739#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_MASK \
740 GENMASK(23, 0)
741#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE_SHIFT 0
742#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_MASK \
743 GENMASK(31, 24)
744#define NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_RSVD_SHIFT 24
745
746/* Voltage Policy Table */
747struct vbios_voltage_policy_table_1x_header {
748 u8 version;
749 u8 header_size;
750 u8 table_entry_size;
751 u8 num_table_entries;
752 u8 perf_core_vf_seq_policy_idx;
753};
754
755struct vbios_voltage_policy_table_1x_entry {
756 u8 type;
757 u32 param0;
758 u32 param1;
759};
760
761#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_INVALID 0x00
762#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL 0x01
763#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP 0x02
764#define NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP 0x03
765
766#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_MASK \
767 GENMASK(7, 0)
768#define NV_VBIOS_VPT_ENTRY_PARAM0_SINGLE_RAIL_VOLT_DOMAIN_SHIFT 0
769#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_MASK GENMASK(8, 31)
770#define NV_VBIOS_VPT_ENTRY_PARAM0_RSVD_SHIFT 8
771
772#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_MASK \
773 GENMASK(7, 0)
774#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER_SHIFT 0
775#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_MASK \
776 GENMASK(15, 8)
777#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE_SHIFT 8
778#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_MASK \
779 GENMASK(23, 16)
780#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN_SHIFT 16
781#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_MASK \
782 GENMASK(31, 24)
783#define NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX_SHIFT 24
784
785/* Type-Specific Parameter DWORD 0 - Type = _SR_MULTI_STEP */
786#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_MASK \
787 GENMASK(15, 0)
788#define NV_VBIOS_VPT_ENTRY_PARAM1_SR_SETTLE_TIME_INTERMEDIATE_SHIFT \
789 0
790
659#endif 791#endif
diff --git a/drivers/gpu/nvgpu/perf/perf.h b/drivers/gpu/nvgpu/perf/perf.h
index 3ffaf4e1..c03bf2ae 100644
--- a/drivers/gpu/nvgpu/perf/perf.h
+++ b/drivers/gpu/nvgpu/perf/perf.h
@@ -17,6 +17,7 @@
17#include "vfe_var.h" 17#include "vfe_var.h"
18#include "pstate/pstate.h" 18#include "pstate/pstate.h"
19#include "gk20a/gk20a.h" 19#include "gk20a/gk20a.h"
20#include "volt/volt.h"
20 21
21#define CTRL_PERF_VFE_VAR_TYPE_INVALID 0x00 22#define CTRL_PERF_VFE_VAR_TYPE_INVALID 0x00
22#define CTRL_PERF_VFE_VAR_TYPE_DERIVED 0x01 23#define CTRL_PERF_VFE_VAR_TYPE_DERIVED 0x01
@@ -55,6 +56,7 @@ struct perf_pmupstate {
55 struct vfe_vars vfe_varobjs; 56 struct vfe_vars vfe_varobjs;
56 struct vfe_equs vfe_equobjs; 57 struct vfe_equs vfe_equobjs;
57 struct pstates pstatesobjs; 58 struct pstates pstatesobjs;
59 struct obj_volt volt;
58}; 60};
59 61
60u32 perf_pmu_vfe_load(struct gk20a *g); 62u32 perf_pmu_vfe_load(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/volt/volt.h b/drivers/gpu/nvgpu/volt/volt.h
new file mode 100644
index 00000000..0d64c265
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt.h
@@ -0,0 +1,30 @@
1/*
2* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14#ifndef _VOLT_H_
15#define _VOLT_H_
16
17#include "volt_rail.h"
18#include "volt_dev.h"
19#include "volt_policy.h"
20#include "volt_pmu.h"
21
22#define VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID 0xFF
23
24struct obj_volt {
25 struct voltage_rail_metadata volt_rail_metadata;
26 struct voltage_device_metadata volt_dev_metadata;
27 struct voltage_policy_metadata volt_policy_metadata;
28};
29
30#endif /* DRIVERS_GPU_NVGPU_VOLT_VOLT_H_ */
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c
new file mode 100644
index 00000000..89040658
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_dev.c
@@ -0,0 +1,582 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <linux/sort.h>
15
16#include "gk20a/gk20a.h"
17#include "include/bios.h"
18#include "boardobj/boardobjgrp.h"
19#include "boardobj/boardobjgrp_e32.h"
20#include "pmuif/gpmuifboardobj.h"
21#include "gm206/bios_gm206.h"
22#include "ctrl/ctrlvolt.h"
23#include "gk20a/pmu_gk20a.h"
24
25#include "pmuif/gpmuifperfvfe.h"
26#include "include/bios.h"
27#include "volt.h"
28
29#define RAW_PERIOD 160
30#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0
31#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1
32
33u32 volt_device_pmu_data_init_super(struct gk20a *g,
34 struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata)
35{
36 u32 status;
37 struct voltage_device *pdev;
38 struct nv_pmu_volt_volt_device_boardobj_set *pset;
39
40 status = boardobj_pmudatainit_super(g, pboard_obj, ppmudata);
41 if (status)
42 return status;
43
44 pdev = (struct voltage_device *)pboard_obj;
45 pset = (struct nv_pmu_volt_volt_device_boardobj_set *)ppmudata;
46
47 pset->switch_delay_us = pdev->switch_delay_us;
48 pset->voltage_min_uv = pdev->voltage_min_uv;
49 pset->voltage_max_uv = pdev->voltage_max_uv;
50 pset->volt_step_uv = pdev->volt_step_uv;
51
52 return status;
53}
54
55static u32 volt_device_pmu_data_init_pwm(struct gk20a *g,
56 struct boardobj *pboard_obj, struct nv_pmu_boardobj *ppmudata)
57{
58 u32 status = 0;
59 struct voltage_device_pwm *pdev;
60 struct nv_pmu_volt_volt_device_pwm_boardobj_set *pset;
61
62 status = volt_device_pmu_data_init_super(g, pboard_obj, ppmudata);
63 if (status)
64 return status;
65
66 pdev = (struct voltage_device_pwm *)pboard_obj;
67 pset = (struct nv_pmu_volt_volt_device_pwm_boardobj_set *)ppmudata;
68
69 pset->raw_period = pdev->raw_period;
70 pset->voltage_base_uv = pdev->voltage_base_uv;
71 pset->voltage_offset_scale_uv = pdev->voltage_offset_scale_uv;
72 pset->pwm_source = pdev->source;
73
74 return status;
75}
76
77u32 construct_volt_device(struct gk20a *g,
78 struct boardobj **ppboardobj, u16 size, void *pargs)
79{
80 struct voltage_device *ptmp_dev = (struct voltage_device *)pargs;
81 struct voltage_device *pvolt_dev = NULL;
82 u32 status = 0;
83
84 status = boardobj_construct_super(g, ppboardobj, size, pargs);
85 if (status)
86 return status;
87
88 pvolt_dev = (struct voltage_device *)*ppboardobj;
89
90 pvolt_dev->volt_domain = ptmp_dev->volt_domain;
91 pvolt_dev->i2c_dev_idx = ptmp_dev->i2c_dev_idx;
92 pvolt_dev->switch_delay_us = ptmp_dev->switch_delay_us;
93 pvolt_dev->rsvd_0 = VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID;
94 pvolt_dev->rsvd_1 =
95 VOLTAGE_DESCRIPTOR_TABLE_ENTRY_INVALID;
96 pvolt_dev->operation_type = ptmp_dev->operation_type;
97 pvolt_dev->voltage_min_uv = ptmp_dev->voltage_min_uv;
98 pvolt_dev->voltage_max_uv = ptmp_dev->voltage_max_uv;
99
100 pvolt_dev->super.pmudatainit = volt_device_pmu_data_init_super;
101
102 return status;
103}
104
105u32 construct_pwm_volt_device(struct gk20a *g, struct boardobj **ppboardobj,
106 u16 size, void *pargs)
107{
108 struct boardobj *pboard_obj = NULL;
109 struct voltage_device_pwm *ptmp_dev =
110 (struct voltage_device_pwm *)pargs;
111 struct voltage_device_pwm *pdev = NULL;
112 u32 status = 0;
113
114 status = construct_volt_device(g, ppboardobj, size, pargs);
115 if (status)
116 return status;
117
118 pboard_obj = (*ppboardobj);
119 pdev = (struct voltage_device_pwm *)*ppboardobj;
120
121 pboard_obj->pmudatainit = volt_device_pmu_data_init_pwm;
122
123 /* Set VOLTAGE_DEVICE_PWM-specific parameters */
124 pdev->voltage_base_uv = ptmp_dev->voltage_base_uv;
125 pdev->voltage_offset_scale_uv = ptmp_dev->voltage_offset_scale_uv;
126 pdev->source = ptmp_dev->source;
127 pdev->raw_period = ptmp_dev->raw_period;
128
129 return status;
130}
131
132
133struct voltage_device_entry *volt_dev_construct_dev_entry_pwm(struct gk20a *g,
134 u32 voltage_uv, void *pargs)
135{
136 struct voltage_device_pwm_entry *pentry = NULL;
137 struct voltage_device_pwm_entry *ptmp_entry =
138 (struct voltage_device_pwm_entry *)pargs;
139
140 pentry = kzalloc(sizeof(struct voltage_device_pwm_entry), GFP_KERNEL);
141 if (pentry == NULL)
142 return NULL;
143
144 memset(pentry, 0, sizeof(struct voltage_device_pwm_entry));
145
146 pentry->super.voltage_uv = voltage_uv;
147 pentry->duty_cycle = ptmp_entry->duty_cycle;
148
149 return (struct voltage_device_entry *)pentry;
150}
151
152static u8 volt_dev_operation_type_convert(u8 vbios_type)
153{
154 switch (vbios_type) {
155 case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_DEFAULT:
156 return CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT;
157
158 case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_STEADY_STATE:
159 return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE;
160
161 case NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE_LPWR_SLEEP_STATE:
162 return CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE;
163 }
164
165 return CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID;
166}
167
168struct voltage_device *volt_volt_device_construct(struct gk20a *g,
169 void *pargs)
170{
171 struct boardobj *pboard_obj = NULL;
172
173 if (BOARDOBJ_GET_TYPE(pargs) == CTRL_VOLT_DEVICE_TYPE_PWM) {
174 u32 status = construct_pwm_volt_device(g, &pboard_obj,
175 sizeof(struct voltage_device_pwm), pargs);
176 if (status) {
177 gk20a_err(dev_from_gk20a(g),
178 " Could not allocate memory for VOLTAGE_DEVICE type (%x).",
179 BOARDOBJ_GET_TYPE(pargs));
180 pboard_obj = NULL;
181 }
182 }
183
184 return (struct voltage_device *)pboard_obj;
185}
186
187static u32 volt_get_voltage_device_table_1x_psv(struct gk20a *g,
188 struct vbios_voltage_device_table_1x_entry *p_bios_entry,
189 struct voltage_device_metadata *p_Volt_Device_Meta_Data,
190 u8 entry_Idx)
191{
192 u32 status = 0;
193 u32 entry_cnt = 0;
194 struct voltage_device *pvolt_dev = NULL;
195 struct voltage_device_pwm *pvolt_dev_pwm = NULL;
196 struct voltage_device_pwm *ptmp_dev = NULL;
197 u32 duty_cycle;
198 u32 frequency_hz;
199 u32 voltage_uv;
200 u8 ext_dev_idx;
201 u8 steps;
202 u8 volt_domain = 0;
203 struct voltage_device_pwm_entry pwm_entry = { { 0 } };
204
205 ptmp_dev = kzalloc(sizeof(struct voltage_device_pwm), GFP_KERNEL);
206 if (ptmp_dev == NULL)
207 return -ENOMEM;
208
209 frequency_hz = (u32)BIOS_GET_FIELD(p_bios_entry->param0,
210 NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_INPUT_FREQUENCY);
211
212 ext_dev_idx = (u8)BIOS_GET_FIELD(p_bios_entry->param0,
213 NV_VBIOS_VDT_1X_ENTRY_PARAM0_PSV_EXT_DEVICE_INDEX);
214
215 ptmp_dev->super.operation_type = volt_dev_operation_type_convert(
216 (u8)BIOS_GET_FIELD(p_bios_entry->param1,
217 NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_OPERATION_TYPE));
218
219 if (ptmp_dev->super.operation_type ==
220 CTRL_VOLT_DEVICE_OPERATION_TYPE_INVALID) {
221 gk20a_err(dev_from_gk20a(g),
222 " Invalid Voltage Device Operation Type.");
223
224 status = -EINVAL;
225 goto done;
226 }
227
228 ptmp_dev->super.voltage_min_uv =
229 (u32)BIOS_GET_FIELD(p_bios_entry->param1,
230 NV_VBIOS_VDT_1X_ENTRY_PARAM1_PSV_VOLTAGE_MINIMUM);
231
232 ptmp_dev->super.voltage_max_uv =
233 (u32)BIOS_GET_FIELD(p_bios_entry->param2,
234 NV_VBIOS_VDT_1X_ENTRY_PARAM2_PSV_VOLTAGE_MAXIMUM);
235
236 ptmp_dev->voltage_base_uv = BIOS_GET_FIELD(p_bios_entry->param3,
237 NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_BASE);
238
239 steps = (u8)BIOS_GET_FIELD(p_bios_entry->param3,
240 NV_VBIOS_VDT_1X_ENTRY_PARAM3_PSV_VOLTAGE_STEPS);
241 if (steps == VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID)
242 steps = VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT;
243
244 ptmp_dev->voltage_offset_scale_uv =
245 BIOS_GET_FIELD(p_bios_entry->param4,
246 NV_VBIOS_VDT_1X_ENTRY_PARAM4_PSV_OFFSET_SCALE);
247
248 volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
249 (u8)p_bios_entry->volt_domain);
250 if (volt_domain == CTRL_VOLT_DOMAIN_INVALID) {
251 gk20a_err(dev_from_gk20a(g),
252 "invalid voltage domain = %d",
253 (u8)p_bios_entry->volt_domain);
254 status = -EINVAL;
255 goto done;
256 }
257
258 if (ptmp_dev->super.operation_type ==
259 CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
260 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_THERM_VID_PWM_1;
261 } else if (ptmp_dev->super.operation_type ==
262 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_STEADY_STATE) {
263 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_0;
264 } else if (ptmp_dev->super.operation_type ==
265 CTRL_VOLT_DEVICE_OPERATION_TYPE_LPWR_SLEEP_STATE) {
266 ptmp_dev->source = NV_PMU_PMGR_PWM_SOURCE_RSVD_1;
267 }
268
269 ptmp_dev->raw_period = RAW_PERIOD;
270
271 /* Initialize data for parent class. */
272 ptmp_dev->super.super.type = CTRL_VOLT_DEVICE_TYPE_PWM;
273 ptmp_dev->super.volt_domain = volt_domain;
274 ptmp_dev->super.i2c_dev_idx = ext_dev_idx;
275 ptmp_dev->super.switch_delay_us = (u16)p_bios_entry->settle_time_us;
276
277 pvolt_dev = volt_volt_device_construct(g, ptmp_dev);
278 if (pvolt_dev == NULL) {
279 gk20a_err(dev_from_gk20a(g),
280 " Failure to construct VOLTAGE_DEVICE object.");
281
282 status = -EINVAL;
283 goto done;
284 }
285
286 status = boardobjgrp_objinsert(
287 &p_Volt_Device_Meta_Data->volt_devices.super,
288 (struct boardobj *)pvolt_dev, entry_Idx);
289 if (status) {
290 gk20a_err(dev_from_gk20a(g),
291 "could not add VOLTAGE_DEVICE for entry %d into boardobjgrp ",
292 entry_Idx);
293 goto done;
294 }
295
296 pvolt_dev_pwm = (struct voltage_device_pwm *)pvolt_dev;
297
298 duty_cycle = 0;
299 do {
300 voltage_uv = (u32)(pvolt_dev_pwm->voltage_base_uv +
301 (s32)((((s64)((s32)duty_cycle)) *
302 pvolt_dev_pwm->voltage_offset_scale_uv)
303 / ((s64)((s32) pvolt_dev_pwm->raw_period))));
304
305 /* Skip creating entry for invalid voltage. */
306 if ((voltage_uv >= pvolt_dev_pwm->super.voltage_min_uv) &&
307 (voltage_uv <= pvolt_dev_pwm->super.voltage_max_uv)) {
308 if (pvolt_dev_pwm->voltage_offset_scale_uv < 0)
309 pwm_entry.duty_cycle =
310 pvolt_dev_pwm->raw_period - duty_cycle;
311 else
312 pwm_entry.duty_cycle = duty_cycle;
313
314 /* Check if there is room left in the voltage table. */
315 if (entry_cnt == VOLTAGE_TABLE_MAX_ENTRIES) {
316 gk20a_err(dev_from_gk20a(g), "Voltage table is full");
317 status = -EINVAL;
318 goto done;
319 }
320
321 pvolt_dev->pentry[entry_cnt] =
322 volt_dev_construct_dev_entry_pwm(g,
323 voltage_uv, &pwm_entry);
324 if (pvolt_dev->pentry[entry_cnt] == NULL) {
325 gk20a_err(dev_from_gk20a(g),
326 " Error creating voltage_device_pwm_entry!");
327 status = -EINVAL;
328 goto done;
329 }
330
331 entry_cnt++;
332 }
333
334 /* Obtain next value after the specified steps. */
335 duty_cycle = duty_cycle + (u32)steps;
336
337 /* Cap duty cycle to PWM period. */
338 if (duty_cycle > pvolt_dev_pwm->raw_period)
339 duty_cycle = pvolt_dev_pwm->raw_period;
340
341 } while (duty_cycle < pvolt_dev_pwm->raw_period);
342
343done:
344 if (pvolt_dev != NULL)
345 pvolt_dev->num_entries = entry_cnt;
346
347 kfree(ptmp_dev);
348 return status;
349}
350
351static u32 volt_get_volt_devices_table(struct gk20a *g,
352 struct voltage_device_metadata *pvolt_device_metadata)
353{
354 u32 status = 0;
355 u8 *volt_device_table_ptr = NULL;
356 struct vbios_voltage_device_table_1x_header header = { 0 };
357 struct vbios_voltage_device_table_1x_entry entry = { 0 };
358 u8 entry_idx;
359 u8 *entry_offset;
360
361 if (g->ops.bios.get_perf_table_ptrs) {
362 volt_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
363 g->bios.perf_token, VOLTAGE_DEVICE_TABLE);
364 if (volt_device_table_ptr == NULL) {
365 status = -EINVAL;
366 goto done;
367 }
368 } else {
369 status = -EINVAL;
370 goto done;
371 }
372
373 memcpy(&header, volt_device_table_ptr,
374 sizeof(struct vbios_voltage_device_table_1x_header));
375
376 /* Read in the entries. */
377 for (entry_idx = 0; entry_idx < header.num_table_entries; entry_idx++) {
378 entry_offset = (volt_device_table_ptr + header.header_size +
379 (entry_idx * header.table_entry_size));
380
381 memcpy(&entry, entry_offset,
382 sizeof(struct vbios_voltage_device_table_1x_entry));
383
384 if (entry.type == NV_VBIOS_VOLTAGE_DEVICE_1X_ENTRY_TYPE_PSV)
385 status = volt_get_voltage_device_table_1x_psv(g,
386 &entry, pvolt_device_metadata,
387 entry_idx);
388 }
389
390done:
391 return status;
392}
393
394static u32 _volt_device_devgrp_pmudata_instget(struct gk20a *g,
395 struct nv_pmu_boardobjgrp *pmuboardobjgrp,
396 struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx)
397{
398 struct nv_pmu_volt_volt_device_boardobj_grp_set *pgrp_set =
399 (struct nv_pmu_volt_volt_device_boardobj_grp_set *)
400 pmuboardobjgrp;
401
402 gk20a_dbg_info("");
403
404 /*check whether pmuboardobjgrp has a valid boardobj in index*/
405 if (((u32)BIT(idx) &
406 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
407 return -EINVAL;
408
409 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
410 &pgrp_set->objects[idx].data.board_obj;
411 gk20a_dbg_info("Done");
412 return 0;
413}
414
415static u32 _volt_device_devgrp_pmustatus_instget(struct gk20a *g,
416 void *pboardobjgrppmu,
417 struct nv_pmu_boardobj_query **ppboardobjpmustatus, u8 idx)
418{
419 struct nv_pmu_volt_volt_device_boardobj_grp_get_status *pgrp_get_status
420 = (struct nv_pmu_volt_volt_device_boardobj_grp_get_status *)
421 pboardobjgrppmu;
422
423 /*check whether pmuboardobjgrp has a valid boardobj in index*/
424 if (((u32)BIT(idx) &
425 pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
426 return -EINVAL;
427
428 *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
429 &pgrp_get_status->objects[idx].data.board_obj;
430 return 0;
431}
432
433static int volt_device_volt_cmp(const void *a, const void *b)
434{
435 const struct voltage_device_entry *a_entry = *(const struct voltage_device_entry **)a;
436 const struct voltage_device_entry *b_entry = *(const struct voltage_device_entry **)b;
437
438 return (int)a_entry->voltage_uv - (int)b_entry->voltage_uv;
439}
440
441u32 volt_device_state_init(struct gk20a *g, struct voltage_device *pvolt_dev)
442{
443 u32 status = 0;
444 struct voltage_rail *pRail = NULL;
445 u8 rail_idx = 0;
446
447 sort(pvolt_dev->pentry, pvolt_dev->num_entries,
448 sizeof(*pvolt_dev->pentry), volt_device_volt_cmp,
449 NULL);
450
451 /* Initialize VOLT_DEVICE step size. */
452 if (pvolt_dev->num_entries <= VOLTAGE_TABLE_MAX_ENTRIES_ONE)
453 pvolt_dev->volt_step_uv = NV_PMU_VOLT_VALUE_0V_IN_UV;
454 else
455 pvolt_dev->volt_step_uv = (pvolt_dev->pentry[1]->voltage_uv -
456 pvolt_dev->pentry[0]->voltage_uv);
457
458 /* Build VOLT_RAIL SW state from VOLT_DEVICE SW state. */
459 /* If VOLT_RAIL isn't supported, exit. */
460 if (VOLT_RAIL_VOLT_3X_SUPPORTED(&g->perf_pmu.volt)) {
461 rail_idx = volt_rail_volt_domain_convert_to_idx(g,
462 pvolt_dev->volt_domain);
463 if (rail_idx == CTRL_BOARDOBJ_IDX_INVALID) {
464 gk20a_err(dev_from_gk20a(g),
465 " could not convert voltage domain to rail index.");
466 status = -EINVAL;
467 goto done;
468 }
469
470 pRail = VOLT_GET_VOLT_RAIL(&g->perf_pmu.volt, rail_idx);
471 if (pRail == NULL) {
472 gk20a_err(dev_from_gk20a(g),
473 "could not obtain ptr to rail object from rail index");
474 status = -EINVAL;
475 goto done;
476 }
477
478 status = volt_rail_volt_dev_register(g, pRail,
479 BOARDOBJ_GET_IDX(pvolt_dev), pvolt_dev->operation_type);
480 if (status) {
481 gk20a_err(dev_from_gk20a(g),
482 "Failed to register the device with rail obj");
483 goto done;
484 }
485 }
486
487done:
488 if (status)
489 gk20a_err(dev_from_gk20a(g),
490 "Error in building rail sw state device sw");
491
492 return status;
493}
494
495u32 volt_dev_pmu_setup(struct gk20a *g)
496{
497 u32 status;
498 struct boardobjgrp *pboardobjgrp = NULL;
499
500 gk20a_dbg_info("");
501
502 pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super;
503
504 if (!pboardobjgrp->bconstructed)
505 return -EINVAL;
506
507 status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
508
509 gk20a_dbg_info("Done");
510 return status;
511}
512
513u32 volt_dev_sw_setup(struct gk20a *g)
514{
515 u32 status = 0;
516 struct boardobjgrp *pboardobjgrp = NULL;
517 struct voltage_device *pvolt_device;
518 u8 i;
519
520 gk20a_dbg_info("");
521
522 status = boardobjgrpconstruct_e32(&g->perf_pmu.volt.volt_dev_metadata.
523 volt_devices);
524 if (status) {
525 gk20a_err(dev_from_gk20a(g),
526 "error creating boardobjgrp for volt rail, status - 0x%x",
527 status);
528 goto done;
529 }
530
531 pboardobjgrp = &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super;
532
533 pboardobjgrp->pmudatainstget = _volt_device_devgrp_pmudata_instget;
534 pboardobjgrp->pmustatusinstget = _volt_device_devgrp_pmustatus_instget;
535
536 /* Obtain Voltage Rail Table from VBIOS */
537 status = volt_get_volt_devices_table(g, &g->perf_pmu.volt.
538 volt_dev_metadata);
539 if (status)
540 goto done;
541
542 /* Populate data for the VOLT_RAIL PMU interface */
543 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_DEVICE);
544
545 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
546 volt, VOLT, volt_device, VOLT_DEVICE);
547 if (status) {
548 gk20a_err(dev_from_gk20a(g),
549 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
550 status);
551 goto done;
552 }
553
554 status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
555 &g->perf_pmu.volt.volt_dev_metadata.volt_devices.super,
556 volt, VOLT, volt_device, VOLT_DEVICE);
557 if (status) {
558 gk20a_err(dev_from_gk20a(g),
559 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
560 status);
561 goto done;
562 }
563
564 /* update calibration to fuse */
565 BOARDOBJGRP_FOR_EACH(&(g->perf_pmu.volt.volt_dev_metadata.volt_devices.
566 super),
567 struct voltage_device *, pvolt_device, i) {
568 status = volt_device_state_init(g, pvolt_device);
569 if (status) {
570 gk20a_err(dev_from_gk20a(g),
571 "failure while executing devices's state init interface");
572 gk20a_err(dev_from_gk20a(g),
573 " railIdx = %d, status = 0x%x", i, status);
574 goto done;
575 }
576 }
577
578done:
579 gk20a_dbg_info(" done status %x", status);
580 return status;
581}
582
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.h b/drivers/gpu/nvgpu/volt/volt_dev.h
new file mode 100644
index 00000000..5113567d
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_dev.h
@@ -0,0 +1,69 @@
1/*
2* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14
15#ifndef _VOLTDEV_H_
16#define _VOLTDEV_H_
17
18#include "boardobj/boardobj.h"
19#include "boardobj/boardobjgrp.h"
20#include "ctrl/ctrlvolt.h"
21
22#define VOLTAGE_TABLE_MAX_ENTRIES_ONE 1
23#define VOLTAGE_TABLE_MAX_ENTRIES 256
24
25struct voltage_device {
26 struct boardobj super;
27 u8 volt_domain;
28 u8 i2c_dev_idx;
29 u32 switch_delay_us;
30 u32 num_entries;
31 struct voltage_device_entry *pentry[VOLTAGE_TABLE_MAX_ENTRIES];
32 struct voltage_device_entry *pcurr_entry;
33 u8 rsvd_0;
34 u8 rsvd_1;
35 u8 operation_type;
36 u32 voltage_min_uv;
37 u32 voltage_max_uv;
38 u32 volt_step_uv;
39};
40
41struct voltage_device_entry {
42 u32 voltage_uv;
43};
44
45struct voltage_device_metadata {
46 struct boardobjgrp_e32 volt_devices;
47};
48
49/*!
50 * Extends VOLTAGE_DEVICE providing attributes specific to PWM controllers.
51 */
52struct voltage_device_pwm {
53 struct voltage_device super;
54 s32 voltage_base_uv;
55 s32 voltage_offset_scale_uv;
56 enum nv_pmu_pmgr_pwm_source source;
57 u32 raw_period;
58};
59
60struct voltage_device_pwm_entry {
61 struct voltage_device_entry super;
62 u32 duty_cycle;
63};
64/* PWM end */
65
66u32 volt_dev_sw_setup(struct gk20a *g);
67u32 volt_dev_pmu_setup(struct gk20a *g);
68
69#endif /* _VOLTDEV_H_ */
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c
new file mode 100644
index 00000000..4d451b65
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.c
@@ -0,0 +1,243 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "gk20a/gk20a.h"
15#include "include/bios.h"
16#include "boardobj/boardobjgrp.h"
17#include "boardobj/boardobjgrp_e32.h"
18#include "pmuif/gpmuifboardobj.h"
19#include "gm206/bios_gm206.h"
20#include "ctrl/ctrlvolt.h"
21#include "ctrl/ctrlperf.h"
22#include "gk20a/pmu_gk20a.h"
23
24#include "pmuif/gpmuifperfvfe.h"
25#include "pmuif/gpmuifvolt.h"
26#include "include/bios.h"
27#include "volt.h"
28
29#define RAIL_COUNT 2
30
31struct volt_rpc_pmucmdhandler_params {
32 struct nv_pmu_volt_rpc *prpc_call;
33 u32 success;
34};
35
36static void volt_rpc_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
37 void *param, u32 handle, u32 status)
38{
39 struct volt_rpc_pmucmdhandler_params *phandlerparams =
40 (struct volt_rpc_pmucmdhandler_params *)param;
41
42 gk20a_dbg_info("");
43
44 if (msg->msg.volt.msg_type != NV_PMU_VOLT_MSG_ID_RPC) {
45 gk20a_err(dev_from_gk20a(g), "unsupported msg for VOLT RPC %x",
46 msg->msg.volt.msg_type);
47 return;
48 }
49
50 if (phandlerparams->prpc_call->b_supported)
51 phandlerparams->success = 1;
52}
53
54
55static u32 volt_pmu_rpc_execute(struct gk20a *g,
56 struct nv_pmu_volt_rpc *prpc_call)
57{
58 struct pmu_cmd cmd = { { 0 } };
59 struct pmu_msg msg = { { 0 } };
60 struct pmu_payload payload = { { 0 } };
61 u32 status = 0;
62 u32 seqdesc;
63 struct volt_rpc_pmucmdhandler_params handler = {0};
64
65 cmd.hdr.unit_id = PMU_UNIT_VOLT;
66 cmd.hdr.size = (u32)sizeof(struct nv_pmu_volt_cmd) +
67 (u32)sizeof(struct pmu_hdr);
68 cmd.cmd.volt.cmd_type = NV_PMU_VOLT_CMD_ID_RPC;
69 msg.hdr.size = sizeof(struct pmu_msg);
70
71 payload.in.buf = (u8 *)prpc_call;
72 payload.in.size = (u32)sizeof(struct nv_pmu_volt_rpc);
73 payload.in.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
74 payload.in.offset = NV_PMU_VOLT_CMD_RPC_ALLOC_OFFSET;
75
76 payload.out.buf = (u8 *)prpc_call;
77 payload.out.size = (u32)sizeof(struct nv_pmu_volt_rpc);
78 payload.out.fb_size = PMU_CMD_SUBMIT_PAYLOAD_PARAMS_FB_SIZE_UNUSED;
79 payload.out.offset = NV_PMU_VOLT_MSG_RPC_ALLOC_OFFSET;
80
81 handler.prpc_call = prpc_call;
82 handler.success = 0;
83
84 status = gk20a_pmu_cmd_post(g, &cmd, NULL, &payload,
85 PMU_COMMAND_QUEUE_LPQ,
86 volt_rpc_pmucmdhandler, (void *)&handler,
87 &seqdesc, ~0);
88 if (status) {
89 gk20a_err(dev_from_gk20a(g), "unable to post volt RPC cmd %x",
90 cmd.cmd.volt.cmd_type);
91 goto volt_pmu_rpc_execute;
92 }
93
94 pmu_wait_message_cond(&g->pmu,
95 gk20a_get_gr_idle_timeout(g),
96 &handler.success, 1);
97
98 if (handler.success == 0) {
99 status = -EINVAL;
100 gk20a_err(dev_from_gk20a(g), "rpc call to volt failed");
101 }
102
103volt_pmu_rpc_execute:
104 return status;
105}
106
107u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g)
108{
109 struct nv_pmu_volt_rpc rpc_call = { 0 };
110 u32 status = 0;
111
112 rpc_call.function = NV_PMU_VOLT_RPC_ID_LOAD;
113
114 status = volt_pmu_rpc_execute(g, &rpc_call);
115 if (status)
116 gk20a_err(dev_from_gk20a(g),
117 "Error while executing LOAD RPC: status = 0x%08x.",
118 status);
119
120 return status;
121}
122
123static u32 volt_rail_get_voltage(struct gk20a *g,
124 u8 volt_domain, u32 *pvoltage_uv)
125{
126 struct nv_pmu_volt_rpc rpc_call = { 0 };
127 u32 status = 0;
128 u8 rail_idx;
129
130 rail_idx = volt_rail_volt_domain_convert_to_idx(g, volt_domain);
131 if ((rail_idx == CTRL_VOLT_RAIL_INDEX_INVALID) ||
132 (!VOLT_RAIL_INDEX_IS_VALID(&g->perf_pmu.volt, rail_idx))) {
133 gk20a_err(dev_from_gk20a(g),
134 "failed: volt_domain = %d, voltage rail table = %d.",
135 volt_domain, rail_idx);
136 return -EINVAL;
137 }
138
139 /* Set RPC parameters. */
140 rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_RAIL_GET_VOLTAGE;
141 rpc_call.params.volt_rail_get_voltage.rail_idx = rail_idx;
142
143 /* Execute the voltage get request via PMU RPC. */
144 status = volt_pmu_rpc_execute(g, &rpc_call);
145 if (status) {
146 gk20a_err(dev_from_gk20a(g),
147 "Error while executing volt_rail_get_voltage rpc");
148 return status;
149 }
150
151 /* Copy out the current voltage. */
152 *pvoltage_uv = rpc_call.params.volt_rail_get_voltage.voltage_uv;
153
154 return status;
155}
156
157
158static u32 volt_policy_set_voltage(struct gk20a *g, u8 client_id,
159 struct ctrl_perf_volt_rail_list *prail_list)
160{
161 struct nv_pmu_volt_rpc rpc_call = { 0 };
162 struct obj_volt *pvolt = &g->perf_pmu.volt;
163 u32 status = 0;
164 u8 policy_idx = CTRL_VOLT_POLICY_INDEX_INVALID;
165 u8 i = 0;
166
167 /* Sanity check input rail list. */
168 for (i = 0; i < prail_list->num_rails; i++) {
169 if ((prail_list->rails[i].volt_domain ==
170 CTRL_VOLT_DOMAIN_INVALID) ||
171 (prail_list->rails[i].voltage_uv ==
172 NV_PMU_VOLT_VALUE_0V_IN_UV)) {
173 gk20a_err(dev_from_gk20a(g), "Invalid voltage domain or target ");
174 gk20a_err(dev_from_gk20a(g), " client_id = %d, listEntry = %d ",
175 client_id, i);
176 gk20a_err(dev_from_gk20a(g),
177 "volt_domain = %d, voltage_uv = %d uV.",
178 prail_list->rails[i].volt_domain,
179 prail_list->rails[i].voltage_uv);
180 status = -EINVAL;
181 goto exit;
182 }
183 }
184
185 /* Convert the client ID to index. */
186 if (client_id == CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ)
187 policy_idx =
188 pvolt->volt_policy_metadata.perf_core_vf_seq_policy_idx;
189 else {
190 status = -EINVAL;
191 goto exit;
192 }
193
194 /* Set RPC parameters. */
195 rpc_call.function = NV_PMU_VOLT_RPC_ID_VOLT_POLICY_SET_VOLTAGE;
196 rpc_call.params.volt_policy_voltage_data.policy_idx = policy_idx;
197 memcpy(&rpc_call.params.volt_policy_voltage_data.rail_list, prail_list,
198 (sizeof(struct ctrl_perf_volt_rail_list)));
199
200 /* Execute the voltage change request via PMU RPC. */
201 status = volt_pmu_rpc_execute(g, &rpc_call);
202 if (status)
203 gk20a_err(dev_from_gk20a(g),
204 "Error while executing VOLT_POLICY_SET_VOLTAGE RPC");
205
206exit:
207 return status;
208}
209
210u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv, u32 sram_voltage_uv)
211{
212 u32 status = 0;
213 struct ctrl_perf_volt_rail_list rail_list = { 0 };
214
215 rail_list.num_rails = RAIL_COUNT;
216 rail_list.rails[0].volt_domain = CTRL_VOLT_DOMAIN_LOGIC;
217 rail_list.rails[0].voltage_uv = logic_voltage_uv;
218 rail_list.rails[0].voltage_min_noise_unaware_uv = logic_voltage_uv;
219 rail_list.rails[1].volt_domain = CTRL_VOLT_DOMAIN_SRAM;
220 rail_list.rails[1].voltage_uv = sram_voltage_uv;
221 rail_list.rails[1].voltage_min_noise_unaware_uv = sram_voltage_uv;
222
223 status = volt_policy_set_voltage(g,
224 CTRL_VOLT_POLICY_CLIENT_PERF_CORE_VF_SEQ, &rail_list);
225
226 return status;
227
228}
229
230u32 volt_get_voltage(struct gk20a *g, u32 volt_domain)
231{
232 u32 status = 0;
233 u32 voltage_uv = 0;
234
235 status = volt_rail_get_voltage(g, volt_domain, &voltage_uv);
236 if (status) {
237 gk20a_err(dev_from_gk20a(g),
238 "CTRL_VOLT_DOMAIN_LOGIC get voltage failed");
239 return 0;
240 }
241
242 return voltage_uv;
243}
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.h b/drivers/gpu/nvgpu/volt/volt_pmu.h
new file mode 100644
index 00000000..c98ba321
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.h
@@ -0,0 +1,22 @@
1/*
2* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14#ifndef _VOLT_PMU_H_
15#define _VOLT_PMU_H_
16
17u32 volt_pmu_send_load_cmd_to_pmu(struct gk20a *g);
18u32 volt_set_voltage(struct gk20a *g, u32 logic_voltage_uv,
19 u32 sram_voltage_uv);
20u32 volt_get_voltage(struct gk20a *g, u32 volt_domain);
21
22#endif
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c
new file mode 100644
index 00000000..ee3e74b8
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_policy.c
@@ -0,0 +1,360 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "gk20a/gk20a.h"
15#include "include/bios.h"
16#include "boardobj/boardobjgrp.h"
17#include "boardobj/boardobjgrp_e32.h"
18#include "pmuif/gpmuifboardobj.h"
19#include "gm206/bios_gm206.h"
20#include "ctrl/ctrlvolt.h"
21#include "gk20a/pmu_gk20a.h"
22
23#include "pmuif/gpmuifperfvfe.h"
24#include "include/bios.h"
25#include "volt.h"
26
27static u32 volt_policy_pmu_data_init_super(struct gk20a *g,
28 struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata)
29{
30 return boardobj_pmudatainit_super(g, pboardobj, ppmudata);
31}
32
33static u32 construct_volt_policy(struct gk20a *g,
34 struct boardobj **ppboardobj, u16 size, void *pArgs)
35{
36 struct voltage_policy *pvolt_policy = NULL;
37 u32 status = 0;
38
39 status = boardobj_construct_super(g, ppboardobj, size, pArgs);
40 if (status)
41 return status;
42
43 pvolt_policy = (struct voltage_policy *)*ppboardobj;
44
45 pvolt_policy->super.pmudatainit = volt_policy_pmu_data_init_super;
46
47 return status;
48}
49
50static u32 construct_volt_policy_split_rail(struct gk20a *g,
51 struct boardobj **ppboardobj, u16 size, void *pArgs)
52{
53 struct voltage_policy_split_rail *ptmp_policy =
54 (struct voltage_policy_split_rail *)pArgs;
55 struct voltage_policy_split_rail *pvolt_policy = NULL;
56 u32 status = 0;
57
58 status = construct_volt_policy(g, ppboardobj, size, pArgs);
59 if (status)
60 return status;
61
62 pvolt_policy = (struct voltage_policy_split_rail *)*ppboardobj;
63
64 pvolt_policy->rail_idx_master = ptmp_policy->rail_idx_master;
65 pvolt_policy->rail_idx_slave = ptmp_policy->rail_idx_slave;
66 pvolt_policy->delta_min_vfe_equ_idx =
67 ptmp_policy->delta_min_vfe_equ_idx;
68 pvolt_policy->delta_max_vfe_equ_idx =
69 ptmp_policy->delta_max_vfe_equ_idx;
70
71 return status;
72}
73
74u32 volt_policy_pmu_data_init_split_rail(struct gk20a *g,
75 struct boardobj *pboardobj, struct nv_pmu_boardobj *ppmudata)
76{
77 u32 status = 0;
78 struct voltage_policy_split_rail *ppolicy;
79 struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *pset;
80
81 status = volt_policy_pmu_data_init_super(g, pboardobj, ppmudata);
82 if (status)
83 goto done;
84
85 ppolicy = (struct voltage_policy_split_rail *)pboardobj;
86 pset = (struct nv_pmu_volt_volt_policy_splt_r_boardobj_set *)
87 ppmudata;
88
89 pset->rail_idx_master = ppolicy->rail_idx_master;
90 pset->rail_idx_slave = ppolicy->rail_idx_slave;
91 pset->delta_min_vfe_equ_idx = ppolicy->delta_min_vfe_equ_idx;
92 pset->delta_max_vfe_equ_idx = ppolicy->delta_max_vfe_equ_idx;
93 pset->offset_delta_min_uv = ppolicy->offset_delta_min_uv;
94 pset->offset_delta_max_uv = ppolicy->offset_delta_max_uv;
95
96done:
97 return status;
98}
99
100static u32 volt_construct_volt_policy_split_rail_single_step(struct gk20a *g,
101 struct boardobj **ppboardobj, u16 size, void *pargs)
102{
103 struct boardobj *pboardobj = NULL;
104 struct voltage_policy_split_rail_single_step *p_volt_policy = NULL;
105 u32 status = 0;
106
107 status = construct_volt_policy_split_rail(g, ppboardobj, size, pargs);
108 if (status)
109 return status;
110
111 pboardobj = (*ppboardobj);
112 p_volt_policy = (struct voltage_policy_split_rail_single_step *)
113 *ppboardobj;
114
115 pboardobj->pmudatainit = volt_policy_pmu_data_init_split_rail;
116
117 return status;
118}
119
120struct voltage_policy *volt_volt_policy_construct(struct gk20a *g, void *pargs)
121{
122 struct boardobj *pboard_obj = NULL;
123 u32 status = 0;
124
125 if (BOARDOBJ_GET_TYPE(pargs) ==
126 CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP) {
127 status = volt_construct_volt_policy_split_rail_single_step(g,
128 &pboard_obj,
129 sizeof(struct voltage_policy_split_rail_single_step),
130 pargs);
131 if (status) {
132 gk20a_err(dev_from_gk20a(g),
133 "Could not allocate memory for voltage_policy");
134 pboard_obj = NULL;
135 }
136 }
137
138 return (struct voltage_policy *)pboard_obj;
139}
140
141static u8 volt_policy_type_convert(u8 vbios_type)
142{
143 switch (vbios_type) {
144 case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SINGLE_RAIL:
145 return CTRL_VOLT_POLICY_TYPE_SINGLE_RAIL;
146
147 case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_MULTI_STEP:
148 return CTRL_VOLT_POLICY_TYPE_SR_MULTI_STEP;
149
150 case NV_VBIOS_VOLTAGE_POLICY_1X_ENTRY_TYPE_SR_SINGLE_STEP:
151 return CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP;
152 }
153
154 return CTRL_VOLT_POLICY_TYPE_INVALID;
155}
156
157static u32 volt_get_volt_policy_table(struct gk20a *g,
158 struct voltage_policy_metadata *pvolt_policy_metadata)
159{
160 u32 status = 0;
161 u8 *voltage_policy_table_ptr = NULL;
162 struct voltage_policy *ppolicy = NULL;
163 struct vbios_voltage_policy_table_1x_header header = { 0 };
164 struct vbios_voltage_policy_table_1x_entry entry = { 0 };
165 u8 i;
166 u8 policy_type = 0;
167 u8 *entry_offset;
168 union policy_type {
169 struct boardobj board_obj;
170 struct voltage_policy volt_policy;
171 struct voltage_policy_split_rail split_rail;
172 } policy_type_data;
173
174 if (g->ops.bios.get_perf_table_ptrs) {
175 voltage_policy_table_ptr =
176 (u8 *)g->ops.bios.get_perf_table_ptrs(g,
177 g->bios.perf_token, VOLTAGE_POLICY_TABLE);
178 if (voltage_policy_table_ptr == NULL) {
179 status = -EINVAL;
180 goto done;
181 }
182 } else {
183 status = -EINVAL;
184 goto done;
185 }
186
187 memcpy(&header, voltage_policy_table_ptr,
188 sizeof(struct vbios_voltage_policy_table_1x_header));
189
190 /* Set Voltage Policy Table Index for Perf Core VF Sequence client. */
191 pvolt_policy_metadata->perf_core_vf_seq_policy_idx =
192 (u8)header.perf_core_vf_seq_policy_idx;
193
194 /* Read in the entries. */
195 for (i = 0; i < header.num_table_entries; i++) {
196 entry_offset = (voltage_policy_table_ptr + header.header_size +
197 i * header.table_entry_size);
198
199 memcpy(&entry, entry_offset,
200 sizeof(struct vbios_voltage_policy_table_1x_entry));
201
202 memset(&policy_type_data, 0x0, sizeof(policy_type_data));
203
204 policy_type = volt_policy_type_convert((u8)entry.type);
205
206 if (policy_type == CTRL_VOLT_POLICY_TYPE_SR_SINGLE_STEP) {
207 policy_type_data.split_rail.rail_idx_master =
208 (u8)BIOS_GET_FIELD(entry.param0,
209 NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_MASTER);
210
211 policy_type_data.split_rail.rail_idx_slave =
212 (u8)BIOS_GET_FIELD(entry.param0,
213 NV_VBIOS_VPT_ENTRY_PARAM0_SR_VD_SLAVE);
214
215 policy_type_data.split_rail.delta_min_vfe_equ_idx =
216 (u8)BIOS_GET_FIELD(entry.param0,
217 NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MIN);
218
219 policy_type_data.split_rail.delta_max_vfe_equ_idx =
220 (u8)BIOS_GET_FIELD(entry.param0,
221 NV_VBIOS_VPT_ENTRY_PARAM0_SR_DELTA_SM_MAX);
222 }
223
224 policy_type_data.board_obj.type = policy_type;
225
226 ppolicy = volt_volt_policy_construct(g,
227 (void *)&policy_type_data);
228 if (ppolicy == NULL) {
229 gk20a_err(dev_from_gk20a(g),
230 "Failure to construct VOLT_POLICY object.");
231 status = -EINVAL;
232 goto done;
233 }
234
235 status = boardobjgrp_objinsert(
236 &pvolt_policy_metadata->volt_policies.super,
237 (struct boardobj *)ppolicy, i);
238 if (status) {
239 gk20a_err(dev_from_gk20a(g),
240 "could not add volt_policy for entry %d into boardobjgrp ",
241 i);
242 goto done;
243 }
244 }
245
246done:
247 return status;
248}
249static u32 _volt_policy_devgrp_pmudata_instget(struct gk20a *g,
250 struct nv_pmu_boardobjgrp *pmuboardobjgrp,
251 struct nv_pmu_boardobj **ppboardobjpmudata, u8 idx)
252{
253 struct nv_pmu_volt_volt_policy_boardobj_grp_set *pgrp_set =
254 (struct nv_pmu_volt_volt_policy_boardobj_grp_set *)
255 pmuboardobjgrp;
256
257 gk20a_dbg_info("");
258
259 /*check whether pmuboardobjgrp has a valid boardobj in index*/
260 if (((u32)BIT(idx) &
261 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
262 return -EINVAL;
263
264 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
265 &pgrp_set->objects[idx].data.board_obj;
266 gk20a_dbg_info(" Done");
267 return 0;
268}
269
270static u32 _volt_policy_devgrp_pmustatus_instget(struct gk20a *g,
271 void *pboardobjgrppmu,
272 struct nv_pmu_boardobj_query **ppboardobjpmustatus, u8 idx)
273{
274 struct nv_pmu_volt_volt_policy_boardobj_grp_get_status *p_get_status =
275 (struct nv_pmu_volt_volt_policy_boardobj_grp_get_status *)
276 pboardobjgrppmu;
277
278 /*check whether pmuboardobjgrp has a valid boardobj in index*/
279 if (((u32)BIT(idx) &
280 p_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
281 return -EINVAL;
282
283 *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
284 &p_get_status->objects[idx].data.board_obj;
285 return 0;
286}
287
288u32 volt_policy_pmu_setup(struct gk20a *g)
289{
290 u32 status;
291 struct boardobjgrp *pboardobjgrp = NULL;
292
293 gk20a_dbg_info("");
294
295 pboardobjgrp =
296 &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super;
297
298 if (!pboardobjgrp->bconstructed)
299 return -EINVAL;
300
301 status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
302
303 gk20a_dbg_info("Done");
304 return status;
305}
306
307u32 volt_policy_sw_setup(struct gk20a *g)
308{
309 u32 status = 0;
310 struct boardobjgrp *pboardobjgrp = NULL;
311
312 gk20a_dbg_info("");
313
314 status = boardobjgrpconstruct_e32(
315 &g->perf_pmu.volt.volt_policy_metadata.volt_policies);
316 if (status) {
317 gk20a_err(dev_from_gk20a(g),
318 "error creating boardobjgrp for volt rail, status - 0x%x",
319 status);
320 goto done;
321 }
322
323 pboardobjgrp =
324 &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super;
325
326 pboardobjgrp->pmudatainstget = _volt_policy_devgrp_pmudata_instget;
327 pboardobjgrp->pmustatusinstget = _volt_policy_devgrp_pmustatus_instget;
328
329 /* Obtain Voltage Rail Table from VBIOS */
330 status = volt_get_volt_policy_table(g, &g->perf_pmu.volt.
331 volt_policy_metadata);
332 if (status)
333 goto done;
334
335 /* Populate data for the VOLT_RAIL PMU interface */
336 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_POLICY);
337
338 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
339 volt, VOLT, volt_policy, VOLT_POLICY);
340 if (status) {
341 gk20a_err(dev_from_gk20a(g),
342 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
343 status);
344 goto done;
345 }
346
347 status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
348 &g->perf_pmu.volt.volt_policy_metadata.volt_policies.super,
349 volt, VOLT, volt_policy, VOLT_POLICY);
350 if (status) {
351 gk20a_err(dev_from_gk20a(g),
352 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
353 status);
354 goto done;
355 }
356
357done:
358 gk20a_dbg_info(" done status %x", status);
359 return status;
360}
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.h b/drivers/gpu/nvgpu/volt/volt_policy.h
new file mode 100644
index 00000000..6adbfd43
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_policy.h
@@ -0,0 +1,64 @@
1/*
2* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14#ifndef _VOLT_POLICY_H_
15#define _VOLT_POLICY_H_
16
17#define VOLT_POLICY_INDEX_IS_VALID(pvolt, policy_idx) \
18 (boardobjgrp_idxisvalid( \
19 &((pvolt)->volt_policy_metadata.volt_policies.super), \
20 (policy_idx)))
21
22/*!
23 * extends boardobj providing attributes common to all voltage_policies.
24 */
25struct voltage_policy {
26 struct boardobj super;
27};
28
29struct voltage_policy_metadata {
30 u8 perf_core_vf_seq_policy_idx;
31 struct boardobjgrp_e32 volt_policies;
32};
33
34/*!
35 * extends voltage_policy providing attributes
36 * common to all voltage_policy_split_rail.
37 */
38struct voltage_policy_split_rail {
39 struct voltage_policy super;
40 u8 rail_idx_master;
41 u8 rail_idx_slave;
42 u8 delta_min_vfe_equ_idx;
43 u8 delta_max_vfe_equ_idx;
44 s32 offset_delta_min_uv;
45 s32 offset_delta_max_uv;
46};
47
48struct voltage_policy_split_rail_single_step {
49 struct voltage_policy_split_rail super;
50};
51
52struct voltage_policy_split_rail_multi_step {
53 struct voltage_policy_split_rail super;
54 u16 inter_switch_delay_us;
55};
56
57struct voltage_policy_single_rail {
58 struct voltage_policy super;
59 u8 rail_idx;
60};
61
62u32 volt_policy_sw_setup(struct gk20a *g);
63u32 volt_policy_pmu_setup(struct gk20a *g);
64#endif
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c
new file mode 100644
index 00000000..87b85160
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_rail.c
@@ -0,0 +1,438 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "gk20a/gk20a.h"
15#include "include/bios.h"
16#include "boardobj/boardobjgrp.h"
17#include "boardobj/boardobjgrp_e32.h"
18#include "pmuif/gpmuifboardobj.h"
19#include "gm206/bios_gm206.h"
20#include "ctrl/ctrlvolt.h"
21#include "gk20a/pmu_gk20a.h"
22
23#include "pmuif/gpmuifperfvfe.h"
24#include "include/bios.h"
25#include "volt.h"
26
27u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
28{
29 switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) {
30 case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
31 if (volt_domain == CTRL_BOARDOBJ_IDX_INVALID)
32 return 0;
33 break;
34 case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
35 switch (volt_domain) {
36 case CTRL_VOLT_DOMAIN_LOGIC:
37 return 0;
38 case CTRL_VOLT_DOMAIN_SRAM:
39 return 1;
40 }
41 break;
42 }
43
44 return CTRL_BOARDOBJ_IDX_INVALID;
45}
46
47u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
48 *pvolt_rail, u8 volt_dev_idx, u8 operation_type)
49{
50 u32 status = 0;
51
52 if (operation_type == CTRL_VOLT_DEVICE_OPERATION_TYPE_DEFAULT) {
53 if (pvolt_rail->volt_dev_idx_default ==
54 CTRL_BOARDOBJ_IDX_INVALID) {
55 pvolt_rail->volt_dev_idx_default = volt_dev_idx;
56 } else {
57 status = -EINVAL;
58 goto exit;
59 }
60 } else {
61 goto exit;
62 }
63
64 status = boardobjgrpmask_bitset(&pvolt_rail->volt_dev_mask.super,
65 volt_dev_idx);
66
67exit:
68 if (status)
69 gk20a_err(dev_from_gk20a(g), "Failed to register VOLTAGE_DEVICE");
70
71 return status;
72}
73
74static u32 volt_rail_state_init(struct gk20a *g,
75 struct voltage_rail *pvolt_rail)
76{
77 u32 status = 0;
78 u32 i;
79
80 pvolt_rail->volt_dev_idx_default = CTRL_BOARDOBJ_IDX_INVALID;
81
82 for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
83 pvolt_rail->volt_delta_uv[i] = NV_PMU_VOLT_VALUE_0V_IN_UV;
84 g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i] =
85 NV_PMU_VOLT_VALUE_0V_IN_UV;
86 }
87
88 pvolt_rail->volt_margin_limit_vfe_equ_mon_handle =
89 NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX;
90 pvolt_rail->rel_limit_vfe_equ_mon_handle =
91 NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX;
92 pvolt_rail->alt_rel_limit_vfe_equ_mon_handle =
93 NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX;
94 pvolt_rail->ov_limit_vfe_equ_mon_handle =
95 NV_PMU_PERF_RPC_VFE_EQU_MONITOR_COUNT_MAX;
96
97 status = boardobjgrpmask_e32_init(&pvolt_rail->volt_dev_mask, NULL);
98 if (status) {
99 gk20a_err(dev_from_gk20a(g),
100 "Failed to initialize BOARDOBJGRPMASK of VOLTAGE_DEVICEs");
101 }
102
103 return status;
104}
105
106static u32 volt_rail_init_pmudata_super(struct gk20a *g,
107 struct boardobj *board_obj_ptr, struct nv_pmu_boardobj *ppmudata)
108{
109 u32 status = 0;
110 struct voltage_rail *prail;
111 struct nv_pmu_volt_volt_rail_boardobj_set *rail_pmu_data;
112 u32 i;
113
114 gk20a_dbg_info("");
115
116 status = boardobj_pmudatainit_super(g, board_obj_ptr, ppmudata);
117 if (status)
118 return status;
119
120 prail = (struct voltage_rail *)board_obj_ptr;
121 rail_pmu_data = (struct nv_pmu_volt_volt_rail_boardobj_set *)
122 ppmudata;
123
124 rail_pmu_data->rel_limit_vfe_equ_idx = prail->rel_limit_vfe_equ_idx;
125 rail_pmu_data->alt_rel_limit_vfe_equ_idx =
126 prail->alt_rel_limit_vfe_equ_idx;
127 rail_pmu_data->ov_limit_vfe_equ_idx = prail->ov_limit_vfe_equ_idx;
128 rail_pmu_data->vmin_limit_vfe_equ_idx = prail->vmin_limit_vfe_equ_idx;
129 rail_pmu_data->volt_margin_limit_vfe_equ_idx =
130 prail->volt_margin_limit_vfe_equ_idx;
131 rail_pmu_data->pwr_equ_idx = prail->pwr_equ_idx;
132 rail_pmu_data->volt_dev_idx_default = prail->volt_dev_idx_default;
133
134 for (i = 0; i < CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES; i++) {
135 rail_pmu_data->volt_delta_uv[i] = prail->volt_delta_uv[i] +
136 g->perf_pmu.volt.volt_rail_metadata.ext_rel_delta_uv[i];
137 }
138
139 status = boardobjgrpmask_export(&prail->volt_dev_mask.super,
140 prail->volt_dev_mask.super.bitcount,
141 &rail_pmu_data->volt_dev_mask.super);
142 if (status)
143 gk20a_err(dev_from_gk20a(g),
144 "Failed to export BOARDOBJGRPMASK of VOLTAGE_DEVICEs");
145
146 gk20a_dbg_info("Done");
147
148 return status;
149}
150
151static struct voltage_rail *construct_volt_rail(struct gk20a *g, void *pargs)
152{
153 struct boardobj *board_obj_ptr = NULL;
154 struct voltage_rail *ptemp_rail = (struct voltage_rail *)pargs;
155 struct voltage_rail *board_obj_volt_rail_ptr = NULL;
156 u32 status;
157
158 gk20a_dbg_info("");
159 status = boardobj_construct_super(g, &board_obj_ptr,
160 sizeof(struct voltage_rail), pargs);
161 if (status)
162 return NULL;
163
164 board_obj_volt_rail_ptr = (struct voltage_rail *)board_obj_ptr;
165 /* override super class interface */
166 board_obj_ptr->pmudatainit = volt_rail_init_pmudata_super;
167
168 board_obj_volt_rail_ptr->boot_voltage_uv =
169 ptemp_rail->boot_voltage_uv;
170 board_obj_volt_rail_ptr->rel_limit_vfe_equ_idx =
171 ptemp_rail->rel_limit_vfe_equ_idx;
172 board_obj_volt_rail_ptr->alt_rel_limit_vfe_equ_idx =
173 ptemp_rail->alt_rel_limit_vfe_equ_idx;
174 board_obj_volt_rail_ptr->ov_limit_vfe_equ_idx =
175 ptemp_rail->ov_limit_vfe_equ_idx;
176 board_obj_volt_rail_ptr->pwr_equ_idx =
177 ptemp_rail->pwr_equ_idx;
178 board_obj_volt_rail_ptr->boot_volt_vfe_equ_idx =
179 ptemp_rail->boot_volt_vfe_equ_idx;
180 board_obj_volt_rail_ptr->vmin_limit_vfe_equ_idx =
181 ptemp_rail->vmin_limit_vfe_equ_idx;
182 board_obj_volt_rail_ptr->volt_margin_limit_vfe_equ_idx =
183 ptemp_rail->volt_margin_limit_vfe_equ_idx;
184
185 gk20a_dbg_info("Done");
186
187 return (struct voltage_rail *)board_obj_ptr;
188}
189
190u8 volt_rail_vbios_volt_domain_convert_to_internal(struct gk20a *g,
191 u8 vbios_volt_domain)
192{
193 switch (g->perf_pmu.volt.volt_rail_metadata.volt_domain_hal) {
194 case CTRL_VOLT_DOMAIN_HAL_GP10X_SINGLE_RAIL:
195 if (vbios_volt_domain == 0)
196 return CTRL_VOLT_DOMAIN_LOGIC;
197 break;
198 case CTRL_VOLT_DOMAIN_HAL_GP10X_SPLIT_RAIL:
199 switch (vbios_volt_domain) {
200 case 0:
201 return CTRL_VOLT_DOMAIN_LOGIC;
202 case 1:
203 return CTRL_VOLT_DOMAIN_SRAM;
204 }
205 break;
206 }
207
208 return CTRL_VOLT_DOMAIN_INVALID;
209}
210
211u32 volt_rail_pmu_setup(struct gk20a *g)
212{
213 u32 status;
214 struct boardobjgrp *pboardobjgrp = NULL;
215
216 gk20a_dbg_info("");
217
218 pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super;
219
220 if (!pboardobjgrp->bconstructed)
221 return -EINVAL;
222
223 status = pboardobjgrp->pmuinithandle(g, pboardobjgrp);
224
225 gk20a_dbg_info("Done");
226 return status;
227}
228
229static u32 volt_get_volt_rail_table(struct gk20a *g,
230 struct voltage_rail_metadata *pvolt_rail_metadata)
231{
232 u32 status = 0;
233 u8 *volt_rail_table_ptr = NULL;
234 struct voltage_rail *prail = NULL;
235 struct vbios_voltage_rail_table_1x_header header = { 0 };
236 struct vbios_voltage_rail_table_1x_entry entry = { 0 };
237 u8 i;
238 u8 volt_domain;
239 u8 *entry_ptr;
240 union rail_type {
241 struct boardobj board_obj;
242 struct voltage_rail volt_rail;
243 } rail_type_data;
244
245 if (g->ops.bios.get_perf_table_ptrs) {
246 volt_rail_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
247 g->bios.perf_token, VOLTAGE_RAIL_TABLE);
248 if (volt_rail_table_ptr == NULL) {
249 status = -EINVAL;
250 goto done;
251 }
252 } else {
253 status = -EINVAL;
254 goto done;
255 }
256
257 memcpy(&header, volt_rail_table_ptr,
258 sizeof(struct vbios_voltage_rail_table_1x_header));
259
260 pvolt_rail_metadata->volt_domain_hal = (u8)header.volt_domain_hal;
261
262 for (i = 0; i < header.num_table_entries; i++) {
263 entry_ptr = (volt_rail_table_ptr + header.header_size +
264 (i * header.table_entry_size));
265
266 memset(&rail_type_data, 0x0, sizeof(rail_type_data));
267
268 memcpy(&entry, entry_ptr,
269 sizeof(struct vbios_voltage_rail_table_1x_entry));
270
271 volt_domain = volt_rail_vbios_volt_domain_convert_to_internal(g,
272 i);
273 if (volt_domain == CTRL_VOLT_DOMAIN_INVALID)
274 continue;
275
276 rail_type_data.board_obj.type = volt_domain;
277 rail_type_data.volt_rail.boot_voltage_uv =
278 (u32)entry.boot_voltage_uv;
279 rail_type_data.volt_rail.rel_limit_vfe_equ_idx =
280 (u8)entry.rel_limit_vfe_equ_idx;
281 rail_type_data.volt_rail.alt_rel_limit_vfe_equ_idx =
282 (u8)entry.alt_rel_limit_vfe_equidx;
283 rail_type_data.volt_rail.ov_limit_vfe_equ_idx =
284 (u8)entry.ov_limit_vfe_equ_idx;
285
286 if (header.table_entry_size >=
287 NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0B)
288 rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx =
289 (u8)entry.volt_margin_limit_vfe_equ_idx;
290 else
291 rail_type_data.volt_rail.volt_margin_limit_vfe_equ_idx =
292 CTRL_BOARDOBJ_IDX_INVALID;
293
294 if (header.table_entry_size >=
295 NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_0A)
296 rail_type_data.volt_rail.vmin_limit_vfe_equ_idx =
297 (u8)entry.vmin_limit_vfe_equ_idx;
298 else
299 rail_type_data.volt_rail.vmin_limit_vfe_equ_idx =
300 CTRL_BOARDOBJ_IDX_INVALID;
301
302 if (header.table_entry_size >=
303 NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_09)
304 rail_type_data.volt_rail.boot_volt_vfe_equ_idx =
305 (u8)entry.boot_volt_vfe_equ_idx;
306 else
307 rail_type_data.volt_rail.boot_volt_vfe_equ_idx =
308 CTRL_BOARDOBJ_IDX_INVALID;
309
310 if (header.table_entry_size >=
311 NV_VBIOS_VOLTAGE_RAIL_1X_ENTRY_SIZE_08)
312 rail_type_data.volt_rail.pwr_equ_idx =
313 (u8)entry.pwr_equ_idx;
314 else
315 rail_type_data.volt_rail.pwr_equ_idx =
316 CTRL_PMGR_PWR_EQUATION_INDEX_INVALID;
317
318 prail = construct_volt_rail(g, &rail_type_data);
319
320 status = boardobjgrp_objinsert(
321 &pvolt_rail_metadata->volt_rails.super,
322 (struct boardobj *)prail, i);
323 }
324
325done:
326 return status;
327}
328
329static u32 _volt_rail_devgrp_pmudata_instget(struct gk20a *g,
330 struct nv_pmu_boardobjgrp *pmuboardobjgrp, struct nv_pmu_boardobj
331 **ppboardobjpmudata, u8 idx)
332{
333 struct nv_pmu_volt_volt_rail_boardobj_grp_set *pgrp_set =
334 (struct nv_pmu_volt_volt_rail_boardobj_grp_set *)
335 pmuboardobjgrp;
336
337 gk20a_dbg_info("");
338
339 /*check whether pmuboardobjgrp has a valid boardobj in index*/
340 if (((u32)BIT(idx) &
341 pgrp_set->hdr.data.super.obj_mask.super.data[0]) == 0)
342 return -EINVAL;
343
344 *ppboardobjpmudata = (struct nv_pmu_boardobj *)
345 &pgrp_set->objects[idx].data.board_obj;
346 gk20a_dbg_info(" Done");
347 return 0;
348}
349
350static u32 _volt_rail_devgrp_pmustatus_instget(struct gk20a *g,
351 void *pboardobjgrppmu, struct nv_pmu_boardobj_query
352 **ppboardobjpmustatus, u8 idx)
353{
354 struct nv_pmu_volt_volt_rail_boardobj_grp_get_status *pgrp_get_status =
355 (struct nv_pmu_volt_volt_rail_boardobj_grp_get_status *)
356 pboardobjgrppmu;
357
358 /*check whether pmuboardobjgrp has a valid boardobj in index*/
359 if (((u32)BIT(idx) &
360 pgrp_get_status->hdr.data.super.obj_mask.super.data[0]) == 0)
361 return -EINVAL;
362
363 *ppboardobjpmustatus = (struct nv_pmu_boardobj_query *)
364 &pgrp_get_status->objects[idx].data.board_obj;
365 return 0;
366}
367
368u32 volt_rail_sw_setup(struct gk20a *g)
369{
370 u32 status = 0;
371 struct boardobjgrp *pboardobjgrp = NULL;
372 struct voltage_rail *pvolt_rail;
373 u8 i;
374
375 gk20a_dbg_info("");
376
377 status = boardobjgrpconstruct_e32(&g->perf_pmu.volt.volt_rail_metadata.
378 volt_rails);
379 if (status) {
380 gk20a_err(dev_from_gk20a(g),
381 "error creating boardobjgrp for volt rail, status - 0x%x",
382 status);
383 goto done;
384 }
385
386 pboardobjgrp = &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super;
387
388 pboardobjgrp->pmudatainstget = _volt_rail_devgrp_pmudata_instget;
389 pboardobjgrp->pmustatusinstget = _volt_rail_devgrp_pmustatus_instget;
390
391 g->perf_pmu.volt.volt_rail_metadata.pct_delta =
392 NV_PMU_VOLT_VALUE_0V_IN_UV;
393
394 /* Obtain Voltage Rail Table from VBIOS */
395 status = volt_get_volt_rail_table(g, &g->perf_pmu.volt.
396 volt_rail_metadata);
397 if (status)
398 goto done;
399
400 /* Populate data for the VOLT_RAIL PMU interface */
401 BOARDOBJGRP_PMU_CONSTRUCT(pboardobjgrp, VOLT, VOLT_RAIL);
402
403 status = BOARDOBJGRP_PMU_CMD_GRP_SET_CONSTRUCT(g, pboardobjgrp,
404 volt, VOLT, volt_rail, VOLT_RAIL);
405 if (status) {
406 gk20a_err(dev_from_gk20a(g),
407 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
408 status);
409 goto done;
410 }
411
412 status = BOARDOBJGRP_PMU_CMD_GRP_GET_STATUS_CONSTRUCT(g,
413 &g->perf_pmu.volt.volt_rail_metadata.volt_rails.super,
414 volt, VOLT, volt_rail, VOLT_RAIL);
415 if (status) {
416 gk20a_err(dev_from_gk20a(g),
417 "error constructing PMU_BOARDOBJ_CMD_GRP_SET interface - 0x%x",
418 status);
419 goto done;
420 }
421
422 /* update calibration to fuse */
423 BOARDOBJGRP_FOR_EACH(&(g->perf_pmu.volt.volt_rail_metadata.
424 volt_rails.super),
425 struct voltage_rail *, pvolt_rail, i) {
426 status = volt_rail_state_init(g, pvolt_rail);
427 if (status) {
428 gk20a_err(dev_from_gk20a(g),
429 "Failure while executing RAIL's state init railIdx = %d",
430 i);
431 goto done;
432 }
433 }
434
435done:
436 gk20a_dbg_info(" done status %x", status);
437 return status;
438}
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.h b/drivers/gpu/nvgpu/volt/volt_rail.h
new file mode 100644
index 00000000..0180992c
--- /dev/null
+++ b/drivers/gpu/nvgpu/volt/volt_rail.h
@@ -0,0 +1,77 @@
1/*
2* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3*
4* This program is free software; you can redistribute it and/or modify it
5* under the terms and conditions of the GNU General Public License,
6* version 2, as published by the Free Software Foundation.
7*
8* This program is distributed in the hope it will be useful, but WITHOUT
9* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11* more details.
12*/
13
14
15#ifndef _VOLT_RAIL_H_
16#define _VOLT_RAIL_H_
17
18#include "boardobj/boardobj.h"
19#include "boardobj/boardobjgrp.h"
20
21#define CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES 0x04
22#define CTRL_PMGR_PWR_EQUATION_INDEX_INVALID 0xFF
23
24#define VOLT_GET_VOLT_RAIL(pvolt, rail_idx) \
25 ((struct voltage_rail *)BOARDOBJGRP_OBJ_GET_BY_IDX( \
26 &((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
27
28#define VOLT_RAIL_INDEX_IS_VALID(pvolt, rail_idx) \
29 (boardobjgrp_idxisvalid( \
30 &((pvolt)->volt_rail_metadata.volt_rails.super), (rail_idx)))
31
32#define VOLT_RAIL_VOLT_3X_SUPPORTED(pvolt) \
33 (!BOARDOBJGRP_IS_EMPTY(&((pvolt)->volt_rail_metadata.volt_rails.super)))
34
35/*!
36 * extends boardobj providing attributes common to all voltage_rails.
37 */
38struct voltage_rail {
39 struct boardobj super;
40 u32 boot_voltage_uv;
41 u8 rel_limit_vfe_equ_idx;
42 u8 alt_rel_limit_vfe_equ_idx;
43 u8 ov_limit_vfe_equ_idx;
44 u8 pwr_equ_idx;
45 u8 volt_dev_idx_default;
46 u8 boot_volt_vfe_equ_idx;
47 u8 vmin_limit_vfe_equ_idx;
48 u8 volt_margin_limit_vfe_equ_idx;
49 u32 volt_margin_limit_vfe_equ_mon_handle;
50 u32 rel_limit_vfe_equ_mon_handle;
51 u32 alt_rel_limit_vfe_equ_mon_handle;
52 u32 ov_limit_vfe_equ_mon_handle;
53 struct boardobjgrpmask_e32 volt_dev_mask;
54 s32 volt_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
55};
56
57/*!
58 * metadata of voltage rail functionality.
59 */
60struct voltage_rail_metadata {
61 u8 volt_domain_hal;
62 u8 pct_delta;
63 u32 ext_rel_delta_uv[CTRL_VOLT_RAIL_VOLT_DELTA_MAX_ENTRIES];
64 struct boardobjgrp_e32 volt_rails;
65};
66
67u8 volt_rail_vbios_volt_domain_convert_to_internal
68 (struct gk20a *g, u8 vbios_volt_domain);
69
70u32 volt_rail_volt_dev_register(struct gk20a *g, struct voltage_rail
71 *pvolt_rail, u8 volt_dev_idx, u8 operation_type);
72
73u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain);
74
75u32 volt_rail_sw_setup(struct gk20a *g);
76u32 volt_rail_pmu_setup(struct gk20a *g);
77#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 20:42:44 -0400