gpu: nvgpu: post BPT_INT/PAUSE and BLOCKING_SYNC events

Post EVENT_ID_BPT_INT when bpt.int is pending
Post EVENT_ID_BPT_PAUSE when bpt.pause is pending
Post EVENT_ID_BLOCKING_SYNC whenever there is
non-stalling semaphore interrupt indicating work
completion from GR/CE2 engine

Bug 200089620

Change-Id: I91b7bf48f8585f0d318298fc0c4a66d42055f0a7
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1112274
(cherry picked from commit d2b744b1f9acac56435cd7e7ab9a7a845579ef24)
Reviewed-on: http://git-master/r/1120321
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

8 files changed, 44 insertions, 8 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
index 3a0f20a9..a3b02481 100644
--- a/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/ce2_gk20a.c
@@ -87,7 +87,7 @@ void gk20a_ce2_nonstall_isr(struct gk20a *g)
                         ce2_nonblockpipe_isr(g, ce2_intr));
 
                 /* wake threads waiting in this channel */
-                gk20a_channel_semaphore_wakeup(g);
+                gk20a_channel_semaphore_wakeup(g, true);
         }
 
         return;
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 468ee7f1..da73d95d 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -2831,7 +2831,7 @@ int gk20a_channel_resume(struct gk20a *g)
         return 0;
 }
 
-void gk20a_channel_semaphore_wakeup(struct gk20a *g)
+void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events)
 {
         struct fifo_gk20a *f = &g->fifo;
         u32 chid;
@@ -2842,6 +2842,18 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g)
                 struct channel_gk20a *c = g->fifo.channel+chid;
                 if (gk20a_channel_get(c)) {
                         wake_up_interruptible_all(&c->semaphore_wq);
+                        if (post_events) {
+                                if (gk20a_is_channel_marked_as_tsg(c)) {
+                                        struct tsg_gk20a *tsg =
+                                                &g->fifo.tsg[c->tsgid];
+
+                                        gk20a_tsg_event_id_post_event(tsg,
+                                            NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC);
+                                } else {
+                                        gk20a_channel_event_id_post_event(c,
+                                            NVGPU_IOCTL_CHANNEL_EVENT_ID_BLOCKING_SYNC);
+                                }
+                        }
                         gk20a_channel_update(c, 0);
                         gk20a_channel_put(c);
                 }
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
index ca11739e..29c39160 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h
@@ -215,7 +215,7 @@ void gk20a_disable_channel(struct channel_gk20a *ch);
 void gk20a_channel_abort(struct channel_gk20a *ch, bool channel_preempt);
 int gk20a_channel_finish(struct channel_gk20a *ch, unsigned long timeout);
 void gk20a_set_error_notifier(struct channel_gk20a *ch, __u32 error);
-void gk20a_channel_semaphore_wakeup(struct gk20a *g);
+void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events);
 int gk20a_channel_alloc_priv_cmdbuf(struct channel_gk20a *c, u32 size,
                              struct priv_cmd_entry **entry);
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 029a713f..9421c017 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1737,7 +1737,7 @@ static u32 gk20a_fifo_handle_pbdma_intr(struct device *dev,
 
 static u32 fifo_channel_isr(struct gk20a *g, u32 fifo_intr)
 {
-        gk20a_channel_semaphore_wakeup(g);
+        gk20a_channel_semaphore_wakeup(g, false);
         return fifo_intr_0_channel_intr_pending_f();
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 56d1d505..116fd88f 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5313,6 +5313,30 @@ int gr_gk20a_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
                 return -EFAULT;
         }
 
+        if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) {
+                if (gk20a_is_channel_marked_as_tsg(fault_ch)) {
+                        struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid];
+
+                        gk20a_tsg_event_id_post_event(tsg,
+                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT);
+                } else {
+                        gk20a_channel_event_id_post_event(fault_ch,
+                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_INT);
+                }
+        }
+
+        if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) {
+                if (gk20a_is_channel_marked_as_tsg(fault_ch)) {
+                        struct tsg_gk20a *tsg = &g->fifo.tsg[fault_ch->tsgid];
+
+                        gk20a_tsg_event_id_post_event(tsg,
+                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE);
+                } else {
+                        gk20a_channel_event_id_post_event(fault_ch,
+                                NVGPU_IOCTL_CHANNEL_EVENT_ID_BPT_PAUSE);
+                }
+        }
+
         gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg,
                   "sm hww global %08x warp %08x", global_esr, warp_esr);
 
@@ -5705,7 +5729,7 @@ int gk20a_gr_nonstall_isr(struct gk20a *g)
                 gk20a_writel(g, gr_intr_nonstall_r(),
                         gr_intr_nonstall_trap_pending_f());
                 /* Wakeup all the waiting channels */
-                gk20a_channel_semaphore_wakeup(g);
+                gk20a_channel_semaphore_wakeup(g, true);
         }
 
         return 0;
diff --git a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c
index 631461f9..5291e0f5 100644
--- a/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/ce2_vgpu.c
@@ -22,7 +22,7 @@ int vgpu_ce2_nonstall_isr(struct gk20a *g,
 
         switch (info->type) {
         case TEGRA_VGPU_CE2_NONSTALL_INTR_NONBLOCKPIPE:
-                gk20a_channel_semaphore_wakeup(g);
+                gk20a_channel_semaphore_wakeup(g, true);
                 break;
         default:
                 WARN_ON(1);
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
index d81e965c..afe3c24b 100644
--- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c
@@ -653,7 +653,7 @@ int vgpu_fifo_nonstall_isr(struct gk20a *g,
 
         switch (info->type) {
         case TEGRA_VGPU_FIFO_NONSTALL_INTR_CHANNEL:
-                gk20a_channel_semaphore_wakeup(g);
+                gk20a_channel_semaphore_wakeup(g, false);
                 break;
         default:
                 WARN_ON(1);
diff --git a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
index 3baa420f..32e451ed 100644
--- a/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
+++ b/drivers/gpu/nvgpu/vgpu/gr_vgpu.c
@@ -919,7 +919,7 @@ int vgpu_gr_nonstall_isr(struct gk20a *g,
 
         switch (info->type) {
         case TEGRA_VGPU_GR_NONSTALL_INTR_SEMAPHORE:
-                gk20a_channel_semaphore_wakeup(g);
+                gk20a_channel_semaphore_wakeup(g, true);
                 break;
         default:
                 WARN_ON(1);