diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-05-24 05:02:09 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-26 19:06:30 -0400 |
commit | 147330c2dac6ffaed78100a7ad46907d7e622dca (patch) | |
tree | cf65b851286f9dc240c17f941957ab49d1022167 /drivers | |
parent | e9d5e7dfca6ac2fa7af380ceea0a0ca4ac3827c6 (diff) |
gpu: nvgpu: move & rename acr_gm20b to acr_desc
acr_gm20b renamed to acr_desc to support
multiple gpu chips
JIRA DNVGPU-10
Change-Id: Ib3b38d5845043f026ddc365a682b7bb454463326
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1152401
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/acr.h | 38 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 5 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 18 |
4 files changed, 44 insertions, 23 deletions
diff --git a/drivers/gpu/nvgpu/acr.h b/drivers/gpu/nvgpu/acr.h new file mode 100644 index 00000000..ad859858 --- /dev/null +++ b/drivers/gpu/nvgpu/acr.h | |||
@@ -0,0 +1,38 @@ | |||
1 | /* | ||
2 | * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved. | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify it | ||
5 | * under the terms and conditions of the GNU General Public License, | ||
6 | * version 2, as published by the Free Software Foundation. | ||
7 | * | ||
8 | * This program is distributed in the hope it will be useful, but WITHOUT | ||
9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | ||
10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | ||
11 | * more details. | ||
12 | */ | ||
13 | |||
14 | #ifndef __ACR_H_ | ||
15 | #define __ACR_H_ | ||
16 | |||
17 | #include "gm20b/mm_gm20b.h" | ||
18 | #include "gm20b/acr_gm20b.h" | ||
19 | |||
20 | struct acr_desc { | ||
21 | struct mem_desc ucode_blob; | ||
22 | struct bin_hdr *bl_bin_hdr; | ||
23 | struct hsflcn_bl_desc *pmu_hsbl_desc; | ||
24 | struct bin_hdr *hsbin_hdr; | ||
25 | struct acr_fw_header *fw_hdr; | ||
26 | u32 pmu_args; | ||
27 | const struct firmware *acr_fw; | ||
28 | struct flcn_acr_desc *acr_dmem_desc; | ||
29 | struct mem_desc acr_ucode; | ||
30 | const struct firmware *hsbl_fw; | ||
31 | struct mem_desc hsbl_ucode; | ||
32 | struct flcn_bl_dmem_desc bl_dmem_desc; | ||
33 | const struct firmware *pmu_fw; | ||
34 | const struct firmware *pmu_desc; | ||
35 | u32 capabilities; | ||
36 | }; | ||
37 | |||
38 | #endif /*__ACR_H_*/ | ||
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index d96ce3d8..56f8fddb 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -26,7 +26,7 @@ struct sim_gk20a; | |||
26 | struct gk20a_ctxsw_ucode_segments; | 26 | struct gk20a_ctxsw_ucode_segments; |
27 | struct gk20a_fecs_trace; | 27 | struct gk20a_fecs_trace; |
28 | struct gk20a_ctxsw_trace; | 28 | struct gk20a_ctxsw_trace; |
29 | struct acr_gm20b; | 29 | struct acr_desc; |
30 | 30 | ||
31 | #include <linux/sched.h> | 31 | #include <linux/sched.h> |
32 | #include <linux/spinlock.h> | 32 | #include <linux/spinlock.h> |
@@ -49,6 +49,7 @@ struct acr_gm20b; | |||
49 | #include "therm_gk20a.h" | 49 | #include "therm_gk20a.h" |
50 | #include "platform_gk20a.h" | 50 | #include "platform_gk20a.h" |
51 | #include "gm20b/acr_gm20b.h" | 51 | #include "gm20b/acr_gm20b.h" |
52 | #include "acr.h" | ||
52 | #include "cde_gk20a.h" | 53 | #include "cde_gk20a.h" |
53 | #include "debug_gk20a.h" | 54 | #include "debug_gk20a.h" |
54 | 55 | ||
@@ -669,7 +670,7 @@ struct gk20a { | |||
669 | struct sim_gk20a sim; | 670 | struct sim_gk20a sim; |
670 | struct mm_gk20a mm; | 671 | struct mm_gk20a mm; |
671 | struct pmu_gk20a pmu; | 672 | struct pmu_gk20a pmu; |
672 | struct acr_gm20b acr; | 673 | struct acr_desc acr; |
673 | struct cooling_device_gk20a gk20a_cdev; | 674 | struct cooling_device_gk20a gk20a_cdev; |
674 | 675 | ||
675 | /* Save pmu fw here so that it lives cross suspend/resume. | 676 | /* Save pmu fw here so that it lives cross suspend/resume. |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index ea4500eb..1f78749c 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1058,7 +1058,7 @@ int gm20b_bootstrap_hs_flcn(struct gk20a *g) | |||
1058 | u32 img_size_in_bytes = 0; | 1058 | u32 img_size_in_bytes = 0; |
1059 | u32 status, size; | 1059 | u32 status, size; |
1060 | u64 start; | 1060 | u64 start; |
1061 | struct acr_gm20b *acr = &g->acr; | 1061 | struct acr_desc *acr = &g->acr; |
1062 | const struct firmware *acr_fw = acr->acr_fw; | 1062 | const struct firmware *acr_fw = acr->acr_fw; |
1063 | struct flcn_bl_dmem_desc *bl_dmem_desc = &acr->bl_dmem_desc; | 1063 | struct flcn_bl_dmem_desc *bl_dmem_desc = &acr->bl_dmem_desc; |
1064 | u32 *acr_ucode_header_t210_load; | 1064 | u32 *acr_ucode_header_t210_load; |
@@ -1204,7 +1204,7 @@ static int bl_bootstrap(struct pmu_gk20a *pmu, | |||
1204 | struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz) | 1204 | struct flcn_bl_dmem_desc *pbl_desc, u32 bl_sz) |
1205 | { | 1205 | { |
1206 | struct gk20a *g = gk20a_from_pmu(pmu); | 1206 | struct gk20a *g = gk20a_from_pmu(pmu); |
1207 | struct acr_gm20b *acr = &g->acr; | 1207 | struct acr_desc *acr = &g->acr; |
1208 | struct mm_gk20a *mm = &g->mm; | 1208 | struct mm_gk20a *mm = &g->mm; |
1209 | u32 imem_dst_blk = 0; | 1209 | u32 imem_dst_blk = 0; |
1210 | u32 virt_addr = 0; | 1210 | u32 virt_addr = 0; |
@@ -1375,7 +1375,7 @@ int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt) | |||
1375 | struct device *d = dev_from_gk20a(g); | 1375 | struct device *d = dev_from_gk20a(g); |
1376 | int err = 0; | 1376 | int err = 0; |
1377 | u32 bl_sz; | 1377 | u32 bl_sz; |
1378 | struct acr_gm20b *acr = &g->acr; | 1378 | struct acr_desc *acr = &g->acr; |
1379 | const struct firmware *hsbl_fw = acr->hsbl_fw; | 1379 | const struct firmware *hsbl_fw = acr->hsbl_fw; |
1380 | struct hsflcn_bl_desc *pmu_bl_gm10x_desc; | 1380 | struct hsflcn_bl_desc *pmu_bl_gm10x_desc; |
1381 | u32 *pmu_bl_gm10x = NULL; | 1381 | u32 *pmu_bl_gm10x = NULL; |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index 179345b9..a1dceae9 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -386,24 +386,6 @@ struct acr_fw_header { | |||
386 | u32 hdr_size; /*size of above header*/ | 386 | u32 hdr_size; /*size of above header*/ |
387 | }; | 387 | }; |
388 | 388 | ||
389 | struct acr_gm20b { | ||
390 | struct mem_desc ucode_blob; | ||
391 | struct bin_hdr *bl_bin_hdr; | ||
392 | struct hsflcn_bl_desc *pmu_hsbl_desc; | ||
393 | struct bin_hdr *hsbin_hdr; | ||
394 | struct acr_fw_header *fw_hdr; | ||
395 | u32 pmu_args; | ||
396 | const struct firmware *acr_fw; | ||
397 | struct flcn_acr_desc *acr_dmem_desc; | ||
398 | struct mem_desc acr_ucode; | ||
399 | const struct firmware *hsbl_fw; | ||
400 | struct mem_desc hsbl_ucode; | ||
401 | struct flcn_bl_dmem_desc bl_dmem_desc; | ||
402 | const struct firmware *pmu_fw; | ||
403 | const struct firmware *pmu_desc; | ||
404 | u32 capabilities; | ||
405 | }; | ||
406 | |||
407 | void gm20b_init_secure_pmu(struct gpu_ops *gops); | 389 | void gm20b_init_secure_pmu(struct gpu_ops *gops); |
408 | int prepare_ucode_blob(struct gk20a *g); | 390 | int prepare_ucode_blob(struct gk20a *g); |
409 | int gm20b_pmu_setup_sw(struct gk20a *g); | 391 | int gm20b_pmu_setup_sw(struct gk20a *g); |