diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-12-06 04:33:08 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-12-21 11:45:59 -0500 |
commit | 145225b896bd43a918280de27260ba5a315751c8 (patch) | |
tree | 5eb9bfba7eff0aa808d66cce81abf19924a3f054 /drivers | |
parent | 34d8421ab4e9ecd0af09f7fefe71b9a1d8781061 (diff) |
gpu: nvgpu: remove clk writel from TPC FS
To floorsweep any TPC on gm20b, we first have to
set BIT(28) in CLK_RST_CONTROLLER_MISC_CLK_ENB_0
from nvgpu driver
But now this bit is set by default from clock
driver, hence remove clk_writel() from nvgpu
driver
Bug 200262155
Change-Id: I65bc60cb017109bdb882d83637f2a06d27586f18
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1265752
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 6 |
2 files changed, 0 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 27c2df3d..01537042 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -511,9 +511,6 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | |||
511 | 511 | ||
512 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 512 | static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
513 | { | 513 | { |
514 | tegra_clk_writel(CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE, | ||
515 | CLK_RST_CONTROLLER_MISC_CLK_ENB_0); | ||
516 | |||
517 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | 514 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) |
518 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); | 515 | tegra_fuse_writel(0x1, FUSE_FUSEBYPASS_0); |
519 | tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); | 516 | tegra_fuse_writel(0x0, FUSE_WRITE_ACCESS_SW_0); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index fd24d105..84eb3862 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -28,12 +28,6 @@ enum { | |||
28 | MAXWELL_CHANNEL_GPFIFO_A= 0xB06F, | 28 | MAXWELL_CHANNEL_GPFIFO_A= 0xB06F, |
29 | }; | 29 | }; |
30 | 30 | ||
31 | #define tegra_clk_writel(value, offset) \ | ||
32 | writel(value, IO_ADDRESS(0x60006000 + offset)) | ||
33 | |||
34 | #define CLK_RST_CONTROLLER_MISC_CLK_ENB_0 0x48 | ||
35 | #define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE BIT(28) | ||
36 | |||
37 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) | 31 | #if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) |
38 | #define FUSE_FUSEBYPASS_0 0x24 | 32 | #define FUSE_FUSEBYPASS_0 0x24 |
39 | #define FUSE_WRITE_ACCESS_SW_0 0x30 | 33 | #define FUSE_WRITE_ACCESS_SW_0 0x30 |