gpu: nvgpu: Expand GM20b PLL fields header

Added masks for GM20b GPCPLL input and post dividers.

Bug 1450787

Change-Id: I39a9c7ffb740fa9ef3a614deb2591412e34ef263
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/447857
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Bo Yan <byan@nvidia.com>

1 files changed, 8 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
index 6a4c10e5..487cd959 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
@@ -126,6 +126,10 @@ static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
 {
         return (v & 0xff) << 0;
 }
+static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
+{
+        return 0xff << 0;
+}
 static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
 {
         return (r >> 0) & 0xff;
@@ -146,6 +150,10 @@ static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
 {
         return (v & 0x3f) << 16;
 }
+static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
+{
+        return 0x3f << 16;
+}
 static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
 {
         return (r >> 16) & 0x3f;