gpu: nvgpu: interface update to sync CL #19870492

- pg statistics update
- perfmon update
- ADD GR inti params interface to enable ELPG

Bug n/a

Change-Id: I39ae1d4518733480a42f06a0be7bd794fc93ff6f
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/799684
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/806176
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 187 insertions, 17 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 110f3c5a..7cc248fa 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -522,6 +522,11 @@ static u16 get_pmu_init_msg_pmu_sw_mg_size_v0(union pmu_init_msg_pmu *init_msg)
         return init->sw_managed_area_size;
 }
 
+static u32 get_pmu_perfmon_cmd_start_size_v2(void)
+{
+        return sizeof(struct pmu_perfmon_cmd_start_v2);
+}
+
 static u32 get_pmu_perfmon_cmd_start_size_v1(void)
 {
         return sizeof(struct pmu_perfmon_cmd_start_v1);
@@ -532,6 +537,20 @@ static u32 get_pmu_perfmon_cmd_start_size_v0(void)
         return sizeof(struct pmu_perfmon_cmd_start_v0);
 }
 
+static int get_perfmon_cmd_start_offsetofvar_v2(
+        enum pmu_perfmon_cmd_start_fields field)
+{
+        switch (field) {
+        case COUNTER_ALLOC:
+                return offsetof(struct pmu_perfmon_cmd_start_v2,
+                counter_alloc);
+        default:
+                return -EINVAL;
+        }
+
+        return 0;
+}
+
 static int get_perfmon_cmd_start_offsetofvar_v1(
         enum pmu_perfmon_cmd_start_fields field)
 {
@@ -541,8 +560,8 @@ static int get_perfmon_cmd_start_offsetofvar_v1(
                 counter_alloc);
         default:
                 return -EINVAL;
-                break;
         }
+
         return 0;
 }
 
@@ -560,6 +579,11 @@ static int get_perfmon_cmd_start_offsetofvar_v0(
         return 0;
 }
 
+static u32 get_pmu_perfmon_cmd_init_size_v2(void)
+{
+        return sizeof(struct pmu_perfmon_cmd_init_v2);
+}
+
 static u32 get_pmu_perfmon_cmd_init_size_v1(void)
 {
         return sizeof(struct pmu_perfmon_cmd_init_v1);
@@ -570,6 +594,20 @@ static u32 get_pmu_perfmon_cmd_init_size_v0(void)
         return sizeof(struct pmu_perfmon_cmd_init_v0);
 }
 
+static int get_perfmon_cmd_init_offsetofvar_v2(
+        enum pmu_perfmon_cmd_start_fields field)
+{
+        switch (field) {
+        case COUNTER_ALLOC:
+                return offsetof(struct pmu_perfmon_cmd_init_v2,
+                counter_alloc);
+        default:
+                return -EINVAL;
+                break;
+        }
+        return 0;
+}
+
 static int get_perfmon_cmd_init_offsetofvar_v1(
         enum pmu_perfmon_cmd_start_fields field)
 {
@@ -598,6 +636,12 @@ static int get_perfmon_cmd_init_offsetofvar_v0(
         return 0;
 }
 
+static void perfmon_start_set_cmd_type_v2(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
+        start->cmd_type = value;
+}
+
 static void perfmon_start_set_cmd_type_v1(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v1 *start = &pc->start_v1;
@@ -610,6 +654,12 @@ static void perfmon_start_set_cmd_type_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->cmd_type = value;
 }
 
+static void perfmon_start_set_group_id_v2(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
+        start->group_id = value;
+}
+
 static void perfmon_start_set_group_id_v1(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v1 *start = &pc->start_v1;
@@ -622,6 +672,12 @@ static void perfmon_start_set_group_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->group_id = value;
 }
 
+static void perfmon_start_set_state_id_v2(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
+        start->state_id = value;
+}
+
 static void perfmon_start_set_state_id_v1(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v1 *start = &pc->start_v1;
@@ -634,6 +690,12 @@ static void perfmon_start_set_state_id_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->state_id = value;
 }
 
+static void perfmon_start_set_flags_v2(struct pmu_perfmon_cmd *pc, u8 value)
+{
+        struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
+        start->flags = value;
+}
+
 static void perfmon_start_set_flags_v1(struct pmu_perfmon_cmd *pc, u8 value)
 {
         struct pmu_perfmon_cmd_start_v1 *start = &pc->start_v1;
@@ -646,6 +708,12 @@ static void perfmon_start_set_flags_v0(struct pmu_perfmon_cmd *pc, u8 value)
         start->flags = value;
 }
 
+static u8 perfmon_start_get_flags_v2(struct pmu_perfmon_cmd *pc)
+{
+        struct pmu_perfmon_cmd_start_v2 *start = &pc->start_v2;
+        return start->flags;
+}
+
 static u8 perfmon_start_get_flags_v1(struct pmu_perfmon_cmd *pc)
 {
         struct pmu_perfmon_cmd_start_v1 *start = &pc->start_v1;
@@ -658,6 +726,14 @@ static u8 perfmon_start_get_flags_v0(struct pmu_perfmon_cmd *pc)
         return start->flags;
 }
 
+static void perfmon_cmd_init_set_sample_buffer_v2(struct pmu_perfmon_cmd *pc,
+        u16 value)
+{
+        struct pmu_perfmon_cmd_init_v2 *init = &pc->init_v2;
+        init->sample_buffer = value;
+}
+
+
 static void perfmon_cmd_init_set_sample_buffer_v1(struct pmu_perfmon_cmd *pc,
         u16 value)
 {
@@ -672,6 +748,13 @@ static void perfmon_cmd_init_set_sample_buffer_v0(struct pmu_perfmon_cmd *pc,
         init->sample_buffer = value;
 }
 
+static void perfmon_cmd_init_set_dec_cnt_v2(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v2 *init = &pc->init_v2;
+        init->to_decrease_count = value;
+}
+
 static void perfmon_cmd_init_set_dec_cnt_v1(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -686,6 +769,13 @@ static void perfmon_cmd_init_set_dec_cnt_v0(struct pmu_perfmon_cmd *pc,
         init->to_decrease_count = value;
 }
 
+static void perfmon_cmd_init_set_base_cnt_id_v2(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v2 *init = &pc->init_v2;
+        init->base_counter_id = value;
+}
+
 static void perfmon_cmd_init_set_base_cnt_id_v1(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -700,6 +790,13 @@ static void perfmon_cmd_init_set_base_cnt_id_v0(struct pmu_perfmon_cmd *pc,
         init->base_counter_id = value;
 }
 
+static void perfmon_cmd_init_set_samp_period_us_v2(struct pmu_perfmon_cmd *pc,
+        u32 value)
+{
+        struct pmu_perfmon_cmd_init_v2 *init = &pc->init_v2;
+        init->sample_period_us = value;
+}
+
 static void perfmon_cmd_init_set_samp_period_us_v1(struct pmu_perfmon_cmd *pc,
         u32 value)
 {
@@ -714,6 +811,13 @@ static void perfmon_cmd_init_set_samp_period_us_v0(struct pmu_perfmon_cmd *pc,
         init->sample_period_us = value;
 }
 
+static void perfmon_cmd_init_set_num_cnt_v2(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v2 *init = &pc->init_v2;
+        init->num_counters = value;
+}
+
 static void perfmon_cmd_init_set_num_cnt_v1(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -728,6 +832,13 @@ static void perfmon_cmd_init_set_num_cnt_v0(struct pmu_perfmon_cmd *pc,
         init->num_counters = value;
 }
 
+static void perfmon_cmd_init_set_mov_avg_v2(struct pmu_perfmon_cmd *pc,
+        u8 value)
+{
+        struct pmu_perfmon_cmd_init_v2 *init = &pc->init_v2;
+        init->samples_in_moving_avg = value;
+}
+
 static void perfmon_cmd_init_set_mov_avg_v1(struct pmu_perfmon_cmd *pc,
         u8 value)
 {
@@ -961,35 +1072,35 @@ int gk20a_init_pmu(struct pmu_gk20a *pmu)
                 g->ops.pmu_ver.get_pmu_init_msg_pmu_sw_mg_size =
                         get_pmu_init_msg_pmu_sw_mg_size_v1;
                 g->ops.pmu_ver.get_pmu_perfmon_cmd_start_size =
-                        get_pmu_perfmon_cmd_start_size_v1;
+                        get_pmu_perfmon_cmd_start_size_v2;
                 g->ops.pmu_ver.get_perfmon_cmd_start_offsetofvar =
-                        get_perfmon_cmd_start_offsetofvar_v1;
+                        get_perfmon_cmd_start_offsetofvar_v2;
                 g->ops.pmu_ver.perfmon_start_set_cmd_type =
-                        perfmon_start_set_cmd_type_v1;
+                        perfmon_start_set_cmd_type_v2;
                 g->ops.pmu_ver.perfmon_start_set_group_id =
-                        perfmon_start_set_group_id_v1;
+                        perfmon_start_set_group_id_v2;
                 g->ops.pmu_ver.perfmon_start_set_state_id =
-                        perfmon_start_set_state_id_v1;
+                        perfmon_start_set_state_id_v2;
                 g->ops.pmu_ver.perfmon_start_set_flags =
-                        perfmon_start_set_flags_v1;
+                        perfmon_start_set_flags_v2;
                 g->ops.pmu_ver.perfmon_start_get_flags =
-                        perfmon_start_get_flags_v1;
+                        perfmon_start_get_flags_v2;
                 g->ops.pmu_ver.get_pmu_perfmon_cmd_init_size =
-                        get_pmu_perfmon_cmd_init_size_v1;
+                        get_pmu_perfmon_cmd_init_size_v2;
                 g->ops.pmu_ver.get_perfmon_cmd_init_offsetofvar =
-                        get_perfmon_cmd_init_offsetofvar_v1;
+                        get_perfmon_cmd_init_offsetofvar_v2;
                 g->ops.pmu_ver.perfmon_cmd_init_set_sample_buffer =
-                        perfmon_cmd_init_set_sample_buffer_v1;
+                        perfmon_cmd_init_set_sample_buffer_v2;
                 g->ops.pmu_ver.perfmon_cmd_init_set_dec_cnt =
-                        perfmon_cmd_init_set_dec_cnt_v1;
+                        perfmon_cmd_init_set_dec_cnt_v2;
                 g->ops.pmu_ver.perfmon_cmd_init_set_base_cnt_id =
-                        perfmon_cmd_init_set_base_cnt_id_v1;
+                        perfmon_cmd_init_set_base_cnt_id_v2;
                 g->ops.pmu_ver.perfmon_cmd_init_set_samp_period_us =
-                        perfmon_cmd_init_set_samp_period_us_v1;
+                        perfmon_cmd_init_set_samp_period_us_v2;
                 g->ops.pmu_ver.perfmon_cmd_init_set_num_cnt =
-                        perfmon_cmd_init_set_num_cnt_v1;
+                        perfmon_cmd_init_set_num_cnt_v2;
                 g->ops.pmu_ver.perfmon_cmd_init_set_mov_avg =
-                        perfmon_cmd_init_set_mov_avg_v1;
+                        perfmon_cmd_init_set_mov_avg_v2;
                 g->ops.pmu_ver.get_pmu_seq_in_a_ptr =
                         get_pmu_sequence_in_alloc_ptr_v1;
                 g->ops.pmu_ver.get_pmu_seq_out_a_ptr =
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index e00991cb..0d7d7435 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -341,7 +341,7 @@ struct pmu_mem_desc_v0 {
     /*!
      * Start address of memory surface that is being communicated to the falcon.
      */
-        u64 dma_addr;
+        struct falc_u64 dma_addr;
     /*!
      * Max allowed DMA transfer size (size of the memory surface). Accesses past
      * this point may result in page faults and/or memory corruptions.
@@ -679,6 +679,15 @@ enum {
         PMU_PG_STAT_CMD_ALLOC_DMEM = 0,
 };
 
+#define PMU_PG_FEATURE_GR_SDIV_SLOWDOWN_ENABLED (1 << 0)
+#define PMU_PG_FEATURE_GR_POWER_GATING_ENABLED  (1 << 2)
+
+struct pmu_pg_cmd_gr_init_param {
+        u8 cmd_type;
+        u16 sub_cmd_id;
+        u8 featuremask;
+};
+
 struct pmu_pg_cmd_stat {
         u8 cmd_type;
         u8 engine_id;
@@ -693,6 +702,7 @@ struct pmu_pg_cmd {
                 struct pmu_pg_cmd_eng_buf_load_v0 eng_buf_load_v0;
                 struct pmu_pg_cmd_eng_buf_load_v1 eng_buf_load_v1;
                 struct pmu_pg_cmd_stat stat;
+                struct pmu_pg_cmd_gr_init_param gr_init_param;
                 /* TBD: other pg commands */
                 union pmu_ap_cmd ap_cmd;
         };
@@ -835,6 +845,14 @@ enum {
         PMU_PERFMON_CMD_ID_INIT  = 2
 };
 
+struct pmu_perfmon_cmd_start_v2 {
+        u8 cmd_type;
+        u8 group_id;
+        u8 state_id;
+        u8 flags;
+        struct pmu_allocation_v2 counter_alloc;
+};
+
 struct pmu_perfmon_cmd_start_v1 {
         u8 cmd_type;
         u8 group_id;
@@ -855,6 +873,17 @@ struct pmu_perfmon_cmd_stop {
         u8 cmd_type;
 };
 
+struct pmu_perfmon_cmd_init_v2 {
+        u8 cmd_type;
+        u8 to_decrease_count;
+        u8 base_counter_id;
+        u32 sample_period_us;
+        struct pmu_allocation_v2 counter_alloc;
+        u8 num_counters;
+        u8 samples_in_moving_avg;
+        u16 sample_buffer;
+};
+
 struct pmu_perfmon_cmd_init_v1 {
         u8 cmd_type;
         u8 to_decrease_count;
@@ -882,9 +911,11 @@ struct pmu_perfmon_cmd {
                 u8 cmd_type;
                 struct pmu_perfmon_cmd_start_v0 start_v0;
                 struct pmu_perfmon_cmd_start_v1 start_v1;
+                struct pmu_perfmon_cmd_start_v2 start_v2;
                 struct pmu_perfmon_cmd_stop stop;
                 struct pmu_perfmon_cmd_init_v0 init_v0;
                 struct pmu_perfmon_cmd_init_v1 init_v1;
+                struct pmu_perfmon_cmd_init_v2 init_v2;
         };
 };
 
@@ -1102,6 +1133,34 @@ struct pmu_sequence {
         void* cb_params;
 };
 
+struct pmu_pg_stats_v1 {
+    /* Number of time PMU successfully engaged sleep state */
+    u32 entryCount;
+    /* Number of time PMU exit sleep state */
+    u32 exitCount;
+    /* Number of time PMU aborted in entry sequence */
+    u32 abortCount;
+    /*
+     * Time for which GPU was neither in Sleep state not
+     * executing sleep sequence.
+     * */
+    u32 poweredUpTimeUs;
+    /* Entry and exit latency of current sleep cycle */
+    u32 entryLatencyUs;
+    u32 exitLatencyUs;
+    /* Resident time for current sleep cycle. */
+    u32 residentTimeUs;
+    /* Rolling average entry and exit latencies */
+    u32 entryLatencyAvgUs;
+    u32 exitLatencyAvgUs;
+    /* Max entry and exit latencies */
+    u32 entryLatencyMaxUs;
+    u32 exitLatencyMaxUs;
+    /* Total time spent in sleep and non-sleep state */
+    u32 totalSleepTimeUs;
+    u32 totalNonSleepTimeUs;
+};
+
 struct pmu_pg_stats {
         u64 pg_entry_start_timestamp;
         u64 pg_ingating_start_timestamp;