diff options
author | Alex Frid <afrid@nvidia.com> | 2014-07-22 19:51:06 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:33 -0400 |
commit | 10571e9db77f47fb50a8a2ebee820966a8c72b87 (patch) | |
tree | 7186dd4becce0594d02bc24a35395404999dc962 /drivers | |
parent | ebf991e990f43f664340016c6825ee4c3cbd5e78 (diff) |
gpu: nvgpu: Add gm20b h/w definitions
Added SYNC_MODE field, and BYPASSCTRL register; expanded
GPC2CLK_OUT_VCODIV field.
Bug 1450787
Signed-off-by: Alex Frid <afrid@nvidia.com>
Change-Id: Ibf2119a88b0d5f099199920e70b2e88f04b8863b
Reviewed-on: http://git-master/r/440928
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h index 17f2af79..6a4c10e5 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h | |||
@@ -82,6 +82,22 @@ static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void) | |||
82 | { | 82 | { |
83 | return 0x00000000; | 83 | return 0x00000000; |
84 | } | 84 | } |
85 | static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void) | ||
86 | { | ||
87 | return 0x1 << 2; | ||
88 | } | ||
89 | static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r) | ||
90 | { | ||
91 | return (r >> 2) & 0x1; | ||
92 | } | ||
93 | static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void) | ||
94 | { | ||
95 | return 0x4; | ||
96 | } | ||
97 | static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void) | ||
98 | { | ||
99 | return 0x0; | ||
100 | } | ||
85 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) | 101 | static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void) |
86 | { | 102 | { |
87 | return 0x1 << 4; | 103 | return 0x1 << 4; |
@@ -182,10 +198,22 @@ static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void) | |||
182 | { | 198 | { |
183 | return 0x3c; | 199 | return 0x3c; |
184 | } | 200 | } |
201 | static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void) | ||
202 | { | ||
203 | return 6; | ||
204 | } | ||
205 | static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v) | ||
206 | { | ||
207 | return (v & 0x3f) << 8; | ||
208 | } | ||
185 | static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) | 209 | static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void) |
186 | { | 210 | { |
187 | return 0x3f << 8; | 211 | return 0x3f << 8; |
188 | } | 212 | } |
213 | static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r) | ||
214 | { | ||
215 | return (r >> 8) & 0x3f; | ||
216 | } | ||
189 | static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) | 217 | static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void) |
190 | { | 218 | { |
191 | return 0x0; | 219 | return 0x0; |
@@ -286,4 +314,20 @@ static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_syn | |||
286 | { | 314 | { |
287 | return (r >> 24) & 0x1; | 315 | return (r >> 24) & 0x1; |
288 | } | 316 | } |
317 | static inline u32 trim_sys_bypassctrl_r(void) | ||
318 | { | ||
319 | return 0x00137340; | ||
320 | } | ||
321 | static inline u32 trim_sys_bypassctrl_gpcpll_m(void) | ||
322 | { | ||
323 | return 0x1 << 0; | ||
324 | } | ||
325 | static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void) | ||
326 | { | ||
327 | return 0x1; | ||
328 | } | ||
329 | static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void) | ||
330 | { | ||
331 | return 0x0; | ||
332 | } | ||
289 | #endif | 333 | #endif |