gpu: nvgpu: program sw veid bundles

Query sw veid bundles from sim/netlist and
initialize hardware with those bundles.

JIRA GV11B-11

Change-Id: I26f174781f0b00b919afac407e2bb9e1fa7b158a
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1231597
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 files changed, 32 insertions, 3 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 6959b86a..a76798d1 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -97,6 +97,7 @@ enum nvgpu_litter_value {
         GPU_LIT_NUM_PES_PER_GPC,
         GPU_LIT_NUM_ZCULL_BANKS,
         GPU_LIT_NUM_TPC_PER_GPC,
+        GPU_LIT_NUM_SM_PER_TPC,
         GPU_LIT_NUM_FBPS,
         GPU_LIT_GPC_BASE,
         GPU_LIT_GPC_STRIDE,
@@ -303,6 +304,7 @@ struct gpu_ops {
                                                 u32 gpc, u32 tpc, u32 smid);
                 void (*program_active_tpc_counts)(struct gk20a *g, u32 gpc);
                 int  (*setup_rop_mapping)(struct gk20a *g, struct gr_gk20a *gr);
+                int (*init_sw_veid_bundle)(struct gk20a *g);
         } gr;
         const char *name;
         struct {
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
index 5a1152d5..f040ffc0 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a.c
@@ -205,6 +205,15 @@ static int gr_gk20a_init_ctx_vars_fw(struct gk20a *g, struct gr_gk20a *gr)
                                 if (err)
                                         goto clean_up;
                                 break;
+                        case NETLIST_REGIONID_SWVEIDBUNDLEINIT:
+                                gk20a_dbg_info(
+                                        "NETLIST_REGIONID_SW_VEID_BUNDLE_INIT");
+                                err = gr_gk20a_alloc_load_netlist_av(
+                                        src, size,
+                                        &g->gr.ctx_vars.sw_veid_bundle_init);
+                                if (err)
+                                        goto clean_up;
+                                break;
                         case NETLIST_REGIONID_CTXREG_SYS:
                                 gk20a_dbg_info("NETLIST_REGIONID_CTXREG_SYS");
                                 err = gr_gk20a_alloc_load_netlist_aiv(
@@ -394,6 +403,7 @@ clean_up:
                 kfree(g->gr.ctx_vars.sw_method_init.l);
                 kfree(g->gr.ctx_vars.sw_ctx_load.l);
                 kfree(g->gr.ctx_vars.sw_non_ctx_load.l);
+                kfree(g->gr.ctx_vars.sw_veid_bundle_init.l);
                 kfree(g->gr.ctx_vars.ctxsw_regs.sys.l);
                 kfree(g->gr.ctx_vars.ctxsw_regs.gpc.l);
                 kfree(g->gr.ctx_vars.ctxsw_regs.tpc.l);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
index 9430ce7b..70787202 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_ctx_gk20a_sim.c
@@ -3,7 +3,7 @@
  *
  * GK20A Graphics Context for Simulation
  *
- * Copyright (c) 2011-2014, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2011-2016, NVIDIA CORPORATION.  All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -50,7 +50,8 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
                             &g->gr.ctx_vars.sw_method_init.count);
         gk20a_sim_esc_readl(g, "GRCTX_SW_CTX_LOAD_SIZE", 0,
                             &g->gr.ctx_vars.sw_ctx_load.count);
-
+        gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT_SIZE", 0,
+                            &g->gr.ctx_vars.sw_veid_bundle_init.count);
 
         gk20a_sim_esc_readl(g, "GRCTX_NONCTXSW_REG_SIZE", 0,
                             &g->gr.ctx_vars.sw_non_ctx_load.count);
@@ -77,6 +78,7 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
         err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_method_init);
         err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.sw_ctx_load);
         err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_non_ctx_load);
+        err |= !alloc_av_list_gk20a(&g->gr.ctx_vars.sw_veid_bundle_init);
         err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.sys);
         err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.gpc);
         err |= !alloc_aiv_list_gk20a(&g->gr.ctx_vars.ctxsw_regs.tpc);
@@ -139,6 +141,15 @@ int gr_gk20a_init_ctx_vars_sim(struct gk20a *g, struct gr_gk20a *gr)
                                     i, &l[i].value);
         }
 
+        for (i = 0; i < g->gr.ctx_vars.sw_veid_bundle_init.count; i++) {
+                struct av_gk20a *l = g->gr.ctx_vars.sw_veid_bundle_init.l;
+
+                gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:ADDR",
+                                    i, &l[i].addr);
+                gk20a_sim_esc_readl(g, "GRCTX_SW_VEID_BUNDLE_INIT:VALUE",
+                                    i, &l[i].value);
+        }
+
         for (i = 0; i < g->gr.ctx_vars.ctxsw_regs.sys.count; i++) {
                 struct aiv_gk20a *l = g->gr.ctx_vars.ctxsw_regs.sys.l;
                 gk20a_sim_esc_readl(g, "GRCTX_REG_LIST_SYS:ADDR",
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index e78c40f3..75f4379d 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -368,7 +368,7 @@ int gr_gk20a_wait_idle(struct gk20a *g, unsigned long end_jiffies,
         return -EAGAIN;
 }
 
-static int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long end_jiffies,
+int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long end_jiffies,
                 u32 expect_delay)
 {
         u32 val;
@@ -1462,6 +1462,8 @@ static u32 gk20a_init_sw_bundle(struct gk20a *g)
                 if (err)
                         break;
         }
+        if (g->ops.gr.init_sw_veid_bundle)
+                g->ops.gr.init_sw_veid_bundle(g);
 
         /* disable pipe mode override */
         gk20a_writel(g, gr_pipe_bundle_config_r(),
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index c337a74a..df6a3f3c 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -231,6 +231,7 @@ struct gr_gk20a {
                 struct av_list_gk20a  sw_method_init;
                 struct aiv_list_gk20a sw_ctx_load;
                 struct av_list_gk20a  sw_non_ctx_load;
+                struct av_list_gk20a  sw_veid_bundle_init;
                 struct {
                         struct aiv_list_gk20a sys;
                         struct aiv_list_gk20a gpc;
@@ -643,6 +644,9 @@ int gr_gk20a_get_ctx_id(struct gk20a *g,
 
 u32 gk20a_mask_hww_warp_esr(u32 hww_warp_esr);
 
+int gr_gk20a_wait_fe_idle(struct gk20a *g, unsigned long end_jiffies,
+                        u32 expect_delay);
+
 bool gr_gk20a_suspend_context(struct channel_gk20a *ch);
 bool gr_gk20a_resume_context(struct channel_gk20a *ch);
 int gr_gk20a_suspend_contexts(struct gk20a *g,