diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-07-02 18:33:42 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-05 06:06:59 -0400 |
commit | 0e2e3898f7f8828ff9601d414f730b9fa8d09b3f (patch) | |
tree | ac1d3e5ec37423c7204a06f9767f2551a7658b34 /drivers | |
parent | b7ae37cc32babbb433a017df12300fe4b4d5e2ac (diff) |
gpu: nvgpu: add suspend_single_sm gr ops
This is required to support multiple SM and t19x
sm register address changes
JIRA GPUT19X-75
Change-Id: Id104f611736535874cdaa5a2f768f692d799c2c5
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512214
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/gr_gp10b.c | 2 |
5 files changed, 13 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index a1ad96b9..f97534b5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -370,6 +370,9 @@ struct gpu_ops { | |||
370 | int (*set_czf_bypass)(struct gk20a *g, | 370 | int (*set_czf_bypass)(struct gk20a *g, |
371 | struct channel_gk20a *ch); | 371 | struct channel_gk20a *ch); |
372 | bool (*sm_debugger_attached)(struct gk20a *g); | 372 | bool (*sm_debugger_attached)(struct gk20a *g); |
373 | void (*suspend_single_sm)(struct gk20a *g, | ||
374 | u32 gpc, u32 tpc, u32 sm, | ||
375 | u32 global_esr_mask, bool check_errors); | ||
373 | } gr; | 376 | } gr; |
374 | struct { | 377 | struct { |
375 | void (*init_hw)(struct gk20a *g); | 378 | void (*init_hw)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 4c1a61a9..64b991a2 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -8013,16 +8013,13 @@ int gk20a_gr_wait_for_sm_lock_down(struct gk20a *g, u32 gpc, u32 tpc, | |||
8013 | return -ETIMEDOUT; | 8013 | return -ETIMEDOUT; |
8014 | } | 8014 | } |
8015 | 8015 | ||
8016 | void gk20a_suspend_single_sm(struct gk20a *g, | 8016 | void gk20a_gr_suspend_single_sm(struct gk20a *g, |
8017 | u32 gpc, u32 tpc, | 8017 | u32 gpc, u32 tpc, u32 sm, |
8018 | u32 global_esr_mask, bool check_errors) | 8018 | u32 global_esr_mask, bool check_errors) |
8019 | { | 8019 | { |
8020 | u32 offset; | ||
8021 | int err; | 8020 | int err; |
8022 | u32 dbgr_control0; | 8021 | u32 dbgr_control0; |
8023 | u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); | 8022 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); |
8024 | u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); | ||
8025 | offset = gpc_stride * gpc + tpc_in_gpc_stride * tpc; | ||
8026 | 8023 | ||
8027 | /* if an SM debugger isn't attached, skip suspend */ | 8024 | /* if an SM debugger isn't attached, skip suspend */ |
8028 | if (!g->ops.gr.sm_debugger_attached(g)) { | 8025 | if (!g->ops.gr.sm_debugger_attached(g)) { |
@@ -8031,6 +8028,9 @@ void gk20a_suspend_single_sm(struct gk20a *g, | |||
8031 | return; | 8028 | return; |
8032 | } | 8029 | } |
8033 | 8030 | ||
8031 | nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
8032 | "suspending gpc:%d, tpc:%d, sm%d", gpc, tpc, sm); | ||
8033 | |||
8034 | /* assert stop trigger. */ | 8034 | /* assert stop trigger. */ |
8035 | dbgr_control0 = gk20a_readl(g, | 8035 | dbgr_control0 = gk20a_readl(g, |
8036 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); | 8036 | gr_gpc0_tpc0_sm_dbgr_control0_r() + offset); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index dd11a082..a9b7c2d7 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -615,8 +615,8 @@ int gr_gk20a_enable_ctxsw(struct gk20a *g); | |||
615 | void gk20a_resume_single_sm(struct gk20a *g, | 615 | void gk20a_resume_single_sm(struct gk20a *g, |
616 | u32 gpc, u32 tpc); | 616 | u32 gpc, u32 tpc); |
617 | void gk20a_resume_all_sms(struct gk20a *g); | 617 | void gk20a_resume_all_sms(struct gk20a *g); |
618 | void gk20a_suspend_single_sm(struct gk20a *g, | 618 | void gk20a_gr_suspend_single_sm(struct gk20a *g, |
619 | u32 gpc, u32 tpc, | 619 | u32 gpc, u32 tpc, u32 sm, |
620 | u32 global_esr_mask, bool check_errors); | 620 | u32 global_esr_mask, bool check_errors); |
621 | void gk20a_suspend_all_sms(struct gk20a *g, | 621 | void gk20a_suspend_all_sms(struct gk20a *g, |
622 | u32 global_esr_mask, bool check_errors); | 622 | u32 global_esr_mask, bool check_errors); |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 043e2855..d985a44d 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1631,4 +1631,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1631 | gops->gr.tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions; | 1631 | gops->gr.tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions; |
1632 | gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel; | 1632 | gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel; |
1633 | gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached; | 1633 | gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached; |
1634 | gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm; | ||
1634 | } | 1635 | } |
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c index 2a3ecd31..5d17472f 100644 --- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c | |||
@@ -1829,7 +1829,7 @@ static int gr_gp10b_pre_process_sm_exception(struct gk20a *g, | |||
1829 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1829 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1830 | "CILP: STOP_TRIGGER from gpc %d tpc %d\n", | 1830 | "CILP: STOP_TRIGGER from gpc %d tpc %d\n", |
1831 | gpc, tpc); | 1831 | gpc, tpc); |
1832 | gk20a_suspend_single_sm(g, gpc, tpc, global_mask, true); | 1832 | g->ops.gr.suspend_single_sm(g, gpc, tpc, sm, global_mask, true); |
1833 | } | 1833 | } |
1834 | 1834 | ||
1835 | /* reset the HWW errors after locking down */ | 1835 | /* reset the HWW errors after locking down */ |