diff options
| author | Vijayakumar <vsubbu@nvidia.com> | 2016-05-17 07:28:03 -0400 |
|---|---|---|
| committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-05-24 15:59:24 -0400 |
| commit | 0d2b93ac3742422386853a2d9e562a673a6424a8 (patch) | |
| tree | f804fd7a45041b4607fc128bbc525a5567aa2312 /drivers | |
| parent | 3e431e26c5c3aba6da8a6555ec3d7b7df53f534a (diff) | |
gpu:nvgpu:gm20b: update elpg prod settings
bug 1764398
PGSequencer settings use index to writ to PSORDER register setting.
HW has implementation for 28 PSORDER (PSORDER0 - 27).
Every write will auto increment index and index will wrap around
after it reaches 27.
In PROD settings we are writing enable for 0 to 27 and
zero for 28 to 65. This overwrites enables written to 0 to 27.
Effectively those partitions are never power gated.
P4 SWCL# 20744424
Change-Id: I45826e98dd6a84e9c4fe119fbe7ca75acfd8a4ea
Signed-off-by: Vijayakumar <vsubbu@nvidia.com>
Reviewed-on: http://git-master/r/1149055
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Supriya Sharatkumar <ssharatkumar@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
| -rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 38 |
1 files changed, 0 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 8eb600ef..8702658c 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
| @@ -69,44 +69,6 @@ static struct pg_init_sequence_list _pginitseq_gm20b[] = { | |||
| 69 | { 0x0010e06c, 0x00000099}, | 69 | { 0x0010e06c, 0x00000099}, |
| 70 | { 0x0010e06c, 0x0000009a}, | 70 | { 0x0010e06c, 0x0000009a}, |
| 71 | { 0x0010e06c, 0x0000009b}, | 71 | { 0x0010e06c, 0x0000009b}, |
| 72 | { 0x0010e06c, 0x00000000}, | ||
| 73 | { 0x0010e06c, 0x00000000}, | ||
| 74 | { 0x0010e06c, 0x00000000}, | ||
| 75 | { 0x0010e06c, 0x00000000}, | ||
| 76 | { 0x0010e06c, 0x00000000}, | ||
| 77 | { 0x0010e06c, 0x00000000}, | ||
| 78 | { 0x0010e06c, 0x00000000}, | ||
| 79 | { 0x0010e06c, 0x00000000}, | ||
| 80 | { 0x0010e06c, 0x00000000}, | ||
| 81 | { 0x0010e06c, 0x00000000}, | ||
| 82 | { 0x0010e06c, 0x00000000}, | ||
| 83 | { 0x0010e06c, 0x00000000}, | ||
| 84 | { 0x0010e06c, 0x00000000}, | ||
| 85 | { 0x0010e06c, 0x00000000}, | ||
| 86 | { 0x0010e06c, 0x00000000}, | ||
| 87 | { 0x0010e06c, 0x00000000}, | ||
| 88 | { 0x0010e06c, 0x00000000}, | ||
| 89 | { 0x0010e06c, 0x00000000}, | ||
| 90 | { 0x0010e06c, 0x00000000}, | ||
| 91 | { 0x0010e06c, 0x00000000}, | ||
| 92 | { 0x0010e06c, 0x00000000}, | ||
| 93 | { 0x0010e06c, 0x00000000}, | ||
| 94 | { 0x0010e06c, 0x00000000}, | ||
| 95 | { 0x0010e06c, 0x00000000}, | ||
| 96 | { 0x0010e06c, 0x00000000}, | ||
| 97 | { 0x0010e06c, 0x00000000}, | ||
| 98 | { 0x0010e06c, 0x00000000}, | ||
| 99 | { 0x0010e06c, 0x00000000}, | ||
| 100 | { 0x0010e06c, 0x00000000}, | ||
| 101 | { 0x0010e06c, 0x00000000}, | ||
| 102 | { 0x0010e06c, 0x00000000}, | ||
| 103 | { 0x0010e06c, 0x00000000}, | ||
| 104 | { 0x0010e06c, 0x00000000}, | ||
| 105 | { 0x0010e06c, 0x00000000}, | ||
| 106 | { 0x0010e06c, 0x00000000}, | ||
| 107 | { 0x0010e06c, 0x00000000}, | ||
| 108 | { 0x0010e06c, 0x00000000}, | ||
| 109 | { 0x0010e06c, 0x00000000}, | ||
| 110 | { 0x0010ab14, 0x00000000}, | 72 | { 0x0010ab14, 0x00000000}, |
| 111 | { 0x0010ab18, 0x00000000}, | 73 | { 0x0010ab18, 0x00000000}, |
| 112 | { 0x0010e024, 0x00000000}, | 74 | { 0x0010e024, 0x00000000}, |