gpu: nvgpu: use litter val for pbdma/eng *status__size*

fifo_pbdma_status__size_1_v() and fifo_engine_status__size_1_v()
are not same for all gpus. Use litter value to calculate chip
specific fifo*status__size_1(v)

JIRA GV11B-45

Change-Id: I3d3d45bf79d15e14739fcc18cb1ca987669d5c11
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1312688
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

2 files changed, 14 insertions, 6 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
index 4b8e61c4..67f9b532 100644
--- a/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/debug_gk20a.c
@@ -176,10 +176,13 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
         struct fifo_gk20a *f = &g->fifo;
         u32 chid;
         unsigned int i;
+        u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA);
+        u32 host_num_engines = nvgpu_get_litter_value(g,
+                                         GPU_LIT_HOST_NUM_ENGINES);
 
         struct ch_state **ch_state;
 
-        for (i = 0; i < fifo_pbdma_status__size_1_v(); i++) {
+        for (i = 0; i < host_num_pbdma; i++) {
                 u32 status = gk20a_readl(g, fifo_pbdma_status_r(i));
                 u32 chan_status = fifo_pbdma_status_chan_status_v(status);
 
@@ -204,7 +207,7 @@ void gk20a_debug_show_dump(struct gk20a *g, struct gk20a_debug_output *o)
         }
         gk20a_debug_output(o, "\n");
 
-        for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
+        for (i = 0; i < host_num_engines; i++) {
                 u32 status = gk20a_readl(g, fifo_engine_status_r(i));
                 u32 ctx_status = fifo_engine_status_ctx_status_v(status);
 
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 0d3a75fc..95351a43 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -3115,9 +3115,11 @@ bool gk20a_fifo_mmu_fault_pending(struct gk20a *g)
 
 bool gk20a_fifo_is_engine_busy(struct gk20a *g)
 {
-        unsigned int i;
+        u32 i, host_num_engines;
+
+        host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
 
-        for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
+        for (i = 0; i < host_num_engines; i++) {
                 u32 status = gk20a_readl(g, fifo_engine_status_r(i));
                 if (fifo_engine_status_engine_v(status) ==
                         fifo_engine_status_engine_busy_v())
@@ -3131,14 +3133,17 @@ int gk20a_fifo_wait_engine_idle(struct gk20a *g)
         struct nvgpu_timeout timeout;
         unsigned long delay = GR_IDLE_CHECK_DEFAULT;
         int ret = -ETIMEDOUT;
-        u32 i;
+        u32 i, host_num_engines;
 
         gk20a_dbg_fn("");
 
+        host_num_engines =
+                 nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES);
+
         nvgpu_timeout_init(g, &timeout, gk20a_get_gr_idle_timeout(g),
                            NVGPU_TIMER_CPU_TIMER);
 
-        for (i = 0; i < fifo_engine_status__size_1_v(); i++) {
+        for (i = 0; i < host_num_engines; i++) {
                 do {
                         u32 status = gk20a_readl(g, fifo_engine_status_r(i));
                         if (!fifo_engine_status_engine_v(status)) {