gpu: nvgpu: nvlink: Add HAL for RXDET

RXDET is supported only on nvlink 2.2 devices and forward.
Add HAL to run RXDET selectively based on chip. RXDET needs to be
done after the links are out of reset but before any other link
level initialization.
minion_send_cmd is also made non-static to support RXDET
functionality.

JIRA NVLINK-160

Change-Id: Ic65b8dbc7281743f62072089ff3c805521ac9b38
Signed-off-by: Tejal Kudav <tkudav@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1729525
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

5 files changed, 32 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 48f0008a..9b72f1a7 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -1182,6 +1182,7 @@ struct gpu_ops {
                 int (*discover_ioctrl)(struct gk20a *g);
                 int (*discover_link)(struct gk20a *g);
                 int (*isr)(struct gk20a *g);
+                int (*rxdet)(struct gk20a *g, u32 link_id);
                 /* API */
                 int (*link_early_init)(struct gk20a *g, unsigned long mask);
                 u32 (*link_get_mode)(struct gk20a *g, u32 link_id);
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 9b38f881..3d47cc40 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -832,6 +832,7 @@ static const struct gpu_ops gv100_ops = {
                 .discover_link = gv100_nvlink_discover_link,
                 .init = gv100_nvlink_init,
                 .isr = gv100_nvlink_isr,
+                .rxdet = NULL,
                 /* API */
                 .link_early_init = gv100_nvlink_link_early_init,
                 .link_get_state = gv100_nvlink_link_get_state,
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
index 7258b9e9..098aae0e 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.c
@@ -735,10 +735,10 @@ static u32 gv100_nvlink_minion_command_complete(struct gk20a *g, u32 link_id)
 /*
  * Send Minion command (can be async)
  */
-static u32 gv100_nvlink_minion_send_command(struct gk20a *g,
-        u32 link_id, u32 command, u32 scratch_0, bool sync)
+int gv100_nvlink_minion_send_command(struct gk20a *g, u32 link_id,
+                                u32 command, u32 scratch_0, bool sync)
 {
-        u32 err = 0;
+        int err = 0;
 
         /* Check last command succeded */
         err = gv100_nvlink_minion_command_complete(g, link_id);
@@ -1579,6 +1579,15 @@ static int gv100_nvlink_enable_links_pre_top(struct gk20a *g, u32 links)
                 IOCTRL_REG_WR32(g, ioctrl_debug_reset_r(), reg);
                 nvgpu_udelay(delay);
 
+                /* Before  doing any link initialization, run RXDET to check
+                 * if link is connected on  other end.
+                 */
+                if (g->ops.nvlink.rxdet) {
+                        err = g->ops.nvlink.rxdet(g, link_id);
+                        if (err)
+                                return err;
+                }
+
                 /* Enable Link DLPL for AN0 */
                 reg = DLPL_REG_RD32(g, link_id, nvl_link_config_r());
                 reg = set_field(reg, nvl_link_config_link_en_m(),
diff --git a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h
index 4ac8b907..a583c576 100644
--- a/drivers/gpu/nvgpu/gv100/nvlink_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/nvlink_gv100.h
@@ -25,23 +25,12 @@
 
 struct gk20a;
 
-#define MINION_REG_RD32(g, off) gk20a_readl(g, g->nvlink.minion_base + (off))
-#define MINION_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.minion_base + (off), (v))
-#define IOCTRL_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ioctrl_base + (off))
-#define IOCTRL_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ioctrl_base + (off), (v));
-#define MIF_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].mif_base + (off))
-#define MIF_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].mif_base + (off), (v))
-#define IPT_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ipt_base + (off))
-#define IPT_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ipt_base + (off), (v))
-#define TLC_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].tl_base + (off))
-#define TLC_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].tl_base + (off), (v))
-#define DLPL_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].dlpl_base + (off))
-#define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].dlpl_base + (off), (v))
-
 int gv100_nvlink_discover_ioctrl(struct gk20a *g);
 int gv100_nvlink_discover_link(struct gk20a *g);
 int gv100_nvlink_init(struct gk20a *g);
 int gv100_nvlink_isr(struct gk20a *g);
+int gv100_nvlink_minion_send_command(struct gk20a *g, u32 link_id, u32 command,
+                                                u32 scratch_0, bool sync);
 /* API */
 int gv100_nvlink_link_early_init(struct gk20a *g, unsigned long mask);
 u32 gv100_nvlink_link_get_mode(struct gk20a *g, u32 link_id);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
index 59e2009f..bb47537f 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvlink.h
@@ -33,6 +33,22 @@
 #include <nvgpu_rmos/include/nvlink.h>
 #endif
 
+#define NV_NVLINK_REG_POLL_TIMEOUT_MS           3000
+#define NV_NVLINK_TIMEOUT_DELAY_US              5
+
+#define MINION_REG_RD32(g, off) gk20a_readl(g, g->nvlink.minion_base + (off))
+#define MINION_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.minion_base + (off), (v))
+#define IOCTRL_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ioctrl_base + (off))
+#define IOCTRL_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ioctrl_base + (off), (v))
+#define MIF_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].mif_base + (off))
+#define MIF_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].mif_base + (off), (v))
+#define IPT_REG_RD32(g, off) gk20a_readl(g, g->nvlink.ipt_base + (off))
+#define IPT_REG_WR32(g, off, v) gk20a_writel(g, g->nvlink.ipt_base + (off), (v))
+#define TLC_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].tl_base + (off))
+#define TLC_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].tl_base + (off), (v))
+#define DLPL_REG_RD32(g, id, off) gk20a_readl(g, g->nvlink.links[(id)].dlpl_base + (off))
+#define DLPL_REG_WR32(g, id, off, v) gk20a_writel(g, g->nvlink.links[(id)].dlpl_base + (off), (v))
+
 struct gk20a;
 
 struct nvgpu_nvlink_ioctrl_list {