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authorSeema Khowala <seemaj@nvidia.com>2017-02-23 13:16:10 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-02 11:53:32 -0500
commit0aafa9e279da0fdcca19b610a57919fd00ad35aa (patch)
treea0d53656ee580adad435ce7dc2d92711d34f0332 /drivers
parent64e1782aee550670fedcf8b8b012fc1281ae9172 (diff)
gpu: nvgpu: gm20b: add gr ops for load tpc mask
gr_fe_tpc_fs_r addr is different for t19x Change-Id: I9868fcaf94d063753c4ecf1970b53374cb67b380 Signed-off-by: Seema Khowala <seemaj@nvidia.com> Reviewed-on: http://git-master/r/1310326 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h1
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c3
2 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 51569fb7..272fadbb 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -341,6 +341,7 @@ struct gpu_ops {
341 void (*write_pm_ptr)(struct gk20a *g, 341 void (*write_pm_ptr)(struct gk20a *g,
342 struct mem_desc *mem, u64 gpu_va); 342 struct mem_desc *mem, u64 gpu_va);
343 void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine); 343 void (*init_elcg_mode)(struct gk20a *g, u32 mode, u32 engine);
344 void (*load_tpc_mask)(struct gk20a *g);
344 } gr; 345 } gr;
345 const char *name; 346 const char *name;
346 struct { 347 struct {
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 44a0116b..de3f879a 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -636,7 +636,7 @@ int gr_gm20b_init_fs_state(struct gk20a *g)
636 636
637 gr_gk20a_init_fs_state(g); 637 gr_gk20a_init_fs_state(g);
638 638
639 gr_gm20b_load_tpc_mask(g); 639 g->ops.gr.load_tpc_mask(g);
640 640
641 gk20a_writel(g, gr_bes_zrop_settings_r(), 641 gk20a_writel(g, gr_bes_zrop_settings_r(),
642 gr_bes_zrop_settings_num_active_ltcs_f(g->ltc_count)); 642 gr_bes_zrop_settings_num_active_ltcs_f(g->ltc_count));
@@ -1605,5 +1605,6 @@ void gm20b_init_gr(struct gpu_ops *gops)
1605 gops->gr.write_zcull_ptr = gr_gk20a_write_zcull_ptr; 1605 gops->gr.write_zcull_ptr = gr_gk20a_write_zcull_ptr;
1606 gops->gr.write_pm_ptr = gr_gk20a_write_pm_ptr; 1606 gops->gr.write_pm_ptr = gr_gk20a_write_pm_ptr;
1607 gops->gr.init_elcg_mode = gr_gk20a_init_elcg_mode; 1607 gops->gr.init_elcg_mode = gr_gk20a_init_elcg_mode;
1608 gops->gr.load_tpc_mask = gr_gm20b_load_tpc_mask;
1608 1609
1609} 1610}