diff options
author | Seema Khowala <seemaj@nvidia.com> | 2016-09-22 17:41:31 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2016-09-28 16:23:42 -0400 |
commit | 09168aac40b22ba264de6a7fc1e5264528b1fe9f (patch) | |
tree | 8985568ba3dc6c8f2830880e1368950301a9b0d2 /drivers | |
parent | 8fdf40a849f19dc2f00aacce976ed2e22dbb08f4 (diff) |
gpu: nvgpu: gv11b: header updates for CL#37119043
Bug 1735760
Change-Id: I5216863a25338f14498ae0be58b86993104d4e99
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1222031
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 207 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | 88 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | 174 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | 16 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | 8 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | 312 |
6 files changed, 283 insertions, 522 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 088ec040..02044df6 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -67,105 +67,16 @@ static int gr_gv11b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
67 | int ret = 0; | 67 | int ret = 0; |
68 | u32 offset = proj_gpc_stride_v() * gpc + | 68 | u32 offset = proj_gpc_stride_v() * gpc + |
69 | proj_tpc_in_gpc_stride_v() * tpc; | 69 | proj_tpc_in_gpc_stride_v() * tpc; |
70 | u32 lrf_ecc_status, shm_ecc_status; | 70 | u32 lrf_ecc_status; |
71 | 71 | ||
72 | gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); | 72 | gr_gk20a_handle_sm_exception(g, gpc, tpc, post_event, fault_ch, hww_global_esr); |
73 | 73 | ||
74 | /* Check for LRF ECC errors. */ | 74 | /* Check for LRF ECC errors. */ |
75 | lrf_ecc_status = gk20a_readl(g, | 75 | lrf_ecc_status = gk20a_readl(g, |
76 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); | 76 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset); |
77 | if ((lrf_ecc_status & | 77 | |
78 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f()) || | ||
79 | (lrf_ecc_status & | ||
80 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f()) || | ||
81 | (lrf_ecc_status & | ||
82 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f()) || | ||
83 | (lrf_ecc_status & | ||
84 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f())) { | ||
85 | |||
86 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
87 | "Single bit error detected in SM LRF!"); | ||
88 | |||
89 | g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += | ||
90 | gk20a_readl(g, | ||
91 | gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset); | ||
92 | gk20a_writel(g, | ||
93 | gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r() + offset, | ||
94 | 0); | ||
95 | } | ||
96 | if ((lrf_ecc_status & | ||
97 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f()) || | ||
98 | (lrf_ecc_status & | ||
99 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f()) || | ||
100 | (lrf_ecc_status & | ||
101 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f()) || | ||
102 | (lrf_ecc_status & | ||
103 | gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f())) { | ||
104 | |||
105 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
106 | "Double bit error detected in SM LRF!"); | ||
107 | |||
108 | g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += | ||
109 | gk20a_readl(g, | ||
110 | gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset); | ||
111 | gk20a_writel(g, | ||
112 | gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r() + offset, 0); | ||
113 | } | ||
114 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, | 78 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, |
115 | lrf_ecc_status); | 79 | lrf_ecc_status); |
116 | |||
117 | /* Check for SHM ECC errors. */ | ||
118 | shm_ecc_status = gk20a_readl(g, | ||
119 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset); | ||
120 | if ((shm_ecc_status & | ||
121 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f()) || | ||
122 | (shm_ecc_status & | ||
123 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f()) || | ||
124 | (shm_ecc_status & | ||
125 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f()) || | ||
126 | (shm_ecc_status & | ||
127 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f())) { | ||
128 | u32 ecc_stats_reg_val; | ||
129 | |||
130 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
131 | "Single bit error detected in SM SHM!"); | ||
132 | |||
133 | ecc_stats_reg_val = | ||
134 | gk20a_readl(g, | ||
135 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | ||
136 | g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] += | ||
137 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); | ||
138 | g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] += | ||
139 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); | ||
140 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | | ||
141 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); | ||
142 | gk20a_writel(g, | ||
143 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, | ||
144 | ecc_stats_reg_val); | ||
145 | } | ||
146 | if ((shm_ecc_status & | ||
147 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f()) || | ||
148 | (shm_ecc_status & | ||
149 | gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f())) { | ||
150 | u32 ecc_stats_reg_val; | ||
151 | |||
152 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
153 | "Double bit error detected in SM SHM!"); | ||
154 | |||
155 | ecc_stats_reg_val = | ||
156 | gk20a_readl(g, | ||
157 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); | ||
158 | g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] += | ||
159 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); | ||
160 | ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); | ||
161 | gk20a_writel(g, | ||
162 | gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset, | ||
163 | ecc_stats_reg_val); | ||
164 | } | ||
165 | gk20a_writel(g, gr_pri_gpc0_tpc0_sm_shm_ecc_status_r() + offset, | ||
166 | shm_ecc_status); | ||
167 | |||
168 | |||
169 | return ret; | 80 | return ret; |
170 | } | 81 | } |
171 | 82 | ||
@@ -176,7 +87,6 @@ static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
176 | u32 offset = proj_gpc_stride_v() * gpc + | 87 | u32 offset = proj_gpc_stride_v() * gpc + |
177 | proj_tpc_in_gpc_stride_v() * tpc; | 88 | proj_tpc_in_gpc_stride_v() * tpc; |
178 | u32 esr; | 89 | u32 esr; |
179 | u32 ecc_stats_reg_val; | ||
180 | 90 | ||
181 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); | 91 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, ""); |
182 | 92 | ||
@@ -184,119 +94,6 @@ static int gr_gv11b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc, | |||
184 | gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); | 94 | gr_gpc0_tpc0_tex_m_hww_esr_r() + offset); |
185 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); | 95 | gk20a_dbg(gpu_dbg_intr | gpu_dbg_gpu_dbg, "0x%08x", esr); |
186 | 96 | ||
187 | if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f()) { | ||
188 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
189 | "Single bit error detected in TEX!"); | ||
190 | |||
191 | /* Pipe 0 counters */ | ||
192 | gk20a_writel(g, | ||
193 | gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, | ||
194 | gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); | ||
195 | |||
196 | ecc_stats_reg_val = gk20a_readl(g, | ||
197 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | ||
198 | g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] += | ||
199 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | ||
200 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | ||
201 | gk20a_writel(g, | ||
202 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, | ||
203 | ecc_stats_reg_val); | ||
204 | |||
205 | ecc_stats_reg_val = gk20a_readl(g, | ||
206 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | ||
207 | g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] += | ||
208 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | ||
209 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | ||
210 | gk20a_writel(g, | ||
211 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, | ||
212 | ecc_stats_reg_val); | ||
213 | |||
214 | |||
215 | /* Pipe 1 counters */ | ||
216 | gk20a_writel(g, | ||
217 | gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, | ||
218 | gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); | ||
219 | |||
220 | ecc_stats_reg_val = gk20a_readl(g, | ||
221 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | ||
222 | g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] += | ||
223 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); | ||
224 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); | ||
225 | gk20a_writel(g, | ||
226 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, | ||
227 | ecc_stats_reg_val); | ||
228 | |||
229 | ecc_stats_reg_val = gk20a_readl(g, | ||
230 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | ||
231 | g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] += | ||
232 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); | ||
233 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); | ||
234 | gk20a_writel(g, | ||
235 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, | ||
236 | ecc_stats_reg_val); | ||
237 | |||
238 | |||
239 | gk20a_writel(g, | ||
240 | gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, | ||
241 | gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); | ||
242 | } | ||
243 | if (esr & gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f()) { | ||
244 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_intr, | ||
245 | "Double bit error detected in TEX!"); | ||
246 | |||
247 | /* Pipe 0 counters */ | ||
248 | gk20a_writel(g, | ||
249 | gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, | ||
250 | gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe0_f()); | ||
251 | |||
252 | ecc_stats_reg_val = gk20a_readl(g, | ||
253 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | ||
254 | g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] += | ||
255 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | ||
256 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | ||
257 | gk20a_writel(g, | ||
258 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, | ||
259 | ecc_stats_reg_val); | ||
260 | |||
261 | ecc_stats_reg_val = gk20a_readl(g, | ||
262 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | ||
263 | g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] += | ||
264 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | ||
265 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | ||
266 | gk20a_writel(g, | ||
267 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, | ||
268 | ecc_stats_reg_val); | ||
269 | |||
270 | |||
271 | /* Pipe 1 counters */ | ||
272 | gk20a_writel(g, | ||
273 | gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, | ||
274 | gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f()); | ||
275 | |||
276 | ecc_stats_reg_val = gk20a_readl(g, | ||
277 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); | ||
278 | g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] += | ||
279 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); | ||
280 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); | ||
281 | gk20a_writel(g, | ||
282 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset, | ||
283 | ecc_stats_reg_val); | ||
284 | |||
285 | ecc_stats_reg_val = gk20a_readl(g, | ||
286 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); | ||
287 | g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] += | ||
288 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); | ||
289 | ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); | ||
290 | gk20a_writel(g, | ||
291 | gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset, | ||
292 | ecc_stats_reg_val); | ||
293 | |||
294 | |||
295 | gk20a_writel(g, | ||
296 | gr_pri_gpc0_tpc0_tex_m_routing_r() + offset, | ||
297 | gr_pri_gpc0_tpc0_tex_m_routing_sel_default_f()); | ||
298 | } | ||
299 | |||
300 | gk20a_writel(g, | 97 | gk20a_writel(g, |
301 | gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, | 98 | gr_gpc0_tpc0_tex_m_hww_esr_r() + offset, |
302 | esr); | 99 | esr); |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h index 8af66362..7e9e2743 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_fifo_gv11b.h | |||
@@ -190,22 +190,6 @@ static inline u32 fifo_intr_0_lb_error_reset_f(void) | |||
190 | { | 190 | { |
191 | return 0x1000000; | 191 | return 0x1000000; |
192 | } | 192 | } |
193 | static inline u32 fifo_intr_0_replayable_fault_error_pending_f(void) | ||
194 | { | ||
195 | return 0x2000000; | ||
196 | } | ||
197 | static inline u32 fifo_intr_0_dropped_mmu_fault_pending_f(void) | ||
198 | { | ||
199 | return 0x8000000; | ||
200 | } | ||
201 | static inline u32 fifo_intr_0_dropped_mmu_fault_reset_f(void) | ||
202 | { | ||
203 | return 0x8000000; | ||
204 | } | ||
205 | static inline u32 fifo_intr_0_mmu_fault_pending_f(void) | ||
206 | { | ||
207 | return 0x10000000; | ||
208 | } | ||
209 | static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) | 193 | static inline u32 fifo_intr_0_pbdma_intr_pending_f(void) |
210 | { | 194 | { |
211 | return 0x20000000; | 195 | return 0x20000000; |
@@ -230,14 +214,6 @@ static inline u32 fifo_intr_en_0_sched_error_m(void) | |||
230 | { | 214 | { |
231 | return 0x1 << 8; | 215 | return 0x1 << 8; |
232 | } | 216 | } |
233 | static inline u32 fifo_intr_en_0_mmu_fault_f(u32 v) | ||
234 | { | ||
235 | return (v & 0x1) << 28; | ||
236 | } | ||
237 | static inline u32 fifo_intr_en_0_mmu_fault_m(void) | ||
238 | { | ||
239 | return 0x1 << 28; | ||
240 | } | ||
241 | static inline u32 fifo_intr_en_1_r(void) | 217 | static inline u32 fifo_intr_en_1_r(void) |
242 | { | 218 | { |
243 | return 0x00002528; | 219 | return 0x00002528; |
@@ -262,62 +238,14 @@ static inline u32 fifo_intr_chsw_error_r(void) | |||
262 | { | 238 | { |
263 | return 0x0000256c; | 239 | return 0x0000256c; |
264 | } | 240 | } |
265 | static inline u32 fifo_intr_mmu_fault_id_r(void) | 241 | static inline u32 fifo_gpc_v(void) |
266 | { | ||
267 | return 0x0000259c; | ||
268 | } | ||
269 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_v(void) | ||
270 | { | ||
271 | return 0x00000040; | ||
272 | } | ||
273 | static inline u32 fifo_intr_mmu_fault_eng_id_graphics_f(void) | ||
274 | { | ||
275 | return 0x0; | ||
276 | } | ||
277 | static inline u32 fifo_intr_mmu_fault_inst_r(u32 i) | ||
278 | { | ||
279 | return 0x00002800 + i*16; | ||
280 | } | ||
281 | static inline u32 fifo_intr_mmu_fault_inst_ptr_v(u32 r) | ||
282 | { | ||
283 | return (r >> 0) & 0xfffffff; | ||
284 | } | ||
285 | static inline u32 fifo_intr_mmu_fault_inst_ptr_align_shift_v(void) | ||
286 | { | ||
287 | return 0x0000000c; | ||
288 | } | ||
289 | static inline u32 fifo_intr_mmu_fault_lo_r(u32 i) | ||
290 | { | ||
291 | return 0x00002804 + i*16; | ||
292 | } | ||
293 | static inline u32 fifo_intr_mmu_fault_hi_r(u32 i) | ||
294 | { | ||
295 | return 0x00002808 + i*16; | ||
296 | } | ||
297 | static inline u32 fifo_intr_mmu_fault_info_r(u32 i) | ||
298 | { | ||
299 | return 0x0000280c + i*16; | ||
300 | } | ||
301 | static inline u32 fifo_intr_mmu_fault_info_type_v(u32 r) | ||
302 | { | ||
303 | return (r >> 0) & 0x1f; | ||
304 | } | ||
305 | static inline u32 fifo_intr_mmu_fault_info_client_type_v(u32 r) | ||
306 | { | ||
307 | return (r >> 20) & 0x1; | ||
308 | } | ||
309 | static inline u32 fifo_intr_mmu_fault_info_client_type_gpc_v(void) | ||
310 | { | 242 | { |
311 | return 0x00000000; | 243 | return 0x00000000; |
312 | } | 244 | } |
313 | static inline u32 fifo_intr_mmu_fault_info_client_type_hub_v(void) | 245 | static inline u32 fifo_hub_v(void) |
314 | { | 246 | { |
315 | return 0x00000001; | 247 | return 0x00000001; |
316 | } | 248 | } |
317 | static inline u32 fifo_intr_mmu_fault_info_client_v(u32 r) | ||
318 | { | ||
319 | return (r >> 8) & 0x7f; | ||
320 | } | ||
321 | static inline u32 fifo_intr_pbdma_id_r(void) | 249 | static inline u32 fifo_intr_pbdma_id_r(void) |
322 | { | 250 | { |
323 | return 0x000025a0; | 251 | return 0x000025a0; |
@@ -394,18 +322,6 @@ static inline u32 fifo_preempt_id_f(u32 v) | |||
394 | { | 322 | { |
395 | return (v & 0xfff) << 0; | 323 | return (v & 0xfff) << 0; |
396 | } | 324 | } |
397 | static inline u32 fifo_trigger_mmu_fault_r(u32 i) | ||
398 | { | ||
399 | return 0x00002a30 + i*4; | ||
400 | } | ||
401 | static inline u32 fifo_trigger_mmu_fault_id_f(u32 v) | ||
402 | { | ||
403 | return (v & 0x1f) << 0; | ||
404 | } | ||
405 | static inline u32 fifo_trigger_mmu_fault_enable_f(u32 v) | ||
406 | { | ||
407 | return (v & 0x1) << 8; | ||
408 | } | ||
409 | static inline u32 fifo_engine_status_r(u32 i) | 325 | static inline u32 fifo_engine_status_r(u32 i) |
410 | { | 326 | { |
411 | return 0x00002640 + i*8; | 327 | return 0x00002640 + i*8; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h index 6cfa33ea..e8394215 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_gr_gv11b.h | |||
@@ -470,102 +470,6 @@ static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r(void) | |||
470 | { | 470 | { |
471 | return 0x00504358; | 471 | return 0x00504358; |
472 | } | 472 | } |
473 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp0_pending_f(void) | ||
474 | { | ||
475 | return 0x10; | ||
476 | } | ||
477 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp1_pending_f(void) | ||
478 | { | ||
479 | return 0x20; | ||
480 | } | ||
481 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp2_pending_f(void) | ||
482 | { | ||
483 | return 0x40; | ||
484 | } | ||
485 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_single_err_detected_qrfdp3_pending_f(void) | ||
486 | { | ||
487 | return 0x80; | ||
488 | } | ||
489 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp0_pending_f(void) | ||
490 | { | ||
491 | return 0x100; | ||
492 | } | ||
493 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp1_pending_f(void) | ||
494 | { | ||
495 | return 0x200; | ||
496 | } | ||
497 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp2_pending_f(void) | ||
498 | { | ||
499 | return 0x400; | ||
500 | } | ||
501 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_status_double_err_detected_qrfdp3_pending_f(void) | ||
502 | { | ||
503 | return 0x800; | ||
504 | } | ||
505 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_r(void) | ||
506 | { | ||
507 | return 0x0050436c; | ||
508 | } | ||
509 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm0_pending_f(void) | ||
510 | { | ||
511 | return 0x1; | ||
512 | } | ||
513 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_corrected_shm1_pending_f(void) | ||
514 | { | ||
515 | return 0x2; | ||
516 | } | ||
517 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm0_pending_f(void) | ||
518 | { | ||
519 | return 0x10; | ||
520 | } | ||
521 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_single_err_detected_shm1_pending_f(void) | ||
522 | { | ||
523 | return 0x20; | ||
524 | } | ||
525 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm0_pending_f(void) | ||
526 | { | ||
527 | return 0x100; | ||
528 | } | ||
529 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_status_double_err_detected_shm1_pending_f(void) | ||
530 | { | ||
531 | return 0x200; | ||
532 | } | ||
533 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_single_err_count_r(void) | ||
534 | { | ||
535 | return 0x0050435c; | ||
536 | } | ||
537 | static inline u32 gr_pri_gpc0_tpc0_sm_lrf_ecc_double_err_count_r(void) | ||
538 | { | ||
539 | return 0x00504360; | ||
540 | } | ||
541 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r(void) | ||
542 | { | ||
543 | return 0x00504370; | ||
544 | } | ||
545 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m(void) | ||
546 | { | ||
547 | return 0xff << 0; | ||
548 | } | ||
549 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(u32 r) | ||
550 | { | ||
551 | return (r >> 0) & 0xff; | ||
552 | } | ||
553 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m(void) | ||
554 | { | ||
555 | return 0xff << 8; | ||
556 | } | ||
557 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(u32 r) | ||
558 | { | ||
559 | return (r >> 8) & 0xff; | ||
560 | } | ||
561 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m(void) | ||
562 | { | ||
563 | return 0xff << 16; | ||
564 | } | ||
565 | static inline u32 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(u32 r) | ||
566 | { | ||
567 | return (r >> 16) & 0xff; | ||
568 | } | ||
569 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) | 473 | static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_r(void) |
570 | { | 474 | { |
571 | return 0x005042c4; | 475 | return 0x005042c4; |
@@ -582,46 +486,6 @@ static inline u32 gr_pri_gpc0_tpc0_tex_m_routing_sel_pipe1_f(void) | |||
582 | { | 486 | { |
583 | return 0x2; | 487 | return 0x2; |
584 | } | 488 | } |
585 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r(void) | ||
586 | { | ||
587 | return 0x00504218; | ||
588 | } | ||
589 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(void) | ||
590 | { | ||
591 | return 0xffff << 0; | ||
592 | } | ||
593 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(u32 r) | ||
594 | { | ||
595 | return (r >> 0) & 0xffff; | ||
596 | } | ||
597 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(void) | ||
598 | { | ||
599 | return 0xffff << 16; | ||
600 | } | ||
601 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(u32 r) | ||
602 | { | ||
603 | return (r >> 16) & 0xffff; | ||
604 | } | ||
605 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r(void) | ||
606 | { | ||
607 | return 0x005042ec; | ||
608 | } | ||
609 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(void) | ||
610 | { | ||
611 | return 0xffff << 0; | ||
612 | } | ||
613 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(u32 r) | ||
614 | { | ||
615 | return (r >> 0) & 0xffff; | ||
616 | } | ||
617 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(void) | ||
618 | { | ||
619 | return 0xffff << 16; | ||
620 | } | ||
621 | static inline u32 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(u32 r) | ||
622 | { | ||
623 | return (r >> 16) & 0xffff; | ||
624 | } | ||
625 | static inline u32 gr_pri_be0_crop_status1_r(void) | 489 | static inline u32 gr_pri_be0_crop_status1_r(void) |
626 | { | 490 | { |
627 | return 0x00410134; | 491 | return 0x00410134; |
@@ -654,6 +518,14 @@ static inline u32 gr_pipe_bundle_address_value_v(u32 r) | |||
654 | { | 518 | { |
655 | return (r >> 0) & 0xffff; | 519 | return (r >> 0) & 0xffff; |
656 | } | 520 | } |
521 | static inline u32 gr_pipe_bundle_address_veid_f(u32 v) | ||
522 | { | ||
523 | return (v & 0x3f) << 20; | ||
524 | } | ||
525 | static inline u32 gr_pipe_bundle_address_veid_v(u32 r) | ||
526 | { | ||
527 | return (r >> 20) & 0x3f; | ||
528 | } | ||
657 | static inline u32 gr_pipe_bundle_data_r(void) | 529 | static inline u32 gr_pipe_bundle_data_r(void) |
658 | { | 530 | { |
659 | return 0x00400204; | 531 | return 0x00400204; |
@@ -1498,14 +1370,6 @@ static inline u32 gr_fecs_feature_override_ecc_sm_lrf_override_v(u32 r) | |||
1498 | { | 1370 | { |
1499 | return (r >> 3) & 0x1; | 1371 | return (r >> 3) & 0x1; |
1500 | } | 1372 | } |
1501 | static inline u32 gr_fecs_feature_override_ecc_sm_shm_override_v(u32 r) | ||
1502 | { | ||
1503 | return (r >> 7) & 0x1; | ||
1504 | } | ||
1505 | static inline u32 gr_fecs_feature_override_ecc_tex_override_v(u32 r) | ||
1506 | { | ||
1507 | return (r >> 11) & 0x1; | ||
1508 | } | ||
1509 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) | 1373 | static inline u32 gr_fecs_feature_override_ecc_ltc_override_v(u32 r) |
1510 | { | 1374 | { |
1511 | return (r >> 15) & 0x1; | 1375 | return (r >> 15) & 0x1; |
@@ -1514,14 +1378,6 @@ static inline u32 gr_fecs_feature_override_ecc_sm_lrf_v(u32 r) | |||
1514 | { | 1378 | { |
1515 | return (r >> 0) & 0x1; | 1379 | return (r >> 0) & 0x1; |
1516 | } | 1380 | } |
1517 | static inline u32 gr_fecs_feature_override_ecc_sm_shm_v(u32 r) | ||
1518 | { | ||
1519 | return (r >> 4) & 0x1; | ||
1520 | } | ||
1521 | static inline u32 gr_fecs_feature_override_ecc_tex_v(u32 r) | ||
1522 | { | ||
1523 | return (r >> 8) & 0x1; | ||
1524 | } | ||
1525 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) | 1381 | static inline u32 gr_fecs_feature_override_ecc_ltc_v(u32 r) |
1526 | { | 1382 | { |
1527 | return (r >> 12) & 0x1; | 1383 | return (r >> 12) & 0x1; |
@@ -2384,11 +2240,11 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_m(void) | |||
2384 | } | 2240 | } |
2385 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) | 2241 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_default_v(void) |
2386 | { | 2242 | { |
2387 | return 0x00001000; | 2243 | return 0x00000800; |
2388 | } | 2244 | } |
2389 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) | 2245 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_gfxp_v(void) |
2390 | { | 2246 | { |
2391 | return 0x00001900; | 2247 | return 0x00001100; |
2392 | } | 2248 | } |
2393 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) | 2249 | static inline u32 gr_gpc0_ppc0_cbm_beta_cb_size_v_granularity_v(void) |
2394 | { | 2250 | { |
@@ -2432,7 +2288,7 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_f(u32 v) | |||
2432 | } | 2288 | } |
2433 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) | 2289 | static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void) |
2434 | { | 2290 | { |
2435 | return 0x00001000; | 2291 | return 0x00000800; |
2436 | } | 2292 | } |
2437 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) | 2293 | static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void) |
2438 | { | 2294 | { |
@@ -3266,14 +3122,6 @@ static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_intr_pending_f(void) | |||
3266 | { | 3122 | { |
3267 | return 0x1; | 3123 | return 0x1; |
3268 | } | 3124 | } |
3269 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_sec_pending_f(void) | ||
3270 | { | ||
3271 | return 0x80; | ||
3272 | } | ||
3273 | static inline u32 gr_gpc0_tpc0_tex_m_hww_esr_ecc_ded_pending_f(void) | ||
3274 | { | ||
3275 | return 0x100; | ||
3276 | } | ||
3277 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) | 3125 | static inline u32 gr_gpc0_tpc0_sm0_hww_warp_esr_r(void) |
3278 | { | 3126 | { |
3279 | return 0x00504730; | 3127 | return 0x00504730; |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h index 259d366d..38d63487 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_pbdma_gv11b.h | |||
@@ -574,4 +574,20 @@ static inline u32 pbdma_runlist_timeslice_enable_true_f(void) | |||
574 | { | 574 | { |
575 | return 0x10000000; | 575 | return 0x10000000; |
576 | } | 576 | } |
577 | static inline u32 pbdma_set_channel_info_r(u32 i) | ||
578 | { | ||
579 | return 0x000400fc + i*8192; | ||
580 | } | ||
581 | static inline u32 pbdma_set_channel_info_scg_type_graphics_compute0_f(void) | ||
582 | { | ||
583 | return 0x0; | ||
584 | } | ||
585 | static inline u32 pbdma_set_channel_info_scg_type_compute1_f(void) | ||
586 | { | ||
587 | return 0x1; | ||
588 | } | ||
589 | static inline u32 pbdma_set_channel_info_veid_f(u32 v) | ||
590 | { | ||
591 | return (v & 0x3f) << 8; | ||
592 | } | ||
577 | #endif | 593 | #endif |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h index 3477c03e..f57e0263 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_proj_gv11b.h | |||
@@ -114,17 +114,21 @@ static inline u32 proj_host_num_pbdma_v(void) | |||
114 | { | 114 | { |
115 | return 0x00000003; | 115 | return 0x00000003; |
116 | } | 116 | } |
117 | static inline u32 proj_litter_num_subctx_v(void) | ||
118 | { | ||
119 | return 0x00000040; | ||
120 | } | ||
117 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) | 121 | static inline u32 proj_scal_litter_num_tpc_per_gpc_v(void) |
118 | { | 122 | { |
119 | return 0x00000004; | 123 | return 0x00000004; |
120 | } | 124 | } |
121 | static inline u32 proj_scal_litter_num_fbps_v(void) | 125 | static inline u32 proj_scal_litter_num_fbps_v(void) |
122 | { | 126 | { |
123 | return 0x00000002; | 127 | return 0x00000001; |
124 | } | 128 | } |
125 | static inline u32 proj_scal_litter_num_fbpas_v(void) | 129 | static inline u32 proj_scal_litter_num_fbpas_v(void) |
126 | { | 130 | { |
127 | return 0x00000004; | 131 | return 0x00000002; |
128 | } | 132 | } |
129 | static inline u32 proj_scal_litter_num_gpcs_v(void) | 133 | static inline u32 proj_scal_litter_num_gpcs_v(void) |
130 | { | 134 | { |
diff --git a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h index 9cd2096a..7c89db4d 100644 --- a/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/hw_ram_gv11b.h | |||
@@ -86,37 +86,9 @@ static inline u32 ram_in_page_dir_base_vol_true_f(void) | |||
86 | { | 86 | { |
87 | return 0x4; | 87 | return 0x4; |
88 | } | 88 | } |
89 | static inline u32 ram_in_page_dir_base_fault_replay_tex_f(u32 v) | 89 | static inline u32 ram_in_page_dir_base_vol_false_f(void) |
90 | { | 90 | { |
91 | return (v & 0x1) << 4; | 91 | return 0x0; |
92 | } | ||
93 | static inline u32 ram_in_page_dir_base_fault_replay_tex_m(void) | ||
94 | { | ||
95 | return 0x1 << 4; | ||
96 | } | ||
97 | static inline u32 ram_in_page_dir_base_fault_replay_tex_w(void) | ||
98 | { | ||
99 | return 128; | ||
100 | } | ||
101 | static inline u32 ram_in_page_dir_base_fault_replay_tex_true_f(void) | ||
102 | { | ||
103 | return 0x10; | ||
104 | } | ||
105 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_f(u32 v) | ||
106 | { | ||
107 | return (v & 0x1) << 5; | ||
108 | } | ||
109 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_m(void) | ||
110 | { | ||
111 | return 0x1 << 5; | ||
112 | } | ||
113 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_w(void) | ||
114 | { | ||
115 | return 128; | ||
116 | } | ||
117 | static inline u32 ram_in_page_dir_base_fault_replay_gcc_true_f(void) | ||
118 | { | ||
119 | return 0x20; | ||
120 | } | 92 | } |
121 | static inline u32 ram_in_big_page_size_f(u32 v) | 93 | static inline u32 ram_in_big_page_size_f(u32 v) |
122 | { | 94 | { |
@@ -154,89 +126,293 @@ static inline u32 ram_in_page_dir_base_hi_w(void) | |||
154 | { | 126 | { |
155 | return 129; | 127 | return 129; |
156 | } | 128 | } |
157 | static inline u32 ram_in_adr_limit_lo_f(u32 v) | 129 | static inline u32 ram_in_engine_cs_w(void) |
158 | { | 130 | { |
159 | return (v & 0xfffff) << 12; | 131 | return 132; |
132 | } | ||
133 | static inline u32 ram_in_engine_cs_wfi_v(void) | ||
134 | { | ||
135 | return 0x00000000; | ||
160 | } | 136 | } |
161 | static inline u32 ram_in_adr_limit_lo_w(void) | 137 | static inline u32 ram_in_engine_cs_wfi_f(void) |
162 | { | 138 | { |
163 | return 130; | 139 | return 0x0; |
164 | } | 140 | } |
165 | static inline u32 ram_in_adr_limit_hi_f(u32 v) | 141 | static inline u32 ram_in_engine_cs_fg_v(void) |
166 | { | 142 | { |
167 | return (v & 0xffffffff) << 0; | 143 | return 0x00000001; |
168 | } | 144 | } |
169 | static inline u32 ram_in_adr_limit_hi_w(void) | 145 | static inline u32 ram_in_engine_cs_fg_f(void) |
170 | { | 146 | { |
171 | return 131; | 147 | return 0x8; |
172 | } | 148 | } |
173 | static inline u32 ram_in_engine_cs_w(void) | 149 | static inline u32 ram_in_engine_wfi_mode_w(void) |
174 | { | 150 | { |
175 | return 132; | 151 | return 132; |
176 | } | 152 | } |
177 | static inline u32 ram_in_engine_cs_wfi_v(void) | 153 | static inline u32 ram_in_engine_wfi_mode_physical_v(void) |
178 | { | 154 | { |
179 | return 0x00000000; | 155 | return 0x00000000; |
180 | } | 156 | } |
181 | static inline u32 ram_in_engine_cs_wfi_f(void) | 157 | static inline u32 ram_in_engine_wfi_mode_physical_f(void) |
182 | { | 158 | { |
183 | return 0x0; | 159 | return 0x0; |
184 | } | 160 | } |
185 | static inline u32 ram_in_engine_cs_fg_v(void) | 161 | static inline u32 ram_in_engine_wfi_mode_virtual_v(void) |
186 | { | 162 | { |
187 | return 0x00000001; | 163 | return 0x00000001; |
188 | } | 164 | } |
189 | static inline u32 ram_in_engine_cs_fg_f(void) | 165 | static inline u32 ram_in_engine_wfi_mode_virtual_f(void) |
190 | { | 166 | { |
191 | return 0x8; | 167 | return 0x4; |
192 | } | 168 | } |
193 | static inline u32 ram_in_gr_cs_w(void) | 169 | static inline u32 ram_in_engine_wfi_target_w(void) |
194 | { | 170 | { |
195 | return 132; | 171 | return 132; |
196 | } | 172 | } |
197 | static inline u32 ram_in_gr_cs_wfi_f(void) | 173 | static inline u32 ram_in_engine_wfi_target_sys_mem_coh_v(void) |
174 | { | ||
175 | return 0x00000002; | ||
176 | } | ||
177 | static inline u32 ram_in_engine_wfi_target_sys_mem_coh_f(void) | ||
178 | { | ||
179 | return 0x2; | ||
180 | } | ||
181 | static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_v(void) | ||
182 | { | ||
183 | return 0x00000003; | ||
184 | } | ||
185 | static inline u32 ram_in_engine_wfi_target_sys_mem_nocoh_f(void) | ||
186 | { | ||
187 | return 0x3; | ||
188 | } | ||
189 | static inline u32 ram_in_engine_wfi_target_local_mem_v(void) | ||
190 | { | ||
191 | return 0x00000000; | ||
192 | } | ||
193 | static inline u32 ram_in_engine_wfi_target_local_mem_f(void) | ||
198 | { | 194 | { |
199 | return 0x0; | 195 | return 0x0; |
200 | } | 196 | } |
201 | static inline u32 ram_in_gr_wfi_target_w(void) | 197 | static inline u32 ram_in_engine_wfi_ptr_lo_f(u32 v) |
202 | { | 198 | { |
203 | return 132; | 199 | return (v & 0xfffff) << 12; |
204 | } | 200 | } |
205 | static inline u32 ram_in_gr_wfi_mode_w(void) | 201 | static inline u32 ram_in_engine_wfi_ptr_lo_w(void) |
206 | { | 202 | { |
207 | return 132; | 203 | return 132; |
208 | } | 204 | } |
209 | static inline u32 ram_in_gr_wfi_mode_physical_v(void) | 205 | static inline u32 ram_in_engine_wfi_ptr_hi_f(u32 v) |
206 | { | ||
207 | return (v & 0xff) << 0; | ||
208 | } | ||
209 | static inline u32 ram_in_engine_wfi_ptr_hi_w(void) | ||
210 | { | ||
211 | return 133; | ||
212 | } | ||
213 | static inline u32 ram_in_engine_wfi_veid_f(u32 v) | ||
214 | { | ||
215 | return (v & 0x3f) << 0; | ||
216 | } | ||
217 | static inline u32 ram_in_engine_wfi_veid_w(void) | ||
218 | { | ||
219 | return 134; | ||
220 | } | ||
221 | static inline u32 ram_in_eng_method_buffer_addr_lo_f(u32 v) | ||
222 | { | ||
223 | return (v & 0xffffffff) << 0; | ||
224 | } | ||
225 | static inline u32 ram_in_eng_method_buffer_addr_lo_w(void) | ||
226 | { | ||
227 | return 136; | ||
228 | } | ||
229 | static inline u32 ram_in_eng_method_buffer_addr_hi_f(u32 v) | ||
230 | { | ||
231 | return (v & 0x1ffff) << 0; | ||
232 | } | ||
233 | static inline u32 ram_in_eng_method_buffer_addr_hi_w(void) | ||
234 | { | ||
235 | return 137; | ||
236 | } | ||
237 | static inline u32 ram_in_sc_page_dir_base_target_f(u32 v, u32 i) | ||
238 | { | ||
239 | return (v & 0x3) << (0 + i*0); | ||
240 | } | ||
241 | static inline u32 ram_in_sc_page_dir_base_target__size_1_v(void) | ||
242 | { | ||
243 | return 0x00000040; | ||
244 | } | ||
245 | static inline u32 ram_in_sc_page_dir_base_target_vid_mem_v(void) | ||
210 | { | 246 | { |
211 | return 0x00000000; | 247 | return 0x00000000; |
212 | } | 248 | } |
213 | static inline u32 ram_in_gr_wfi_mode_physical_f(void) | 249 | static inline u32 ram_in_sc_page_dir_base_target_invalid_v(void) |
214 | { | 250 | { |
215 | return 0x0; | 251 | return 0x00000001; |
252 | } | ||
253 | static inline u32 ram_in_sc_page_dir_base_target_sys_mem_coh_v(void) | ||
254 | { | ||
255 | return 0x00000002; | ||
216 | } | 256 | } |
217 | static inline u32 ram_in_gr_wfi_mode_virtual_v(void) | 257 | static inline u32 ram_in_sc_page_dir_base_target_sys_mem_ncoh_v(void) |
258 | { | ||
259 | return 0x00000003; | ||
260 | } | ||
261 | static inline u32 ram_in_sc_page_dir_base_vol_f(u32 v, u32 i) | ||
262 | { | ||
263 | return (v & 0x1) << (2 + i*0); | ||
264 | } | ||
265 | static inline u32 ram_in_sc_page_dir_base_vol__size_1_v(void) | ||
266 | { | ||
267 | return 0x00000040; | ||
268 | } | ||
269 | static inline u32 ram_in_sc_page_dir_base_vol_true_v(void) | ||
218 | { | 270 | { |
219 | return 0x00000001; | 271 | return 0x00000001; |
220 | } | 272 | } |
221 | static inline u32 ram_in_gr_wfi_mode_virtual_f(void) | 273 | static inline u32 ram_in_sc_page_dir_base_vol_false_v(void) |
222 | { | 274 | { |
223 | return 0x4; | 275 | return 0x00000000; |
276 | } | ||
277 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_f(u32 v, u32 i) | ||
278 | { | ||
279 | return (v & 0x1) << (4 + i*0); | ||
280 | } | ||
281 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex__size_1_v(void) | ||
282 | { | ||
283 | return 0x00000040; | ||
284 | } | ||
285 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_enabled_v(void) | ||
286 | { | ||
287 | return 0x00000001; | ||
288 | } | ||
289 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_disabled_v(void) | ||
290 | { | ||
291 | return 0x00000000; | ||
292 | } | ||
293 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_f(u32 v, u32 i) | ||
294 | { | ||
295 | return (v & 0x1) << (5 + i*0); | ||
296 | } | ||
297 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc__size_1_v(void) | ||
298 | { | ||
299 | return 0x00000040; | ||
300 | } | ||
301 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_enabled_v(void) | ||
302 | { | ||
303 | return 0x00000001; | ||
304 | } | ||
305 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_disabled_v(void) | ||
306 | { | ||
307 | return 0x00000000; | ||
308 | } | ||
309 | static inline u32 ram_in_sc_use_ver2_pt_format_f(u32 v, u32 i) | ||
310 | { | ||
311 | return (v & 0x1) << (10 + i*0); | ||
312 | } | ||
313 | static inline u32 ram_in_sc_use_ver2_pt_format__size_1_v(void) | ||
314 | { | ||
315 | return 0x00000040; | ||
316 | } | ||
317 | static inline u32 ram_in_sc_use_ver2_pt_format_false_v(void) | ||
318 | { | ||
319 | return 0x00000000; | ||
320 | } | ||
321 | static inline u32 ram_in_sc_use_ver2_pt_format_true_v(void) | ||
322 | { | ||
323 | return 0x00000001; | ||
324 | } | ||
325 | static inline u32 ram_in_sc_big_page_size_f(u32 v, u32 i) | ||
326 | { | ||
327 | return (v & 0x1) << (11 + i*0); | ||
328 | } | ||
329 | static inline u32 ram_in_sc_big_page_size__size_1_v(void) | ||
330 | { | ||
331 | return 0x00000040; | ||
332 | } | ||
333 | static inline u32 ram_in_sc_big_page_size_64kb_v(void) | ||
334 | { | ||
335 | return 0x00000001; | ||
336 | } | ||
337 | static inline u32 ram_in_sc_page_dir_base_lo_f(u32 v, u32 i) | ||
338 | { | ||
339 | return (v & 0xfffff) << (12 + i*0); | ||
340 | } | ||
341 | static inline u32 ram_in_sc_page_dir_base_lo__size_1_v(void) | ||
342 | { | ||
343 | return 0x00000040; | ||
344 | } | ||
345 | static inline u32 ram_in_sc_page_dir_base_hi_f(u32 v, u32 i) | ||
346 | { | ||
347 | return (v & 0xffffffff) << (0 + i*0); | ||
348 | } | ||
349 | static inline u32 ram_in_sc_page_dir_base_hi__size_1_v(void) | ||
350 | { | ||
351 | return 0x00000040; | ||
352 | } | ||
353 | static inline u32 ram_in_sc_page_dir_base_target_0_f(u32 v) | ||
354 | { | ||
355 | return (v & 0x3) << 0; | ||
356 | } | ||
357 | static inline u32 ram_in_sc_page_dir_base_target_0_w(void) | ||
358 | { | ||
359 | return 168; | ||
360 | } | ||
361 | static inline u32 ram_in_sc_page_dir_base_vol_0_f(u32 v) | ||
362 | { | ||
363 | return (v & 0x1) << 2; | ||
364 | } | ||
365 | static inline u32 ram_in_sc_page_dir_base_vol_0_w(void) | ||
366 | { | ||
367 | return 168; | ||
224 | } | 368 | } |
225 | static inline u32 ram_in_gr_wfi_ptr_lo_f(u32 v) | 369 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_f(u32 v) |
370 | { | ||
371 | return (v & 0x1) << 4; | ||
372 | } | ||
373 | static inline u32 ram_in_sc_page_dir_base_fault_replay_tex_0_w(void) | ||
374 | { | ||
375 | return 168; | ||
376 | } | ||
377 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_f(u32 v) | ||
378 | { | ||
379 | return (v & 0x1) << 5; | ||
380 | } | ||
381 | static inline u32 ram_in_sc_page_dir_base_fault_replay_gcc_0_w(void) | ||
382 | { | ||
383 | return 168; | ||
384 | } | ||
385 | static inline u32 ram_in_sc_use_ver2_pt_format_0_f(u32 v) | ||
386 | { | ||
387 | return (v & 0x1) << 10; | ||
388 | } | ||
389 | static inline u32 ram_in_sc_use_ver2_pt_format_0_w(void) | ||
390 | { | ||
391 | return 168; | ||
392 | } | ||
393 | static inline u32 ram_in_sc_big_page_size_0_f(u32 v) | ||
394 | { | ||
395 | return (v & 0x1) << 11; | ||
396 | } | ||
397 | static inline u32 ram_in_sc_big_page_size_0_w(void) | ||
398 | { | ||
399 | return 168; | ||
400 | } | ||
401 | static inline u32 ram_in_sc_page_dir_base_lo_0_f(u32 v) | ||
226 | { | 402 | { |
227 | return (v & 0xfffff) << 12; | 403 | return (v & 0xfffff) << 12; |
228 | } | 404 | } |
229 | static inline u32 ram_in_gr_wfi_ptr_lo_w(void) | 405 | static inline u32 ram_in_sc_page_dir_base_lo_0_w(void) |
230 | { | 406 | { |
231 | return 132; | 407 | return 168; |
232 | } | 408 | } |
233 | static inline u32 ram_in_gr_wfi_ptr_hi_f(u32 v) | 409 | static inline u32 ram_in_sc_page_dir_base_hi_0_f(u32 v) |
234 | { | 410 | { |
235 | return (v & 0xff) << 0; | 411 | return (v & 0xffffffff) << 0; |
236 | } | 412 | } |
237 | static inline u32 ram_in_gr_wfi_ptr_hi_w(void) | 413 | static inline u32 ram_in_sc_page_dir_base_hi_0_w(void) |
238 | { | 414 | { |
239 | return 133; | 415 | return 169; |
240 | } | 416 | } |
241 | static inline u32 ram_in_base_shift_v(void) | 417 | static inline u32 ram_in_base_shift_v(void) |
242 | { | 418 | { |
@@ -378,6 +554,10 @@ static inline u32 ram_fc_runlist_timeslice_w(void) | |||
378 | { | 554 | { |
379 | return 62; | 555 | return 62; |
380 | } | 556 | } |
557 | static inline u32 ram_fc_set_channel_info_w(void) | ||
558 | { | ||
559 | return 63; | ||
560 | } | ||
381 | static inline u32 ram_userd_base_shift_v(void) | 561 | static inline u32 ram_userd_base_shift_v(void) |
382 | { | 562 | { |
383 | return 0x00000009; | 563 | return 0x00000009; |
@@ -550,10 +730,6 @@ static inline u32 ram_rl_entry_tsg_tsgid_f(u32 v) | |||
550 | { | 730 | { |
551 | return (v & 0xfff) << 0; | 731 | return (v & 0xfff) << 0; |
552 | } | 732 | } |
553 | static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) | ||
554 | { | ||
555 | return 0x0000000c; | ||
556 | } | ||
557 | static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) | 733 | static inline u32 ram_rl_entry_chan_userd_ptr_align_shift_v(void) |
558 | { | 734 | { |
559 | return 0x00000008; | 735 | return 0x00000008; |
@@ -562,4 +738,8 @@ static inline u32 ram_rl_entry_chan_userd_align_shift_v(void) | |||
562 | { | 738 | { |
563 | return 0x00000008; | 739 | return 0x00000008; |
564 | } | 740 | } |
741 | static inline u32 ram_rl_entry_chan_inst_ptr_align_shift_v(void) | ||
742 | { | ||
743 | return 0x0000000c; | ||
744 | } | ||
565 | #endif | 745 | #endif |