diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2014-07-24 00:56:58 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:43 -0400 |
commit | 0858498f7b615467af33c4268fd0c0ac7fe19788 (patch) | |
tree | 44dc8ee02f5b5c516a5536e997ec766713282920 /drivers | |
parent | e5f82c848d75783c0e8d748dc7482ca29605fb12 (diff) |
nvgpu:Added PROD settings for ELPG sequencing
Added PROD settings for ELPG sequencing registers
Bug 200023161
Change-Id: Id313f9bc800d3a57f45aff0f0f609887565971be
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 133 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | 2 |
4 files changed, 142 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index b2ecade5..a03d5765 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -238,6 +238,7 @@ struct gpu_ops { | |||
238 | struct { | 238 | struct { |
239 | int (*prepare_ucode)(struct gk20a *g); | 239 | int (*prepare_ucode)(struct gk20a *g); |
240 | int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); | 240 | int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g); |
241 | int (*pmu_setup_elpg)(struct gk20a *g); | ||
241 | } pmu; | 242 | } pmu; |
242 | struct { | 243 | struct { |
243 | int (*init_clk_support)(struct gk20a *g); | 244 | int (*init_clk_support)(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 068611e3..7c441f53 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -2280,8 +2280,12 @@ static void pmu_setup_hw_enable_elpg(struct gk20a *g) | |||
2280 | /* Save zbc table after PMU is initialized. */ | 2280 | /* Save zbc table after PMU is initialized. */ |
2281 | gr_gk20a_pmu_save_zbc(g, 0xf); | 2281 | gr_gk20a_pmu_save_zbc(g, 0xf); |
2282 | 2282 | ||
2283 | if (g->elpg_enabled) | 2283 | if (g->elpg_enabled) { |
2284 | /* Init reg with prod values*/ | ||
2285 | if (g->ops.pmu.pmu_setup_elpg) | ||
2286 | g->ops.pmu.pmu_setup_elpg(g); | ||
2284 | gk20a_pmu_enable_elpg(g); | 2287 | gk20a_pmu_enable_elpg(g); |
2288 | } | ||
2285 | 2289 | ||
2286 | udelay(50); | 2290 | udelay(50); |
2287 | 2291 | ||
@@ -2296,6 +2300,7 @@ void gk20a_init_pmu_ops(struct gpu_ops *gops) | |||
2296 | { | 2300 | { |
2297 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; | 2301 | gops->pmu.prepare_ucode = gk20a_prepare_ucode; |
2298 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; | 2302 | gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1; |
2303 | gops->pmu.pmu_setup_elpg = NULL; | ||
2299 | } | 2304 | } |
2300 | 2305 | ||
2301 | int gk20a_init_pmu_support(struct gk20a *g) | 2306 | int gk20a_init_pmu_support(struct gk20a *g) |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 4b42b838..04f9e02a 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -15,6 +15,138 @@ | |||
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "acr_gm20b.h" | 17 | #include "acr_gm20b.h" |
18 | #include "pmu_gm20b.h" | ||
19 | |||
20 | /*! | ||
21 | * Structure/object which single register write need to be done during PG init | ||
22 | * sequence to set PROD values. | ||
23 | */ | ||
24 | struct pg_init_sequence_list { | ||
25 | u32 regaddr; | ||
26 | u32 writeval; | ||
27 | }; | ||
28 | |||
29 | |||
30 | /* PROD settings for ELPG sequencing registers*/ | ||
31 | static struct pg_init_sequence_list _pginitseq_gm20b[] = { | ||
32 | { 0x0010ab10, 0x8180}, | ||
33 | { 0x0010e118, 0x81818080}, | ||
34 | { 0x0010e068, 0}, | ||
35 | { 0x0010e06c, 0x00000080}, | ||
36 | { 0x0010e06c, 0x00000080}, | ||
37 | { 0x0010e06c, 0x00000081}, | ||
38 | { 0x0010e06c, 0x00000081}, | ||
39 | { 0x0010e06c, 0x00000082}, | ||
40 | { 0x0010e06c, 0x00000083}, | ||
41 | { 0x0010e06c, 0x00000083}, | ||
42 | { 0x0010e06c, 0x00000083}, | ||
43 | { 0x0010e06c, 0x00000083}, | ||
44 | { 0x0010e06c, 0x00000083}, | ||
45 | { 0x0010e06c, 0x00000080}, | ||
46 | { 0x0010e06c, 0x00000080}, | ||
47 | { 0x0010e06c, 0x00000081}, | ||
48 | { 0x0010e06c, 0x00000081}, | ||
49 | { 0x0010e06c, 0x00000082}, | ||
50 | { 0x0010e06c, 0x00000083}, | ||
51 | { 0x0010e06c, 0x00000083}, | ||
52 | { 0x0010e06c, 0x00000083}, | ||
53 | { 0x0010e06c, 0x00000083}, | ||
54 | { 0x0010e06c, 0x00000083}, | ||
55 | { 0x0010e06c, 0x00000080}, | ||
56 | { 0x0010e06c, 0x00000080}, | ||
57 | { 0x0010e06c, 0x00000081}, | ||
58 | { 0x0010e06c, 0x00000081}, | ||
59 | { 0x0010e06c, 0x00000082}, | ||
60 | { 0x0010e06c, 0x00000083}, | ||
61 | { 0x0010e06c, 0x00000083}, | ||
62 | { 0x0010e06c, 0x00000083}, | ||
63 | { 0x0010e06c, 0x00000083}, | ||
64 | { 0x0010e06c, 0x00000083}, | ||
65 | { 0x0010e06c, 0x00000080}, | ||
66 | { 0x0010e06c, 0x00000080}, | ||
67 | { 0x0010e06c, 0x00000081}, | ||
68 | { 0x0010e06c, 0x00000081}, | ||
69 | { 0x0010e06c, 0x00000082}, | ||
70 | { 0x0010e06c, 0x00000083}, | ||
71 | { 0x0010e06c, 0x00000083}, | ||
72 | { 0x0010e06c, 0x00000083}, | ||
73 | { 0x0010e06c, 0x00000083}, | ||
74 | { 0x0010e06c, 0x00000083}, | ||
75 | { 0x0010e06c, 0x00000080}, | ||
76 | { 0x0010e06c, 0x00000080}, | ||
77 | { 0x0010e06c, 0x00000081}, | ||
78 | { 0x0010e06c, 0x00000081}, | ||
79 | { 0x0010e06c, 0x00000082}, | ||
80 | { 0x0010e06c, 0x00000083}, | ||
81 | { 0x0010e06c, 0x00000083}, | ||
82 | { 0x0010e06c, 0x00000083}, | ||
83 | { 0x0010e06c, 0x00000083}, | ||
84 | { 0x0010e06c, 0x00000083}, | ||
85 | { 0x0010e06c, 0x00000080}, | ||
86 | { 0x0010e06c, 0x00000080}, | ||
87 | { 0x0010e06c, 0x00000081}, | ||
88 | { 0x0010e06c, 0x00000081}, | ||
89 | { 0x0010e06c, 0x00000082}, | ||
90 | { 0x0010e06c, 0x00000083}, | ||
91 | { 0x0010e06c, 0x00000083}, | ||
92 | { 0x0010e06c, 0x00000083}, | ||
93 | { 0x0010e06c, 0x00000083}, | ||
94 | { 0x0010e06c, 0x00000083}, | ||
95 | { 0x0010e06c, 0x00000080}, | ||
96 | { 0x0010e06c, 0x00000080}, | ||
97 | { 0x0010e06c, 0x00000081}, | ||
98 | { 0x0010e06c, 0x00000081}, | ||
99 | { 0x0010e06c, 0x00000082}, | ||
100 | { 0x0010e06c, 0x00000083}, | ||
101 | { 0x0010ab14, 0x00000000}, | ||
102 | { 0x0010ab18, 0x00000000}, | ||
103 | { 0x0010e024, 0x00000000}, | ||
104 | { 0x0010e028, 0x00000000}, | ||
105 | { 0x0010e11c, 0x00000000}, | ||
106 | { 0x0010e120, 0x00000000}, | ||
107 | { 0x0010ab1c, 0x00010011}, | ||
108 | { 0x0010e020, 0x001C0011}, | ||
109 | { 0x0010e124, 0x00030011}, | ||
110 | { 0x0010ab20, 0xfedcba98}, | ||
111 | { 0x0010ab24, 0x00000000}, | ||
112 | { 0x0010e02c, 0xfedcba98}, | ||
113 | { 0x0010e030, 0x00000000}, | ||
114 | { 0x0010e128, 0xfedcba98}, | ||
115 | { 0x0010e12c, 0x00000000}, | ||
116 | { 0x0010ab28, 0x71111111}, | ||
117 | { 0x0010ab2c, 0x70000000}, | ||
118 | { 0x0010e034, 0x71111111}, | ||
119 | { 0x0010e038, 0x70000000}, | ||
120 | { 0x0010e130, 0x71111111}, | ||
121 | { 0x0010e134, 0x70000000}, | ||
122 | { 0x0010ab30, 0x00000000}, | ||
123 | { 0x0010ab34, 0x00000001}, | ||
124 | { 0x00020004, 0x00000000}, | ||
125 | { 0x0010e138, 0x00000000}, | ||
126 | { 0x0010e040, 0x00000000}, | ||
127 | }; | ||
128 | |||
129 | int gm20b_pmu_setup_elpg(struct gk20a *g) | ||
130 | { | ||
131 | int ret = 0; | ||
132 | u32 reg_writes; | ||
133 | u32 index; | ||
134 | |||
135 | gk20a_dbg_fn(""); | ||
136 | |||
137 | if (g->elpg_enabled) { | ||
138 | reg_writes = ((sizeof(_pginitseq_gm20b) / | ||
139 | sizeof((_pginitseq_gm20b)[0]))); | ||
140 | /* Initialize registers with production values*/ | ||
141 | for (index = 0; index < reg_writes; index++) { | ||
142 | gk20a_writel(g, _pginitseq_gm20b[index].regaddr, | ||
143 | _pginitseq_gm20b[index].writeval); | ||
144 | } | ||
145 | } | ||
146 | |||
147 | gk20a_dbg_fn("done"); | ||
148 | return ret; | ||
149 | } | ||
18 | 150 | ||
19 | void gm20b_init_pmu_ops(struct gpu_ops *gops) | 151 | void gm20b_init_pmu_ops(struct gpu_ops *gops) |
20 | { | 152 | { |
@@ -23,4 +155,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) | |||
23 | #else | 155 | #else |
24 | gk20a_init_pmu_ops(gops); | 156 | gk20a_init_pmu_ops(gops); |
25 | #endif | 157 | #endif |
158 | gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg; | ||
26 | } | 159 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h index d36d3803..fc2f7d60 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h | |||
@@ -15,5 +15,7 @@ | |||
15 | 15 | ||
16 | #ifndef __PMU_GM20B_H_ | 16 | #ifndef __PMU_GM20B_H_ |
17 | #define __PMU_GM20B_H_ | 17 | #define __PMU_GM20B_H_ |
18 | |||
18 | void gm20b_init_pmu_ops(struct gpu_ops *gops); | 19 | void gm20b_init_pmu_ops(struct gpu_ops *gops); |
20 | |||
19 | #endif /*__PMU_GM20B_H_*/ | 21 | #endif /*__PMU_GM20B_H_*/ |