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authorDavid Nieto <dmartineznie@nvidia.com>2017-05-18 19:50:57 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-05-24 07:55:59 -0400
commit05388ad24a61c43a110e3d235622c23a356b5df7 (patch)
tree98e4eacd09571d8575a49977e268c3410a0e6834 /drivers
parent94226c9c1ed67be2dd146648b0460ef7346a2900 (diff)
gpu: nvgpu: re-arrange parity counters
(1) Re-arrange the structure for parity counters reporting so multiple units can be managed JIRA: GPUT19X-84 Change-Id: If59a883dfe22d5a1d91a6d0ed2f5a6254434ffcb Signed-off-by: David Nieto <dmartineznie@nvidia.com> Reviewed-on: http://git-master/r/1485276 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/ecc_t18x.h20
-rw-r--r--drivers/gpu/nvgpu/gk20a/ecc_gk20a.h48
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gk20a/gr_gk20a.h3
-rw-r--r--drivers/gpu/nvgpu/gp10b/ecc_gp10b.h41
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.c26
-rw-r--r--drivers/gpu/nvgpu/gp10b/gr_gp10b.h27
-rw-r--r--drivers/gpu/nvgpu/gp10b/ltc_gp10b.c4
-rw-r--r--drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c117
-rw-r--r--drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.h15
10 files changed, 211 insertions, 93 deletions
diff --git a/drivers/gpu/nvgpu/ecc_t18x.h b/drivers/gpu/nvgpu/ecc_t18x.h
new file mode 100644
index 00000000..11832ee1
--- /dev/null
+++ b/drivers/gpu/nvgpu/ecc_t18x.h
@@ -0,0 +1,20 @@
1/*
2 * NVIDIA T18x ECC
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15#ifndef _NVGPU_ECC_T18X_H_
16#define _NVGPU_ECC_T18X_H_
17
18#include "gp10b/ecc_gp10b.h"
19
20#endif
diff --git a/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
new file mode 100644
index 00000000..8ba01226
--- /dev/null
+++ b/drivers/gpu/nvgpu/gk20a/ecc_gk20a.h
@@ -0,0 +1,48 @@
1/*
2 * GK20A ECC
3 *
4 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18#ifndef ECC_GK20A_H
19#define ECC_GK20A_H
20
21#include <uapi/linux/nvgpu.h>
22
23struct gk20a_ecc_stat {
24 char **names;
25 u32 *counters;
26 struct hlist_node hash_node;
27};
28
29#ifdef CONFIG_ARCH_TEGRA_18x_SOC
30#include "ecc_t18x.h"
31#endif
32#ifdef CONFIG_TEGRA_19x_GPU
33#include "ecc_t19x.h"
34#endif
35
36struct ecc_gk20a {
37 /* Stats per engine */
38 struct {
39#ifdef CONFIG_ARCH_TEGRA_18x_SOC
40 struct ecc_gr_t18x t18x;
41#endif
42#ifdef CONFIG_TEGRA_19x_GPU
43 struct ecc_gr_t19x t19x;
44#endif
45 } gr;
46};
47
48#endif /*__ECC_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index cca414a2..68c10284 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -29,6 +29,7 @@ struct gk20a_ctxsw_trace;
29struct acr_desc; 29struct acr_desc;
30struct nvgpu_mem_alloc_tracker; 30struct nvgpu_mem_alloc_tracker;
31struct dbg_profiler_object_data; 31struct dbg_profiler_object_data;
32struct ecc_gk20a;
32 33
33#include <linux/sched.h> 34#include <linux/sched.h>
34#include <nvgpu/lock.h> 35#include <nvgpu/lock.h>
@@ -69,6 +70,7 @@ struct dbg_profiler_object_data;
69#include "pmgr/pmgr.h" 70#include "pmgr/pmgr.h"
70#include "therm/thrm.h" 71#include "therm/thrm.h"
71#endif 72#endif
73#include "ecc_gk20a.h"
72 74
73#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0) 75#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
74#define WRITE_ONCE(x, val) \ 76#define WRITE_ONCE(x, val) \
@@ -991,6 +993,7 @@ struct gk20a {
991 struct mm_gk20a mm; 993 struct mm_gk20a mm;
992 struct pmu_gk20a pmu; 994 struct pmu_gk20a pmu;
993 struct acr_desc acr; 995 struct acr_desc acr;
996 struct ecc_gk20a ecc;
994 struct cooling_device_gk20a gk20a_cdev; 997 struct cooling_device_gk20a gk20a_cdev;
995#ifdef CONFIG_ARCH_TEGRA_18x_SOC 998#ifdef CONFIG_ARCH_TEGRA_18x_SOC
996 struct clk_pmupstate clk_pmu; 999 struct clk_pmupstate clk_pmu;
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 5e49edb8..bf936418 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -374,9 +374,6 @@ struct gr_gk20a {
374#ifdef CONFIG_ARCH_TEGRA_18x_SOC 374#ifdef CONFIG_ARCH_TEGRA_18x_SOC
375 struct gr_t18x t18x; 375 struct gr_t18x t18x;
376#endif 376#endif
377#ifdef CONFIG_TEGRA_19x_GPU
378 struct gr_t19x t19x;
379#endif
380 377
381 u32 fbp_en_mask; 378 u32 fbp_en_mask;
382 u32 *fbp_rop_l2_en_mask; 379 u32 *fbp_rop_l2_en_mask;
diff --git a/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
new file mode 100644
index 00000000..454dcb20
--- /dev/null
+++ b/drivers/gpu/nvgpu/gp10b/ecc_gp10b.h
@@ -0,0 +1,41 @@
1/*
2 * GP10B ECC
3 *
4 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#ifndef _NVGPU_ECC_GP10B_H_
17#define _NVGPU_ECC_GP10B_H_
18
19#include <linux/version.h>
20
21struct ecc_gr_t18x {
22 struct gk20a_ecc_stat sm_lrf_single_err_count;
23 struct gk20a_ecc_stat sm_lrf_double_err_count;
24
25 struct gk20a_ecc_stat sm_shm_sec_count;
26 struct gk20a_ecc_stat sm_shm_sed_count;
27 struct gk20a_ecc_stat sm_shm_ded_count;
28
29 struct gk20a_ecc_stat tex_total_sec_pipe0_count;
30 struct gk20a_ecc_stat tex_total_ded_pipe0_count;
31 struct gk20a_ecc_stat tex_unique_sec_pipe0_count;
32 struct gk20a_ecc_stat tex_unique_ded_pipe0_count;
33 struct gk20a_ecc_stat tex_total_sec_pipe1_count;
34 struct gk20a_ecc_stat tex_total_ded_pipe1_count;
35 struct gk20a_ecc_stat tex_unique_sec_pipe1_count;
36 struct gk20a_ecc_stat tex_unique_ded_pipe1_count;
37
38 struct gk20a_ecc_stat l2_sec_count;
39 struct gk20a_ecc_stat l2_ded_count;
40};
41#endif
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 1853aaec..2c85a667 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -169,7 +169,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
169 lrf_ecc_ded_status, 169 lrf_ecc_ded_status,
170 &lrf_single_count_delta, 170 &lrf_single_count_delta,
171 lrf_double_count_delta); 171 lrf_double_count_delta);
172 g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters[tpc] += 172 g->ecc.gr.t18x.sm_lrf_single_err_count.counters[tpc] +=
173 lrf_single_count_delta; 173 lrf_single_count_delta;
174 } 174 }
175 if (lrf_ecc_ded_status) { 175 if (lrf_ecc_ded_status) {
@@ -181,7 +181,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
181 lrf_ecc_ded_status, 181 lrf_ecc_ded_status,
182 &lrf_double_count_delta, 182 &lrf_double_count_delta,
183 lrf_single_count_delta); 183 lrf_single_count_delta);
184 g->gr.t18x.ecc_stats.sm_lrf_double_err_count.counters[tpc] += 184 g->ecc.gr.t18x.sm_lrf_double_err_count.counters[tpc] +=
185 lrf_double_count_delta; 185 lrf_double_count_delta;
186 } 186 }
187 gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset, 187 gk20a_writel(g, gr_pri_gpc0_tpc0_sm_lrf_ecc_status_r() + offset,
@@ -206,9 +206,9 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
206 ecc_stats_reg_val = 206 ecc_stats_reg_val =
207 gk20a_readl(g, 207 gk20a_readl(g,
208 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); 208 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
209 g->gr.t18x.ecc_stats.sm_shm_sec_count.counters[tpc] += 209 g->ecc.gr.t18x.sm_shm_sec_count.counters[tpc] +=
210 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val); 210 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_v(ecc_stats_reg_val);
211 g->gr.t18x.ecc_stats.sm_shm_sed_count.counters[tpc] += 211 g->ecc.gr.t18x.sm_shm_sed_count.counters[tpc] +=
212 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val); 212 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_v(ecc_stats_reg_val);
213 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() | 213 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_corrected_m() |
214 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m()); 214 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_single_detected_m());
@@ -228,7 +228,7 @@ static int gr_gp10b_handle_sm_exception(struct gk20a *g, u32 gpc, u32 tpc,
228 ecc_stats_reg_val = 228 ecc_stats_reg_val =
229 gk20a_readl(g, 229 gk20a_readl(g,
230 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset); 230 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_r() + offset);
231 g->gr.t18x.ecc_stats.sm_shm_ded_count.counters[tpc] += 231 g->ecc.gr.t18x.sm_shm_ded_count.counters[tpc] +=
232 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val); 232 gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_v(ecc_stats_reg_val);
233 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m()); 233 ecc_stats_reg_val &= ~(gr_pri_gpc0_tpc0_sm_shm_ecc_err_count_double_detected_m());
234 gk20a_writel(g, 234 gk20a_writel(g,
@@ -269,7 +269,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
269 269
270 ecc_stats_reg_val = gk20a_readl(g, 270 ecc_stats_reg_val = gk20a_readl(g,
271 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); 271 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
272 g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count.counters[tpc] += 272 g->ecc.gr.t18x.tex_total_sec_pipe0_count.counters[tpc] +=
273 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); 273 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
274 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); 274 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
275 gk20a_writel(g, 275 gk20a_writel(g,
@@ -278,7 +278,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
278 278
279 ecc_stats_reg_val = gk20a_readl(g, 279 ecc_stats_reg_val = gk20a_readl(g,
280 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); 280 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
281 g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count.counters[tpc] += 281 g->ecc.gr.t18x.tex_unique_sec_pipe0_count.counters[tpc] +=
282 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); 282 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
283 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); 283 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
284 gk20a_writel(g, 284 gk20a_writel(g,
@@ -293,7 +293,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
293 293
294 ecc_stats_reg_val = gk20a_readl(g, 294 ecc_stats_reg_val = gk20a_readl(g,
295 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); 295 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
296 g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count.counters[tpc] += 296 g->ecc.gr.t18x.tex_total_sec_pipe1_count.counters[tpc] +=
297 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val); 297 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_v(ecc_stats_reg_val);
298 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m(); 298 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_sec_m();
299 gk20a_writel(g, 299 gk20a_writel(g,
@@ -302,7 +302,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
302 302
303 ecc_stats_reg_val = gk20a_readl(g, 303 ecc_stats_reg_val = gk20a_readl(g,
304 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); 304 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
305 g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count.counters[tpc] += 305 g->ecc.gr.t18x.tex_unique_sec_pipe1_count.counters[tpc] +=
306 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val); 306 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_v(ecc_stats_reg_val);
307 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m(); 307 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_sec_m();
308 gk20a_writel(g, 308 gk20a_writel(g,
@@ -325,7 +325,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
325 325
326 ecc_stats_reg_val = gk20a_readl(g, 326 ecc_stats_reg_val = gk20a_readl(g,
327 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); 327 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
328 g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count.counters[tpc] += 328 g->ecc.gr.t18x.tex_total_ded_pipe0_count.counters[tpc] +=
329 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); 329 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
330 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); 330 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
331 gk20a_writel(g, 331 gk20a_writel(g,
@@ -334,7 +334,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
334 334
335 ecc_stats_reg_val = gk20a_readl(g, 335 ecc_stats_reg_val = gk20a_readl(g,
336 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); 336 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
337 g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count.counters[tpc] += 337 g->ecc.gr.t18x.tex_unique_ded_pipe0_count.counters[tpc] +=
338 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); 338 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
339 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); 339 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
340 gk20a_writel(g, 340 gk20a_writel(g,
@@ -349,7 +349,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
349 349
350 ecc_stats_reg_val = gk20a_readl(g, 350 ecc_stats_reg_val = gk20a_readl(g,
351 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset); 351 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_r() + offset);
352 g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count.counters[tpc] += 352 g->ecc.gr.t18x.tex_total_ded_pipe1_count.counters[tpc] +=
353 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val); 353 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_v(ecc_stats_reg_val);
354 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m(); 354 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_total_ded_m();
355 gk20a_writel(g, 355 gk20a_writel(g,
@@ -358,7 +358,7 @@ static int gr_gp10b_handle_tex_exception(struct gk20a *g, u32 gpc, u32 tpc,
358 358
359 ecc_stats_reg_val = gk20a_readl(g, 359 ecc_stats_reg_val = gk20a_readl(g,
360 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset); 360 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_r() + offset);
361 g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count.counters[tpc] += 361 g->ecc.gr.t18x.tex_unique_ded_pipe1_count.counters[tpc] +=
362 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val); 362 gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_v(ecc_stats_reg_val);
363 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m(); 363 ecc_stats_reg_val &= ~gr_pri_gpc0_tpc0_tex_m_ecc_cnt_unique_ded_m();
364 gk20a_writel(g, 364 gk20a_writel(g,
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
index 588a7d8f..81ec7927 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.h
@@ -22,12 +22,6 @@
22 22
23struct gpu_ops; 23struct gpu_ops;
24 24
25struct gr_gp10b_ecc_stat {
26 char **names;
27 u32 *counters;
28 struct hlist_node hash_node;
29};
30
31enum { 25enum {
32 PASCAL_CHANNEL_GPFIFO_A = 0xC06F, 26 PASCAL_CHANNEL_GPFIFO_A = 0xC06F,
33 PASCAL_A = 0xC097, 27 PASCAL_A = 0xC097,
@@ -68,27 +62,6 @@ struct gr_t18x {
68 struct dentry *debugfs_dump_ctxsw_stats; 62 struct dentry *debugfs_dump_ctxsw_stats;
69 } ctx_vars; 63 } ctx_vars;
70 64
71 struct {
72 struct gr_gp10b_ecc_stat sm_lrf_single_err_count;
73 struct gr_gp10b_ecc_stat sm_lrf_double_err_count;
74
75 struct gr_gp10b_ecc_stat sm_shm_sec_count;
76 struct gr_gp10b_ecc_stat sm_shm_sed_count;
77 struct gr_gp10b_ecc_stat sm_shm_ded_count;
78
79 struct gr_gp10b_ecc_stat tex_total_sec_pipe0_count;
80 struct gr_gp10b_ecc_stat tex_total_ded_pipe0_count;
81 struct gr_gp10b_ecc_stat tex_unique_sec_pipe0_count;
82 struct gr_gp10b_ecc_stat tex_unique_ded_pipe0_count;
83 struct gr_gp10b_ecc_stat tex_total_sec_pipe1_count;
84 struct gr_gp10b_ecc_stat tex_total_ded_pipe1_count;
85 struct gr_gp10b_ecc_stat tex_unique_sec_pipe1_count;
86 struct gr_gp10b_ecc_stat tex_unique_ded_pipe1_count;
87
88 struct gr_gp10b_ecc_stat l2_sec_count;
89 struct gr_gp10b_ecc_stat l2_ded_count;
90 } ecc_stats;
91
92 u32 fecs_feature_override_ecc_val; 65 u32 fecs_feature_override_ecc_val;
93 66
94 int cilp_preempt_pending_chid; 67 int cilp_preempt_pending_chid;
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
index e65e3d06..165e93fe 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
@@ -149,7 +149,7 @@ static void gp10b_ltc_isr(struct gk20a *g)
149 ecc_stats_reg_val = 149 ecc_stats_reg_val =
150 gk20a_readl(g, 150 gk20a_readl(g,
151 ltc_ltc0_lts0_dstg_ecc_report_r() + offset); 151 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
152 g->gr.t18x.ecc_stats.l2_sec_count.counters[ltc] += 152 g->ecc.gr.t18x.l2_sec_count.counters[ltc] +=
153 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val); 153 ltc_ltc0_lts0_dstg_ecc_report_sec_count_v(ecc_stats_reg_val);
154 ecc_stats_reg_val &= 154 ecc_stats_reg_val &=
155 ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m()); 155 ~(ltc_ltc0_lts0_dstg_ecc_report_sec_count_m());
@@ -169,7 +169,7 @@ static void gp10b_ltc_isr(struct gk20a *g)
169 ecc_stats_reg_val = 169 ecc_stats_reg_val =
170 gk20a_readl(g, 170 gk20a_readl(g,
171 ltc_ltc0_lts0_dstg_ecc_report_r() + offset); 171 ltc_ltc0_lts0_dstg_ecc_report_r() + offset);
172 g->gr.t18x.ecc_stats.l2_ded_count.counters[ltc] += 172 g->ecc.gr.t18x.l2_ded_count.counters[ltc] +=
173 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val); 173 ltc_ltc0_lts0_dstg_ecc_report_ded_count_v(ecc_stats_reg_val);
174 ecc_stats_reg_val &= 174 ecc_stats_reg_val &=
175 ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m()); 175 ~(ltc_ltc0_lts0_dstg_ecc_report_ded_count_m());
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c
index 1dedd593..84175e98 100644
--- a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c
+++ b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.c
@@ -484,13 +484,15 @@ static ssize_t ecc_stat_show(struct device *dev,
484 const char *ecc_stat_full_name = attr->attr.name; 484 const char *ecc_stat_full_name = attr->attr.name;
485 const char *ecc_stat_base_name; 485 const char *ecc_stat_base_name;
486 unsigned int hw_unit; 486 unsigned int hw_unit;
487 struct gr_gp10b_ecc_stat *ecc_stat; 487 struct gk20a_ecc_stat *ecc_stat;
488 u32 hash_key; 488 u32 hash_key;
489 489
490 if (sscanf(ecc_stat_full_name, "ltc%u", &hw_unit) == 1) { 490 if (sscanf(ecc_stat_full_name, "ltc%u", &hw_unit) == 1) {
491 ecc_stat_base_name = &(ecc_stat_full_name[strlen("ltc0_")]); 491 ecc_stat_base_name = &(ecc_stat_full_name[strlen("ltc0_")]);
492 } else if (sscanf(ecc_stat_full_name, "gpc0_tpc%u", &hw_unit) == 1) { 492 } else if (sscanf(ecc_stat_full_name, "gpc0_tpc%u", &hw_unit) == 1) {
493 ecc_stat_base_name = &(ecc_stat_full_name[strlen("gpc0_tpc0_")]); 493 ecc_stat_base_name = &(ecc_stat_full_name[strlen("gpc0_tpc0_")]);
494 } else if (sscanf(ecc_stat_full_name, "gpc%u", &hw_unit) == 1) {
495 ecc_stat_base_name = &(ecc_stat_full_name[strlen("gpc0_")]);
494 } else { 496 } else {
495 return snprintf(buf, 497 return snprintf(buf,
496 PAGE_SIZE, 498 PAGE_SIZE,
@@ -512,20 +514,39 @@ static ssize_t ecc_stat_show(struct device *dev,
512int gr_gp10b_ecc_stat_create(struct device *dev, 514int gr_gp10b_ecc_stat_create(struct device *dev,
513 int is_l2, 515 int is_l2,
514 char *ecc_stat_name, 516 char *ecc_stat_name,
515 struct gr_gp10b_ecc_stat *ecc_stat, 517 struct gk20a_ecc_stat *ecc_stat,
516 struct device_attribute *dev_attr_array) 518 struct device_attribute *dev_attr_array)
517{ 519{
518 int error = 0;
519 struct gk20a *g = get_gk20a(dev); 520 struct gk20a *g = get_gk20a(dev);
521 char *ltc_unit_name = "ltc";
522 char *gr_unit_name = "gpc0_tpc";
520 int num_hw_units = 0; 523 int num_hw_units = 0;
521 int hw_unit = 0;
522 u32 hash_key = 0;
523 524
524 if (is_l2) 525 if (is_l2)
525 num_hw_units = g->ltc_count; 526 num_hw_units = g->ltc_count;
526 else 527 else
527 num_hw_units = g->gr.tpc_count; 528 num_hw_units = g->gr.tpc_count;
528 529
530
531 return gp10b_ecc_stat_create(dev, num_hw_units,
532 is_l2 ? ltc_unit_name : gr_unit_name,
533 ecc_stat_name,
534 ecc_stat,
535 dev_attr_array);
536}
537
538int gp10b_ecc_stat_create(struct device *dev,
539 int num_hw_units,
540 char *ecc_unit_name,
541 char *ecc_stat_name,
542 struct gk20a_ecc_stat *ecc_stat,
543 struct device_attribute *dev_attr_array)
544{
545 int error = 0;
546 struct gk20a *g = get_gk20a(dev);
547 int hw_unit = 0;
548 u32 hash_key = 0;
549
529 /* Allocate arrays */ 550 /* Allocate arrays */
530 dev_attr_array = nvgpu_kzalloc(g, sizeof(struct device_attribute) * 551 dev_attr_array = nvgpu_kzalloc(g, sizeof(struct device_attribute) *
531 num_hw_units); 552 num_hw_units);
@@ -538,16 +559,10 @@ int gr_gp10b_ecc_stat_create(struct device *dev,
538 559
539 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { 560 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
540 /* Fill in struct device_attribute members */ 561 /* Fill in struct device_attribute members */
541 if (is_l2)
542 snprintf(ecc_stat->names[hw_unit], 562 snprintf(ecc_stat->names[hw_unit],
543 ECC_STAT_NAME_MAX_SIZE, 563 ECC_STAT_NAME_MAX_SIZE,
544 "ltc%d_%s", 564 "%s%d_%s",
545 hw_unit, 565 ecc_unit_name,
546 ecc_stat_name);
547 else
548 snprintf(ecc_stat->names[hw_unit],
549 ECC_STAT_NAME_MAX_SIZE,
550 "gpc0_tpc%d_%s",
551 hw_unit, 566 hw_unit,
552 ecc_stat_name); 567 ecc_stat_name);
553 568
@@ -572,18 +587,28 @@ int gr_gp10b_ecc_stat_create(struct device *dev,
572 587
573void gr_gp10b_ecc_stat_remove(struct device *dev, 588void gr_gp10b_ecc_stat_remove(struct device *dev,
574 int is_l2, 589 int is_l2,
575 struct gr_gp10b_ecc_stat *ecc_stat, 590 struct gk20a_ecc_stat *ecc_stat,
576 struct device_attribute *dev_attr_array) 591 struct device_attribute *dev_attr_array)
577{ 592{
578 struct gk20a *g = get_gk20a(dev); 593 struct gk20a *g = get_gk20a(dev);
579 int num_hw_units = 0; 594 int num_hw_units = 0;
580 int hw_unit = 0;
581 595
582 if (is_l2) 596 if (is_l2)
583 num_hw_units = g->ltc_count; 597 num_hw_units = g->ltc_count;
584 else 598 else
585 num_hw_units = g->gr.tpc_count; 599 num_hw_units = g->gr.tpc_count;
586 600
601 gp10b_ecc_stat_remove(dev, num_hw_units, ecc_stat, dev_attr_array);
602}
603
604void gp10b_ecc_stat_remove(struct device *dev,
605 int num_hw_units,
606 struct gk20a_ecc_stat *ecc_stat,
607 struct device_attribute *dev_attr_array)
608{
609 struct gk20a *g = get_gk20a(dev);
610 int hw_unit = 0;
611
587 /* Remove sysfs files */ 612 /* Remove sysfs files */
588 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) { 613 for (hw_unit = 0; hw_unit < num_hw_units; hw_unit++) {
589 device_remove_file(dev, &dev_attr_array[hw_unit]); 614 device_remove_file(dev, &dev_attr_array[hw_unit]);
@@ -610,86 +635,86 @@ void gr_gp10b_create_sysfs(struct device *dev)
610 initialized multiple times but we only need to create the ECC 635 initialized multiple times but we only need to create the ECC
611 stats once. Therefore, add the following check to avoid 636 stats once. Therefore, add the following check to avoid
612 creating duplicate stat sysfs nodes. */ 637 creating duplicate stat sysfs nodes. */
613 if (g->gr.t18x.ecc_stats.sm_lrf_single_err_count.counters != NULL) 638 if (g->ecc.gr.t18x.sm_lrf_single_err_count.counters != NULL)
614 return; 639 return;
615 640
616 error |= gr_gp10b_ecc_stat_create(dev, 641 error |= gr_gp10b_ecc_stat_create(dev,
617 0, 642 0,
618 "sm_lrf_ecc_single_err_count", 643 "sm_lrf_ecc_single_err_count",
619 &g->gr.t18x.ecc_stats.sm_lrf_single_err_count, 644 &g->ecc.gr.t18x.sm_lrf_single_err_count,
620 dev_attr_sm_lrf_ecc_single_err_count_array); 645 dev_attr_sm_lrf_ecc_single_err_count_array);
621 error |= gr_gp10b_ecc_stat_create(dev, 646 error |= gr_gp10b_ecc_stat_create(dev,
622 0, 647 0,
623 "sm_lrf_ecc_double_err_count", 648 "sm_lrf_ecc_double_err_count",
624 &g->gr.t18x.ecc_stats.sm_lrf_double_err_count, 649 &g->ecc.gr.t18x.sm_lrf_double_err_count,
625 dev_attr_sm_lrf_ecc_double_err_count_array); 650 dev_attr_sm_lrf_ecc_double_err_count_array);
626 651
627 error |= gr_gp10b_ecc_stat_create(dev, 652 error |= gr_gp10b_ecc_stat_create(dev,
628 0, 653 0,
629 "sm_shm_ecc_sec_count", 654 "sm_shm_ecc_sec_count",
630 &g->gr.t18x.ecc_stats.sm_shm_sec_count, 655 &g->ecc.gr.t18x.sm_shm_sec_count,
631 dev_attr_sm_shm_ecc_sec_count_array); 656 dev_attr_sm_shm_ecc_sec_count_array);
632 error |= gr_gp10b_ecc_stat_create(dev, 657 error |= gr_gp10b_ecc_stat_create(dev,
633 0, 658 0,
634 "sm_shm_ecc_sed_count", 659 "sm_shm_ecc_sed_count",
635 &g->gr.t18x.ecc_stats.sm_shm_sed_count, 660 &g->ecc.gr.t18x.sm_shm_sed_count,
636 dev_attr_sm_shm_ecc_sed_count_array); 661 dev_attr_sm_shm_ecc_sed_count_array);
637 error |= gr_gp10b_ecc_stat_create(dev, 662 error |= gr_gp10b_ecc_stat_create(dev,
638 0, 663 0,
639 "sm_shm_ecc_ded_count", 664 "sm_shm_ecc_ded_count",
640 &g->gr.t18x.ecc_stats.sm_shm_ded_count, 665 &g->ecc.gr.t18x.sm_shm_ded_count,
641 dev_attr_sm_shm_ecc_ded_count_array); 666 dev_attr_sm_shm_ecc_ded_count_array);
642 667
643 error |= gr_gp10b_ecc_stat_create(dev, 668 error |= gr_gp10b_ecc_stat_create(dev,
644 0, 669 0,
645 "tex_ecc_total_sec_pipe0_count", 670 "tex_ecc_total_sec_pipe0_count",
646 &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count, 671 &g->ecc.gr.t18x.tex_total_sec_pipe0_count,
647 dev_attr_tex_ecc_total_sec_pipe0_count_array); 672 dev_attr_tex_ecc_total_sec_pipe0_count_array);
648 error |= gr_gp10b_ecc_stat_create(dev, 673 error |= gr_gp10b_ecc_stat_create(dev,
649 0, 674 0,
650 "tex_ecc_total_ded_pipe0_count", 675 "tex_ecc_total_ded_pipe0_count",
651 &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count, 676 &g->ecc.gr.t18x.tex_total_ded_pipe0_count,
652 dev_attr_tex_ecc_total_ded_pipe0_count_array); 677 dev_attr_tex_ecc_total_ded_pipe0_count_array);
653 error |= gr_gp10b_ecc_stat_create(dev, 678 error |= gr_gp10b_ecc_stat_create(dev,
654 0, 679 0,
655 "tex_ecc_unique_sec_pipe0_count", 680 "tex_ecc_unique_sec_pipe0_count",
656 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count, 681 &g->ecc.gr.t18x.tex_unique_sec_pipe0_count,
657 dev_attr_tex_ecc_unique_sec_pipe0_count_array); 682 dev_attr_tex_ecc_unique_sec_pipe0_count_array);
658 error |= gr_gp10b_ecc_stat_create(dev, 683 error |= gr_gp10b_ecc_stat_create(dev,
659 0, 684 0,
660 "tex_ecc_unique_ded_pipe0_count", 685 "tex_ecc_unique_ded_pipe0_count",
661 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count, 686 &g->ecc.gr.t18x.tex_unique_ded_pipe0_count,
662 dev_attr_tex_ecc_unique_ded_pipe0_count_array); 687 dev_attr_tex_ecc_unique_ded_pipe0_count_array);
663 error |= gr_gp10b_ecc_stat_create(dev, 688 error |= gr_gp10b_ecc_stat_create(dev,
664 0, 689 0,
665 "tex_ecc_total_sec_pipe1_count", 690 "tex_ecc_total_sec_pipe1_count",
666 &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count, 691 &g->ecc.gr.t18x.tex_total_sec_pipe1_count,
667 dev_attr_tex_ecc_total_sec_pipe1_count_array); 692 dev_attr_tex_ecc_total_sec_pipe1_count_array);
668 error |= gr_gp10b_ecc_stat_create(dev, 693 error |= gr_gp10b_ecc_stat_create(dev,
669 0, 694 0,
670 "tex_ecc_total_ded_pipe1_count", 695 "tex_ecc_total_ded_pipe1_count",
671 &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count, 696 &g->ecc.gr.t18x.tex_total_ded_pipe1_count,
672 dev_attr_tex_ecc_total_ded_pipe1_count_array); 697 dev_attr_tex_ecc_total_ded_pipe1_count_array);
673 error |= gr_gp10b_ecc_stat_create(dev, 698 error |= gr_gp10b_ecc_stat_create(dev,
674 0, 699 0,
675 "tex_ecc_unique_sec_pipe1_count", 700 "tex_ecc_unique_sec_pipe1_count",
676 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count, 701 &g->ecc.gr.t18x.tex_unique_sec_pipe1_count,
677 dev_attr_tex_ecc_unique_sec_pipe1_count_array); 702 dev_attr_tex_ecc_unique_sec_pipe1_count_array);
678 error |= gr_gp10b_ecc_stat_create(dev, 703 error |= gr_gp10b_ecc_stat_create(dev,
679 0, 704 0,
680 "tex_ecc_unique_ded_pipe1_count", 705 "tex_ecc_unique_ded_pipe1_count",
681 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count, 706 &g->ecc.gr.t18x.tex_unique_ded_pipe1_count,
682 dev_attr_tex_ecc_unique_ded_pipe1_count_array); 707 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
683 708
684 error |= gr_gp10b_ecc_stat_create(dev, 709 error |= gr_gp10b_ecc_stat_create(dev,
685 1, 710 1,
686 "lts0_ecc_sec_count", 711 "lts0_ecc_sec_count",
687 &g->gr.t18x.ecc_stats.l2_sec_count, 712 &g->ecc.gr.t18x.l2_sec_count,
688 dev_attr_l2_ecc_sec_count_array); 713 dev_attr_l2_ecc_sec_count_array);
689 error |= gr_gp10b_ecc_stat_create(dev, 714 error |= gr_gp10b_ecc_stat_create(dev,
690 1, 715 1,
691 "lts0_ecc_ded_count", 716 "lts0_ecc_ded_count",
692 &g->gr.t18x.ecc_stats.l2_ded_count, 717 &g->ecc.gr.t18x.l2_ded_count,
693 dev_attr_l2_ecc_ded_count_array); 718 dev_attr_l2_ecc_ded_count_array);
694 719
695 if (error) 720 if (error)
@@ -702,65 +727,65 @@ static void gr_gp10b_remove_sysfs(struct device *dev)
702 727
703 gr_gp10b_ecc_stat_remove(dev, 728 gr_gp10b_ecc_stat_remove(dev,
704 0, 729 0,
705 &g->gr.t18x.ecc_stats.sm_lrf_single_err_count, 730 &g->ecc.gr.t18x.sm_lrf_single_err_count,
706 dev_attr_sm_lrf_ecc_single_err_count_array); 731 dev_attr_sm_lrf_ecc_single_err_count_array);
707 gr_gp10b_ecc_stat_remove(dev, 732 gr_gp10b_ecc_stat_remove(dev,
708 0, 733 0,
709 &g->gr.t18x.ecc_stats.sm_lrf_double_err_count, 734 &g->ecc.gr.t18x.sm_lrf_double_err_count,
710 dev_attr_sm_lrf_ecc_double_err_count_array); 735 dev_attr_sm_lrf_ecc_double_err_count_array);
711 736
712 gr_gp10b_ecc_stat_remove(dev, 737 gr_gp10b_ecc_stat_remove(dev,
713 0, 738 0,
714 &g->gr.t18x.ecc_stats.sm_shm_sec_count, 739 &g->ecc.gr.t18x.sm_shm_sec_count,
715 dev_attr_sm_shm_ecc_sec_count_array); 740 dev_attr_sm_shm_ecc_sec_count_array);
716 gr_gp10b_ecc_stat_remove(dev, 741 gr_gp10b_ecc_stat_remove(dev,
717 0, 742 0,
718 &g->gr.t18x.ecc_stats.sm_shm_sed_count, 743 &g->ecc.gr.t18x.sm_shm_sed_count,
719 dev_attr_sm_shm_ecc_sed_count_array); 744 dev_attr_sm_shm_ecc_sed_count_array);
720 gr_gp10b_ecc_stat_remove(dev, 745 gr_gp10b_ecc_stat_remove(dev,
721 0, 746 0,
722 &g->gr.t18x.ecc_stats.sm_shm_ded_count, 747 &g->ecc.gr.t18x.sm_shm_ded_count,
723 dev_attr_sm_shm_ecc_ded_count_array); 748 dev_attr_sm_shm_ecc_ded_count_array);
724 749
725 gr_gp10b_ecc_stat_remove(dev, 750 gr_gp10b_ecc_stat_remove(dev,
726 0, 751 0,
727 &g->gr.t18x.ecc_stats.tex_total_sec_pipe0_count, 752 &g->ecc.gr.t18x.tex_total_sec_pipe0_count,
728 dev_attr_tex_ecc_total_sec_pipe0_count_array); 753 dev_attr_tex_ecc_total_sec_pipe0_count_array);
729 gr_gp10b_ecc_stat_remove(dev, 754 gr_gp10b_ecc_stat_remove(dev,
730 0, 755 0,
731 &g->gr.t18x.ecc_stats.tex_total_ded_pipe0_count, 756 &g->ecc.gr.t18x.tex_total_ded_pipe0_count,
732 dev_attr_tex_ecc_total_ded_pipe0_count_array); 757 dev_attr_tex_ecc_total_ded_pipe0_count_array);
733 gr_gp10b_ecc_stat_remove(dev, 758 gr_gp10b_ecc_stat_remove(dev,
734 0, 759 0,
735 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe0_count, 760 &g->ecc.gr.t18x.tex_unique_sec_pipe0_count,
736 dev_attr_tex_ecc_unique_sec_pipe0_count_array); 761 dev_attr_tex_ecc_unique_sec_pipe0_count_array);
737 gr_gp10b_ecc_stat_remove(dev, 762 gr_gp10b_ecc_stat_remove(dev,
738 0, 763 0,
739 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe0_count, 764 &g->ecc.gr.t18x.tex_unique_ded_pipe0_count,
740 dev_attr_tex_ecc_unique_ded_pipe0_count_array); 765 dev_attr_tex_ecc_unique_ded_pipe0_count_array);
741 gr_gp10b_ecc_stat_remove(dev, 766 gr_gp10b_ecc_stat_remove(dev,
742 0, 767 0,
743 &g->gr.t18x.ecc_stats.tex_total_sec_pipe1_count, 768 &g->ecc.gr.t18x.tex_total_sec_pipe1_count,
744 dev_attr_tex_ecc_total_sec_pipe1_count_array); 769 dev_attr_tex_ecc_total_sec_pipe1_count_array);
745 gr_gp10b_ecc_stat_remove(dev, 770 gr_gp10b_ecc_stat_remove(dev,
746 0, 771 0,
747 &g->gr.t18x.ecc_stats.tex_total_ded_pipe1_count, 772 &g->ecc.gr.t18x.tex_total_ded_pipe1_count,
748 dev_attr_tex_ecc_total_ded_pipe1_count_array); 773 dev_attr_tex_ecc_total_ded_pipe1_count_array);
749 gr_gp10b_ecc_stat_remove(dev, 774 gr_gp10b_ecc_stat_remove(dev,
750 0, 775 0,
751 &g->gr.t18x.ecc_stats.tex_unique_sec_pipe1_count, 776 &g->ecc.gr.t18x.tex_unique_sec_pipe1_count,
752 dev_attr_tex_ecc_unique_sec_pipe1_count_array); 777 dev_attr_tex_ecc_unique_sec_pipe1_count_array);
753 gr_gp10b_ecc_stat_remove(dev, 778 gr_gp10b_ecc_stat_remove(dev,
754 0, 779 0,
755 &g->gr.t18x.ecc_stats.tex_unique_ded_pipe1_count, 780 &g->ecc.gr.t18x.tex_unique_ded_pipe1_count,
756 dev_attr_tex_ecc_unique_ded_pipe1_count_array); 781 dev_attr_tex_ecc_unique_ded_pipe1_count_array);
757 782
758 gr_gp10b_ecc_stat_remove(dev, 783 gr_gp10b_ecc_stat_remove(dev,
759 1, 784 1,
760 &g->gr.t18x.ecc_stats.l2_sec_count, 785 &g->ecc.gr.t18x.l2_sec_count,
761 dev_attr_l2_ecc_sec_count_array); 786 dev_attr_l2_ecc_sec_count_array);
762 gr_gp10b_ecc_stat_remove(dev, 787 gr_gp10b_ecc_stat_remove(dev,
763 1, 788 1,
764 &g->gr.t18x.ecc_stats.l2_ded_count, 789 &g->ecc.gr.t18x.l2_ded_count,
765 dev_attr_l2_ecc_ded_count_array); 790 dev_attr_l2_ecc_ded_count_array);
766} 791}
diff --git a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.h b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.h
index 0fcb9f39..fb69fa98 100644
--- a/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.h
+++ b/drivers/gpu/nvgpu/tegra/linux/platform_gp10b_tegra.h
@@ -22,12 +22,23 @@
22int gr_gp10b_ecc_stat_create(struct device *dev, 22int gr_gp10b_ecc_stat_create(struct device *dev,
23 int is_l2, 23 int is_l2,
24 char *ecc_stat_name, 24 char *ecc_stat_name,
25 struct gr_gp10b_ecc_stat *ecc_stat, 25 struct gk20a_ecc_stat *ecc_stat,
26 struct device_attribute *dev_attr_array);
27int gp10b_ecc_stat_create(struct device *dev,
28 int hw_units,
29 char *ecc_unit_name,
30 char *ecc_stat_name,
31 struct gk20a_ecc_stat *ecc_stat,
26 struct device_attribute *dev_attr_array); 32 struct device_attribute *dev_attr_array);
27 33
28void gr_gp10b_ecc_stat_remove(struct device *dev, 34void gr_gp10b_ecc_stat_remove(struct device *dev,
29 int is_l2, 35 int is_l2,
30 struct gr_gp10b_ecc_stat *ecc_stat, 36 struct gk20a_ecc_stat *ecc_stat,
37 struct device_attribute *dev_attr_array);
38
39void gp10b_ecc_stat_remove(struct device *dev,
40 int hw_units,
41 struct gk20a_ecc_stat *ecc_stat,
31 struct device_attribute *dev_attr_array); 42 struct device_attribute *dev_attr_array);
32 43
33int gp10b_tegra_remove(struct device *dev); 44int gp10b_tegra_remove(struct device *dev);