summaryrefslogtreecommitdiffstats
path: root/drivers
diff options
context:
space:
mode:
authorMahantesh Kumbar <mkumbar@nvidia.com>2017-01-31 02:26:10 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-08 00:53:39 -0500
commit02190c7597d3b1a04ebcbc746b41f949ab699a18 (patch)
tree882e161d094e43a97bd51973795ea3ff6cd5d4cb /drivers
parent3335ff9fe90d3f523a463107bae864b011590182 (diff)
gpu: nvgpu: PMU interface headers reorganization
Moved PMU/Falcon interface which are present in pmu_gk20a.h & pmu_common.h to new files as per feature nvgpu_gpmu_cmdif.h - Top-level header-file that defines the command/message interfaces used to communicate with PMU gpmuif_pmu.h - PMU Command/Message init interfaces gpmuif_cmn.h - Common definitions used by interfaces Jira NVGPU-19 Change-Id: Id8ea6075e4dbba7697036951dcb85487eb861710 Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: http://git-master/r/1296415 GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_common.h48
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.h310
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h121
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h215
-rw-r--r--drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h85
5 files changed, 423 insertions, 356 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_common.h b/drivers/gpu/nvgpu/gk20a/pmu_common.h
index de37caeb..3b3362c1 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_common.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_common.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2011-2016, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2011-2017, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -72,24 +72,6 @@ struct pmu_dmem {
72 u32 offset; 72 u32 offset;
73}; 73};
74 74
75/* Make sure size of this structure is a multiple of 4 bytes */
76struct pmu_cmdline_args_v0 {
77 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
78 u32 falc_trace_size; /* falctrace buffer size (bytes) */
79 u32 falc_trace_dma_base; /* 256-byte block address */
80 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
81 struct pmu_mem_v0 gc6_ctx; /* dmem offset of gc6 context */
82};
83
84struct pmu_cmdline_args_v1 {
85 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
86 u32 falc_trace_size; /* falctrace buffer size (bytes) */
87 u32 falc_trace_dma_base; /* 256-byte block address */
88 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
89 u8 secure_mode;
90 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */
91};
92
93struct flcn_u64 { 75struct flcn_u64 {
94 u32 lo; 76 u32 lo;
95 u32 hi; 77 u32 hi;
@@ -148,34 +130,6 @@ typedef u8 flcn_status;
148 130
149#define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1)) 131#define ALIGN_UP(v, gran) (((v) + ((gran) - 1)) & ~((gran)-1))
150 132
151/*!
152 * Falcon PMU DMA's minimum size in bytes.
153 */
154#define PMU_DMA_MIN_READ_SIZE_BYTES 16
155#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4
156
157#define PMU_FB_COPY_RW_ALIGNMENT \
158 (PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES ? \
159 PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES)
160
161/*!
162 * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned
163 * data structures to issue DMA read/write operations.
164 */
165#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \
166union name##_aligned { \
167 struct name data; \
168 u8 pad[ALIGN_UP(sizeof(struct name), \
169 (PMU_FB_COPY_RW_ALIGNMENT))]; \
170}
171
172#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \
173union name##_aligned { \
174 union name data; \
175 u8 pad[ALIGN_UP(sizeof(union name), \
176 (PMU_FB_COPY_RW_ALIGNMENT))]; \
177}
178
179#define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b)) 133#define NV_UNSIGNED_ROUNDED_DIV(a, b) (((a) + ((b) / 2)) / (b))
180 134
181#endif 135#endif
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
index ad29516a..84377d0b 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h
@@ -24,12 +24,7 @@
24#include <linux/version.h> 24#include <linux/version.h>
25#include "pmu_api.h" 25#include "pmu_api.h"
26#include "pmu_common.h" 26#include "pmu_common.h"
27#include "pmuif/gpmuifboardobj.h" 27#include "pmuif/nvgpu_gpmu_cmdif.h"
28#include "pmuif/gpmuifclk.h"
29#include "pmuif/gpmuifperf.h"
30#include "pmuif/gpmuifpmgr.h"
31#include "pmuif/gpmuifvolt.h"
32#include "pmuif/gpmuiftherm.h"
33 28
34/* defined by pmu hw spec */ 29/* defined by pmu hw spec */
35#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024) 30#define GK20A_PMU_VA_SIZE (512 * 1024 * 1024)
@@ -74,53 +69,6 @@ enum {
74 GK20A_PMU_DMAIDX_END = 7 69 GK20A_PMU_DMAIDX_END = 7
75}; 70};
76 71
77struct pmu_cmdline_args_v2 {
78 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
79 u32 falc_trace_size; /* falctrace buffer size (bytes) */
80 u32 falc_trace_dma_base; /* 256-byte block address */
81 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
82 u8 secure_mode;
83 u8 raise_priv_sec; /*Raise priv level required for desired
84 registers*/
85 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */
86};
87
88struct pmu_cmdline_args_v3 {
89 u32 reserved;
90 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
91 u32 falc_trace_size; /* falctrace buffer size (bytes) */
92 u32 falc_trace_dma_base; /* 256-byte block address */
93 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
94 u8 secure_mode;
95 u8 raise_priv_sec; /*Raise priv level required for desired
96 registers*/
97 struct pmu_mem_v1 gc6_ctx; /* dmem offset of gc6 context */
98};
99
100struct pmu_cmdline_args_v4 {
101 u32 reserved;
102 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
103 u32 falc_trace_size; /* falctrace buffer size (bytes) */
104 struct falc_dma_addr dma_addr; /* 256-byte block address */
105 u32 falc_trace_dma_idx; /* dmaIdx for DMA operations */
106 u8 secure_mode;
107 u8 raise_priv_sec; /*Raise priv level required for desired
108 registers*/
109 struct pmu_mem_desc_v0 gc6_ctx; /* dmem offset of gc6 context */
110 u8 pad;
111};
112
113struct pmu_cmdline_args_v5 {
114 u32 cpu_freq_hz; /* Frequency of the clock driving PMU */
115 struct flcn_mem_desc_v0 trace_buf;
116 u8 secure_mode;
117 u8 raise_priv_sec;
118 struct flcn_mem_desc_v0 gc6_ctx;
119 struct flcn_mem_desc_v0 init_data_dma_info;
120 u32 dummy;
121};
122
123
124#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */ 72#define GK20A_PMU_TRACE_BUFSIZE 0x4000 /* 4K */
125#define GK20A_PMU_DMEM_BLKSIZE2 8 73#define GK20A_PMU_DMEM_BLKSIZE2 8
126 74
@@ -176,29 +124,6 @@ struct pmu_ucode_desc_v1 {
176 u32 compressed; 124 u32 compressed;
177}; 125};
178 126
179#define PMU_UNIT_REWIND (0x00)
180#define PMU_UNIT_PG (0x03)
181#define PMU_UNIT_INIT (0x07)
182#define PMU_UNIT_ACR (0x0A)
183#define PMU_UNIT_PERFMON_T18X (0x11)
184#define PMU_UNIT_PERFMON (0x12)
185#define PMU_UNIT_PERF (0x13)
186#define PMU_UNIT_RC (0x1F)
187#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E)
188#define PMU_UNIT_CLK (0x0D)
189#define PMU_UNIT_THERM (0x14)
190#define PMU_UNIT_PMGR (0x18)
191#define PMU_UNIT_VOLT (0x0E)
192
193#define PMU_UNIT_END (0x23)
194
195#define PMU_UNIT_TEST_START (0xFE)
196#define PMU_UNIT_END_SIM (0xFF)
197#define PMU_UNIT_TEST_END (0xFF)
198
199#define PMU_UNIT_ID_IS_VALID(id) \
200 (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START))
201
202#define PMU_DMEM_ALLOC_ALIGNMENT (4) 127#define PMU_DMEM_ALLOC_ALIGNMENT (4)
203#define PMU_DMEM_ALIGNMENT (4) 128#define PMU_DMEM_ALIGNMENT (4)
204 129
@@ -212,124 +137,7 @@ struct pmu_ucode_desc_v1 {
212#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr) 137#define PMU_MSG_HDR_SIZE sizeof(struct pmu_hdr)
213#define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr) 138#define PMU_CMD_HDR_SIZE sizeof(struct pmu_hdr)
214 139
215#define PMU_QUEUE_COUNT 5
216
217enum {
218 PMU_INIT_MSG_TYPE_PMU_INIT = 0,
219};
220
221struct pmu_init_msg_pmu_v0 {
222 u8 msg_type;
223 u8 pad;
224
225 struct {
226 u16 size;
227 u16 offset;
228 u8 index;
229 u8 pad;
230 } queue_info[PMU_QUEUE_COUNT];
231
232 u16 sw_managed_area_offset;
233 u16 sw_managed_area_size;
234};
235
236struct pmu_init_msg_pmu_v1 {
237 u8 msg_type;
238 u8 pad;
239 u16 os_debug_entry_point;
240
241 struct {
242 u16 size;
243 u16 offset;
244 u8 index;
245 u8 pad;
246 } queue_info[PMU_QUEUE_COUNT];
247
248 u16 sw_managed_area_offset;
249 u16 sw_managed_area_size;
250};
251struct pmu_init_msg_pmu_v2 {
252 u8 msg_type;
253 u8 pad;
254 u16 os_debug_entry_point;
255
256 struct {
257 u16 size;
258 u16 offset;
259 u8 index;
260 u8 pad;
261 } queue_info[PMU_QUEUE_COUNT];
262
263 u16 sw_managed_area_offset;
264 u16 sw_managed_area_size;
265 u8 dummy[18];
266};
267
268#define PMU_QUEUE_COUNT_FOR_V4 5
269#define PMU_QUEUE_COUNT_FOR_V3 3
270#define PMU_QUEUE_HPQ_IDX_FOR_V3 0
271#define PMU_QUEUE_LPQ_IDX_FOR_V3 1
272#define PMU_QUEUE_MSG_IDX_FOR_V3 2
273struct pmu_init_msg_pmu_v3 {
274 u8 msg_type;
275 u8 queue_index[PMU_QUEUE_COUNT_FOR_V3];
276 u16 queue_size[PMU_QUEUE_COUNT_FOR_V3];
277 u16 queue_offset;
278
279 u16 sw_managed_area_offset;
280 u16 sw_managed_area_size;
281
282 u16 os_debug_entry_point;
283
284 u8 dummy[18];
285};
286
287struct pmu_init_msg_pmu_v4 {
288 u8 msg_type;
289 u8 queue_index[PMU_QUEUE_COUNT_FOR_V4];
290 u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
291 u16 queue_offset;
292
293 u16 sw_managed_area_offset;
294 u16 sw_managed_area_size;
295
296 u16 os_debug_entry_point;
297
298 u8 dummy[18];
299};
300
301union pmu_init_msg_pmu {
302 struct pmu_init_msg_pmu_v0 v0;
303 struct pmu_init_msg_pmu_v1 v1;
304 struct pmu_init_msg_pmu_v2 v2;
305 struct pmu_init_msg_pmu_v3 v3;
306 struct pmu_init_msg_pmu_v4 v4;
307};
308
309struct pmu_init_msg {
310 union {
311 u8 msg_type;
312 struct pmu_init_msg_pmu_v1 pmu_init_v1;
313 struct pmu_init_msg_pmu_v0 pmu_init_v0;
314 struct pmu_init_msg_pmu_v2 pmu_init_v2;
315 struct pmu_init_msg_pmu_v3 pmu_init_v3;
316 struct pmu_init_msg_pmu_v4 pmu_init_v4;
317 };
318};
319
320enum {
321 PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
322};
323
324struct pmu_rc_msg_unhandled_cmd {
325 u8 msg_type;
326 u8 unit_id;
327};
328 140
329struct pmu_rc_msg {
330 u8 msg_type;
331 struct pmu_rc_msg_unhandled_cmd unhandled_cmd;
332};
333 141
334/***************************** ACR ERROR CODES ******************************/ 142/***************************** ACR ERROR CODES ******************************/
335/*! 143/*!
@@ -374,120 +182,10 @@ struct pmu_perfmon_counter_v2 {
374#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004) 182#define PMU_PERFMON_FLAG_CLEAR_PREV (0x00000004)
375 183
376 184
377struct pmu_cmd {
378 struct pmu_hdr hdr;
379 union {
380 struct pmu_perfmon_cmd perfmon;
381 struct pmu_pg_cmd pg;
382 struct pmu_zbc_cmd zbc;
383 struct pmu_acr_cmd acr;
384 struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram;
385 struct nv_pmu_boardobj_cmd boardobj;
386 struct nv_pmu_perf_cmd perf;
387 struct nv_pmu_volt_cmd volt;
388 struct nv_pmu_clk_cmd clk;
389 struct nv_pmu_pmgr_cmd pmgr;
390 struct nv_pmu_therm_cmd therm;
391 } cmd;
392};
393
394struct pmu_msg {
395 struct pmu_hdr hdr;
396 union {
397 struct pmu_init_msg init;
398 struct pmu_perfmon_msg perfmon;
399 struct pmu_pg_msg pg;
400 struct pmu_rc_msg rc;
401 struct pmu_acr_msg acr;
402 struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram;
403 struct nv_pmu_boardobj_msg boardobj;
404 struct nv_pmu_perf_msg perf;
405 struct nv_pmu_volt_msg volt;
406 struct nv_pmu_clk_msg clk;
407 struct nv_pmu_pmgr_msg pmgr;
408 struct nv_pmu_therm_msg therm;
409 } msg;
410};
411
412#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2
413#define PMU_SHA1_GID_SIGNATURE_SIZE 4
414
415#define PMU_SHA1_GID_SIZE 16
416
417struct pmu_sha1_gid {
418 bool valid;
419 u8 gid[PMU_SHA1_GID_SIZE];
420};
421
422struct pmu_sha1_gid_data {
423 u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE];
424 u8 gid[PMU_SHA1_GID_SIZE];
425};
426
427#define PMU_COMMAND_QUEUE_HPQ 0 /* write by sw, read by pmu, protected by sw mutex lock */
428#define PMU_COMMAND_QUEUE_LPQ 1 /* write by sw, read by pmu, protected by sw mutex lock */
429#define PMU_COMMAND_QUEUE_BIOS 2 /* read/write by sw/hw, protected by hw pmu mutex, id = 2 */
430#define PMU_COMMAND_QUEUE_SMI 3 /* read/write by sw/hw, protected by hw pmu mutex, id = 3 */
431#define PMU_MESSAGE_QUEUE 4 /* write by pmu, read by sw, accessed by interrupt handler, no lock */
432#define PMU_QUEUE_COUNT 5
433
434enum {
435 PMU_MUTEX_ID_RSVD1 = 0 ,
436 PMU_MUTEX_ID_GPUSER ,
437 PMU_MUTEX_ID_QUEUE_BIOS ,
438 PMU_MUTEX_ID_QUEUE_SMI ,
439 PMU_MUTEX_ID_GPMUTEX ,
440 PMU_MUTEX_ID_I2C ,
441 PMU_MUTEX_ID_RMLOCK ,
442 PMU_MUTEX_ID_MSGBOX ,
443 PMU_MUTEX_ID_FIFO ,
444 PMU_MUTEX_ID_PG ,
445 PMU_MUTEX_ID_GR ,
446 PMU_MUTEX_ID_CLK ,
447 PMU_MUTEX_ID_RSVD6 ,
448 PMU_MUTEX_ID_RSVD7 ,
449 PMU_MUTEX_ID_RSVD8 ,
450 PMU_MUTEX_ID_RSVD9 ,
451 PMU_MUTEX_ID_INVALID
452};
453
454#define PMU_IS_COMMAND_QUEUE(id) \
455 ((id) < PMU_MESSAGE_QUEUE)
456
457#define PMU_IS_SW_COMMAND_QUEUE(id) \
458 (((id) == PMU_COMMAND_QUEUE_HPQ) || \
459 ((id) == PMU_COMMAND_QUEUE_LPQ))
460
461#define PMU_IS_MESSAGE_QUEUE(id) \
462 ((id) == PMU_MESSAGE_QUEUE)
463
464enum
465{
466 OFLAG_READ = 0,
467 OFLAG_WRITE
468};
469
470#define QUEUE_SET (true)
471#define QUEUE_GET (false)
472
473#define QUEUE_ALIGNMENT (4)
474
475#define PMU_PGENG_GR_BUFFER_IDX_INIT (0) 185#define PMU_PGENG_GR_BUFFER_IDX_INIT (0)
476#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1) 186#define PMU_PGENG_GR_BUFFER_IDX_ZBC (1)
477#define PMU_PGENG_GR_BUFFER_IDX_FECS (2) 187#define PMU_PGENG_GR_BUFFER_IDX_FECS (2)
478 188
479enum
480{
481 PMU_DMAIDX_UCODE = 0,
482 PMU_DMAIDX_VIRT = 1,
483 PMU_DMAIDX_PHYS_VID = 2,
484 PMU_DMAIDX_PHYS_SYS_COH = 3,
485 PMU_DMAIDX_PHYS_SYS_NCOH = 4,
486 PMU_DMAIDX_RSVD = 5,
487 PMU_DMAIDX_PELPG = 6,
488 PMU_DMAIDX_END = 7
489};
490
491struct pmu_gk20a; 189struct pmu_gk20a;
492struct pmu_queue; 190struct pmu_queue;
493 191
@@ -515,12 +213,6 @@ struct pmu_queue {
515 bool opened; /* opened implies locked */ 213 bool opened; /* opened implies locked */
516}; 214};
517 215
518
519#define PMU_MUTEX_ID_IS_VALID(id) \
520 ((id) < PMU_MUTEX_ID_INVALID)
521
522#define PMU_INVALID_MUTEX_OWNER_ID (0)
523
524struct pmu_mutex { 216struct pmu_mutex {
525 u32 id; 217 u32 id;
526 u32 index; 218 u32 index;
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h b/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h
new file mode 100644
index 00000000..1d200129
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/gpmuif_cmn.h
@@ -0,0 +1,121 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef _GPMUIFCMN_H_
14#define _GPMUIFCMN_H_
15
16/*
17 * Defines the logical queue IDs that must be used when submitting
18 * commands to the PMU
19 */
20/* write by sw, read by pmu, protected by sw mutex lock */
21#define PMU_COMMAND_QUEUE_HPQ 0
22/* write by sw, read by pmu, protected by sw mutex lock */
23#define PMU_COMMAND_QUEUE_LPQ 1
24/* read/write by sw/hw, protected by hw pmu mutex, id = 2 */
25#define PMU_COMMAND_QUEUE_BIOS 2
26/* read/write by sw/hw, protected by hw pmu mutex, id = 3 */
27#define PMU_COMMAND_QUEUE_SMI 3
28/* write by pmu, read by sw, accessed by interrupt handler, no lock */
29#define PMU_MESSAGE_QUEUE 4
30#define PMU_QUEUE_COUNT 5
31
32#define PMU_IS_COMMAND_QUEUE(id) \
33 ((id) < PMU_MESSAGE_QUEUE)
34
35#define PMU_IS_SW_COMMAND_QUEUE(id) \
36 (((id) == PMU_COMMAND_QUEUE_HPQ) || \
37 ((id) == PMU_COMMAND_QUEUE_LPQ))
38
39#define PMU_IS_MESSAGE_QUEUE(id) \
40 ((id) == PMU_MESSAGE_QUEUE)
41
42enum {
43 OFLAG_READ = 0,
44 OFLAG_WRITE
45};
46
47#define QUEUE_SET (true)
48#define QUEUE_GET (false)
49
50#define QUEUE_ALIGNMENT (4)
51
52/* An enumeration containing all valid logical mutex identifiers */
53enum {
54 PMU_MUTEX_ID_RSVD1 = 0,
55 PMU_MUTEX_ID_GPUSER,
56 PMU_MUTEX_ID_QUEUE_BIOS,
57 PMU_MUTEX_ID_QUEUE_SMI,
58 PMU_MUTEX_ID_GPMUTEX,
59 PMU_MUTEX_ID_I2C,
60 PMU_MUTEX_ID_RMLOCK,
61 PMU_MUTEX_ID_MSGBOX,
62 PMU_MUTEX_ID_FIFO,
63 PMU_MUTEX_ID_PG,
64 PMU_MUTEX_ID_GR,
65 PMU_MUTEX_ID_CLK,
66 PMU_MUTEX_ID_RSVD6,
67 PMU_MUTEX_ID_RSVD7,
68 PMU_MUTEX_ID_RSVD8,
69 PMU_MUTEX_ID_RSVD9,
70 PMU_MUTEX_ID_INVALID
71};
72
73#define PMU_MUTEX_ID_IS_VALID(id) \
74 ((id) < PMU_MUTEX_ID_INVALID)
75
76#define PMU_INVALID_MUTEX_OWNER_ID (0)
77
78/*
79 * The PMU's frame-buffer interface block has several slots/indices
80 * which can be bound to support DMA to various surfaces in memory
81 */
82enum {
83 PMU_DMAIDX_UCODE = 0,
84 PMU_DMAIDX_VIRT = 1,
85 PMU_DMAIDX_PHYS_VID = 2,
86 PMU_DMAIDX_PHYS_SYS_COH = 3,
87 PMU_DMAIDX_PHYS_SYS_NCOH = 4,
88 PMU_DMAIDX_RSVD = 5,
89 PMU_DMAIDX_PELPG = 6,
90 PMU_DMAIDX_END = 7
91};
92
93/*
94 * Falcon PMU DMA's minimum size in bytes.
95 */
96#define PMU_DMA_MIN_READ_SIZE_BYTES 16
97#define PMU_DMA_MIN_WRITE_SIZE_BYTES 4
98
99#define PMU_FB_COPY_RW_ALIGNMENT \
100 ((PMU_DMA_MIN_READ_SIZE_BYTES > PMU_DMA_MIN_WRITE_SIZE_BYTES) ? \
101 PMU_DMA_MIN_READ_SIZE_BYTES : PMU_DMA_MIN_WRITE_SIZE_BYTES)
102
103/*
104 * Macros to make aligned versions of RM_PMU_XXX structures. PMU needs aligned
105 * data structures to issue DMA read/write operations.
106 */
107#define NV_PMU_MAKE_ALIGNED_STRUCT(name, size) \
108union name##_aligned { \
109 struct name data; \
110 u8 pad[ALIGN_UP(sizeof(struct name), \
111 (PMU_FB_COPY_RW_ALIGNMENT))]; \
112}
113
114#define NV_PMU_MAKE_ALIGNED_UNION(name, size) \
115union name##_aligned { \
116 union name data; \
117 u8 pad[ALIGN_UP(sizeof(union name), \
118 (PMU_FB_COPY_RW_ALIGNMENT))]; \
119}
120
121#endif /* _GPMUIFCMN_H_*/
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h
new file mode 100644
index 00000000..f9ffb4b1
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/gpmuif_pmu.h
@@ -0,0 +1,215 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef _GPMUIFPMU_H_
14#define _GPMUIFPMU_H_
15
16#include "gk20a/pmu_common.h"
17#include "gpmuif_cmn.h"
18
19/* Make sure size of this structure is a multiple of 4 bytes */
20struct pmu_cmdline_args_v0 {
21 u32 cpu_freq_hz;
22 u32 falc_trace_size;
23 u32 falc_trace_dma_base;
24 u32 falc_trace_dma_idx;
25 struct pmu_mem_v0 gc6_ctx;
26};
27
28struct pmu_cmdline_args_v1 {
29 u32 cpu_freq_hz;
30 u32 falc_trace_size;
31 u32 falc_trace_dma_base;
32 u32 falc_trace_dma_idx;
33 u8 secure_mode;
34 struct pmu_mem_v1 gc6_ctx;
35};
36
37struct pmu_cmdline_args_v2 {
38 u32 cpu_freq_hz;
39 u32 falc_trace_size;
40 u32 falc_trace_dma_base;
41 u32 falc_trace_dma_idx;
42 u8 secure_mode;
43 u8 raise_priv_sec;
44 struct pmu_mem_v1 gc6_ctx;
45};
46
47struct pmu_cmdline_args_v3 {
48 u32 reserved;
49 u32 cpu_freq_hz;
50 u32 falc_trace_size;
51 u32 falc_trace_dma_base;
52 u32 falc_trace_dma_idx;
53 u8 secure_mode;
54 u8 raise_priv_sec;
55 struct pmu_mem_v1 gc6_ctx;
56};
57
58struct pmu_cmdline_args_v4 {
59 u32 reserved;
60 u32 cpu_freq_hz;
61 u32 falc_trace_size;
62 struct falc_dma_addr dma_addr;
63 u32 falc_trace_dma_idx;
64 u8 secure_mode;
65 u8 raise_priv_sec;
66 struct pmu_mem_desc_v0 gc6_ctx;
67 u8 pad;
68};
69
70struct pmu_cmdline_args_v5 {
71 u32 cpu_freq_hz;
72 struct flcn_mem_desc_v0 trace_buf;
73 u8 secure_mode;
74 u8 raise_priv_sec;
75 struct flcn_mem_desc_v0 gc6_ctx;
76 struct flcn_mem_desc_v0 init_data_dma_info;
77 u32 dummy;
78};
79
80/* GPU ID */
81#define PMU_SHA1_GID_SIGNATURE 0xA7C66AD2
82#define PMU_SHA1_GID_SIGNATURE_SIZE 4
83
84#define PMU_SHA1_GID_SIZE 16
85
86struct pmu_sha1_gid {
87 bool valid;
88 u8 gid[PMU_SHA1_GID_SIZE];
89};
90
91struct pmu_sha1_gid_data {
92 u8 signature[PMU_SHA1_GID_SIGNATURE_SIZE];
93 u8 gid[PMU_SHA1_GID_SIZE];
94};
95
96/* PMU INIT MSG */
97enum {
98 PMU_INIT_MSG_TYPE_PMU_INIT = 0,
99};
100
101struct pmu_init_msg_pmu_v0 {
102 u8 msg_type;
103 u8 pad;
104
105 struct {
106 u16 size;
107 u16 offset;
108 u8 index;
109 u8 pad;
110 } queue_info[PMU_QUEUE_COUNT];
111
112 u16 sw_managed_area_offset;
113 u16 sw_managed_area_size;
114};
115
116struct pmu_init_msg_pmu_v1 {
117 u8 msg_type;
118 u8 pad;
119 u16 os_debug_entry_point;
120
121 struct {
122 u16 size;
123 u16 offset;
124 u8 index;
125 u8 pad;
126 } queue_info[PMU_QUEUE_COUNT];
127
128 u16 sw_managed_area_offset;
129 u16 sw_managed_area_size;
130};
131struct pmu_init_msg_pmu_v2 {
132 u8 msg_type;
133 u8 pad;
134 u16 os_debug_entry_point;
135
136 struct {
137 u16 size;
138 u16 offset;
139 u8 index;
140 u8 pad;
141 } queue_info[PMU_QUEUE_COUNT];
142
143 u16 sw_managed_area_offset;
144 u16 sw_managed_area_size;
145 u8 dummy[18];
146};
147
148#define PMU_QUEUE_COUNT_FOR_V4 5
149#define PMU_QUEUE_COUNT_FOR_V3 3
150#define PMU_QUEUE_HPQ_IDX_FOR_V3 0
151#define PMU_QUEUE_LPQ_IDX_FOR_V3 1
152#define PMU_QUEUE_MSG_IDX_FOR_V3 2
153struct pmu_init_msg_pmu_v3 {
154 u8 msg_type;
155 u8 queue_index[PMU_QUEUE_COUNT_FOR_V3];
156 u16 queue_size[PMU_QUEUE_COUNT_FOR_V3];
157 u16 queue_offset;
158
159 u16 sw_managed_area_offset;
160 u16 sw_managed_area_size;
161
162 u16 os_debug_entry_point;
163
164 u8 dummy[18];
165};
166
167struct pmu_init_msg_pmu_v4 {
168 u8 msg_type;
169 u8 queue_index[PMU_QUEUE_COUNT_FOR_V4];
170 u16 queue_size[PMU_QUEUE_COUNT_FOR_V4];
171 u16 queue_offset;
172
173 u16 sw_managed_area_offset;
174 u16 sw_managed_area_size;
175
176 u16 os_debug_entry_point;
177
178 u8 dummy[18];
179};
180
181union pmu_init_msg_pmu {
182 struct pmu_init_msg_pmu_v0 v0;
183 struct pmu_init_msg_pmu_v1 v1;
184 struct pmu_init_msg_pmu_v2 v2;
185 struct pmu_init_msg_pmu_v3 v3;
186 struct pmu_init_msg_pmu_v4 v4;
187};
188
189struct pmu_init_msg {
190 union {
191 u8 msg_type;
192 struct pmu_init_msg_pmu_v1 pmu_init_v1;
193 struct pmu_init_msg_pmu_v0 pmu_init_v0;
194 struct pmu_init_msg_pmu_v2 pmu_init_v2;
195 struct pmu_init_msg_pmu_v3 pmu_init_v3;
196 struct pmu_init_msg_pmu_v4 pmu_init_v4;
197 };
198};
199
200/* robust channel (RC) messages */
201enum {
202 PMU_RC_MSG_TYPE_UNHANDLED_CMD = 0,
203};
204
205struct pmu_rc_msg_unhandled_cmd {
206 u8 msg_type;
207 u8 unit_id;
208};
209
210struct pmu_rc_msg {
211 u8 msg_type;
212 struct pmu_rc_msg_unhandled_cmd unhandled_cmd;
213};
214
215#endif /* _GPMUIFPMU_H_*/
diff --git a/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
new file mode 100644
index 00000000..b21b3981
--- /dev/null
+++ b/drivers/gpu/nvgpu/pmuif/nvgpu_gpmu_cmdif.h
@@ -0,0 +1,85 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13#ifndef _NVGPUGPMUCMDIF_H_
14#define _NVGPUGPMUCMDIF_H_
15
16#include "gk20a/pmu_api.h"
17#include "gk20a/pmu_common.h"
18#include "gpmuif_cmn.h"
19#include "gpmuif_pmu.h"
20#include "gpmuifboardobj.h"
21#include "gpmuifclk.h"
22#include "gpmuifperf.h"
23#include "gpmuifpmgr.h"
24#include "gpmuifvolt.h"
25#include "gpmuiftherm.h"
26
27struct pmu_cmd {
28 struct pmu_hdr hdr;
29 union {
30 struct pmu_perfmon_cmd perfmon;
31 struct pmu_pg_cmd pg;
32 struct pmu_zbc_cmd zbc;
33 struct pmu_acr_cmd acr;
34 struct pmu_lrf_tex_ltc_dram_cmd lrf_tex_ltc_dram;
35 struct nv_pmu_boardobj_cmd boardobj;
36 struct nv_pmu_perf_cmd perf;
37 struct nv_pmu_volt_cmd volt;
38 struct nv_pmu_clk_cmd clk;
39 struct nv_pmu_pmgr_cmd pmgr;
40 struct nv_pmu_therm_cmd therm;
41 } cmd;
42};
43
44struct pmu_msg {
45 struct pmu_hdr hdr;
46 union {
47 struct pmu_init_msg init;
48 struct pmu_perfmon_msg perfmon;
49 struct pmu_pg_msg pg;
50 struct pmu_rc_msg rc;
51 struct pmu_acr_msg acr;
52 struct pmu_lrf_tex_ltc_dram_msg lrf_tex_ltc_dram;
53 struct nv_pmu_boardobj_msg boardobj;
54 struct nv_pmu_perf_msg perf;
55 struct nv_pmu_volt_msg volt;
56 struct nv_pmu_clk_msg clk;
57 struct nv_pmu_pmgr_msg pmgr;
58 struct nv_pmu_therm_msg therm;
59 } msg;
60};
61
62#define PMU_UNIT_REWIND (0x00)
63#define PMU_UNIT_PG (0x03)
64#define PMU_UNIT_INIT (0x07)
65#define PMU_UNIT_ACR (0x0A)
66#define PMU_UNIT_PERFMON_T18X (0x11)
67#define PMU_UNIT_PERFMON (0x12)
68#define PMU_UNIT_PERF (0x13)
69#define PMU_UNIT_RC (0x1F)
70#define PMU_UNIT_FECS_MEM_OVERRIDE (0x1E)
71#define PMU_UNIT_CLK (0x0D)
72#define PMU_UNIT_THERM (0x14)
73#define PMU_UNIT_PMGR (0x18)
74#define PMU_UNIT_VOLT (0x0E)
75
76#define PMU_UNIT_END (0x23)
77
78#define PMU_UNIT_TEST_START (0xFE)
79#define PMU_UNIT_END_SIM (0xFF)
80#define PMU_UNIT_TEST_END (0xFF)
81
82#define PMU_UNIT_ID_IS_VALID(id) \
83 (((id) < PMU_UNIT_END) || ((id) >= PMU_UNIT_TEST_START))
84
85#endif /* _NVGPUGPMUCMDIF_H_*/
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-05 00:33:35 -0400