diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2017-05-24 15:06:39 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-05-29 16:33:37 -0400 |
commit | 0181a4e60248c2e3fbb46aa3a33c6154df8b5c5f (patch) | |
tree | 5bcde9ccda08409d54f8fa7cf1cd3334f48c6c76 /drivers | |
parent | da02ea50f0704ad0836177c315c9ff87288f0969 (diff) |
gpu: nvgpu: gv11b: Update nvlink soc cedits
This temp fix will be modified to call proper
nvlink module API, once it is available.
Change-Id: Id6e9651452a7d7072c285ab00330c85928cdf4d6
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/1489068
GVS: Gerrit_Virtual_Submit
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fb_gv11b.c | 43 |
1 files changed, 31 insertions, 12 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c index c3524953..7bf7139e 100644 --- a/drivers/gpu/nvgpu/gv11b/fb_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fb_gv11b.c | |||
@@ -31,21 +31,40 @@ | |||
31 | 31 | ||
32 | static void gv11b_init_nvlink_soc_credits(struct gk20a *g) | 32 | static void gv11b_init_nvlink_soc_credits(struct gk20a *g) |
33 | { | 33 | { |
34 | void __iomem *soc1 = ioremap(0x02b10010, 4096); | 34 | void __iomem *soc0 = ioremap(0x01f00010, 4096); //MSS_NVLINK_0_BASE |
35 | void __iomem *soc2 = ioremap(0x02b20010, 4096); | 35 | void __iomem *soc1 = ioremap(0x01f20010, 4096); //MSS_NVLINK_1_BASE |
36 | void __iomem *soc3 = ioremap(0x02b30010, 4096); | 36 | void __iomem *soc2 = ioremap(0x01f40010, 4096); //MSS_NVLINK_2_BASE |
37 | void __iomem *soc4 = ioremap(0x02b40010, 4096); | 37 | void __iomem *soc3 = ioremap(0x01f60010, 4096); //MSS_NVLINK_3_BASE |
38 | void __iomem *soc4 = ioremap(0x01f80010, 4096); //MSS_NVLINK_4_BASE | ||
39 | u32 val; | ||
38 | 40 | ||
41 | /* TODO : replace this code with proper nvlink API */ | ||
39 | nvgpu_info(g, "init nvlink soc credits"); | 42 | nvgpu_info(g, "init nvlink soc credits"); |
40 | 43 | ||
41 | writel_relaxed(0x14050000, soc1); | 44 | val = readl_relaxed(soc0); |
42 | writel_relaxed(0x08020000, soc1 + 4); | 45 | writel_relaxed(val, soc0); |
43 | writel_relaxed(0x14050000, soc2); | 46 | val = readl_relaxed(soc0 + 4); |
44 | writel_relaxed(0x08020000, soc2 + 4); | 47 | writel_relaxed(val, soc0 + 4); |
45 | writel_relaxed(0x14050000, soc3); | 48 | |
46 | writel_relaxed(0x08020000, soc3 + 4); | 49 | val = readl_relaxed(soc1); |
47 | writel_relaxed(0x14050000, soc4); | 50 | writel_relaxed(val, soc1); |
48 | writel_relaxed(0x08020000, soc4 + 4); | 51 | val = readl_relaxed(soc1 + 4); |
52 | writel_relaxed(val, soc1 + 4); | ||
53 | |||
54 | val = readl_relaxed(soc2); | ||
55 | writel_relaxed(val, soc2); | ||
56 | val = readl_relaxed(soc2 + 4); | ||
57 | writel_relaxed(val, soc2 + 4); | ||
58 | |||
59 | val = readl_relaxed(soc3); | ||
60 | writel_relaxed(val, soc3); | ||
61 | val = readl_relaxed(soc3 + 4); | ||
62 | writel_relaxed(val, soc3 + 4); | ||
63 | |||
64 | val = readl_relaxed(soc4); | ||
65 | writel_relaxed(val, soc4); | ||
66 | val = readl_relaxed(soc4 + 4); | ||
67 | writel_relaxed(val, soc4 + 4); | ||
49 | 68 | ||
50 | } | 69 | } |
51 | 70 | ||