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authorTerje Bergstrom <tbergstrom@nvidia.com>2018-09-12 17:51:40 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-27 18:05:34 -0400
commitf89ea110417e1c83cf21f495d6da7cdc8138a29f (patch)
tree198f25d08d650e5a42470eb1823b441c07d8b71f /drivers/gpu
parente3ae03e17abd452c157545234348692364b4b9f6 (diff)
gpu: nvgpu: Move FB reset to MC unit
FB reset is done by accessing MC register. Move the code to MC unit. JIRA NVGPU-954 Change-Id: I1636887af805f016da5490af65e808f9ac015cde Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1823385 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gm20b.c14
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gm20b.h1
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gp106.c2
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gp106.h2
-rw-r--r--drivers/gpu/nvgpu/common/fb/fb_gv11b.c7
-rw-r--r--drivers/gpu/nvgpu/common/mm/mm.c4
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c2
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c4
-rw-r--r--drivers/gpu/nvgpu/gp10b/hal_gp10b.c2
-rw-r--r--drivers/gpu/nvgpu/gv100/hal_gv100.c5
-rw-r--r--drivers/gpu/nvgpu/gv11b/hal_gv11b.c2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/gk20a.h2
-rw-r--r--drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c1
-rw-r--r--drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c1
14 files changed, 15 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c
index 9a13ecca..bf509caf 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.c
@@ -33,25 +33,11 @@
33#include <nvgpu/io.h> 33#include <nvgpu/io.h>
34#include <nvgpu/timers.h> 34#include <nvgpu/timers.h>
35 35
36#include <nvgpu/hw/gm20b/hw_mc_gm20b.h>
37#include <nvgpu/hw/gm20b/hw_fb_gm20b.h> 36#include <nvgpu/hw/gm20b/hw_fb_gm20b.h>
38 37
39#define VPR_INFO_FETCH_WAIT (5) 38#define VPR_INFO_FETCH_WAIT (5)
40#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c 39#define WPR_INFO_ADDR_ALIGNMENT 0x0000000c
41 40
42void gm20b_fb_reset(struct gk20a *g)
43{
44 u32 val;
45
46 nvgpu_log_info(g, "reset gk20a fb");
47
48 val = gk20a_readl(g, mc_elpg_enable_r());
49 val |= mc_elpg_enable_xbar_enabled_f()
50 | mc_elpg_enable_pfb_enabled_f()
51 | mc_elpg_enable_hub_enabled_f();
52 gk20a_writel(g, mc_elpg_enable_r(), val);
53}
54
55void gm20b_fb_init_hw(struct gk20a *g) 41void gm20b_fb_init_hw(struct gk20a *g)
56{ 42{
57 u64 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8; 43 u64 addr = nvgpu_mem_get_addr(g, &g->mm.sysmem_flush) >> 8;
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h
index bc240ae3..cb5b5d9a 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gm20b.h
+++ b/drivers/gpu/nvgpu/common/fb/fb_gm20b.h
@@ -31,7 +31,6 @@ struct gk20a;
31struct wpr_carveout_info; 31struct wpr_carveout_info;
32struct nvgpu_mem; 32struct nvgpu_mem;
33 33
34void gm20b_fb_reset(struct gk20a *g);
35void gm20b_fb_init_hw(struct gk20a *g); 34void gm20b_fb_init_hw(struct gk20a *g);
36int gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb); 35int gm20b_fb_tlb_invalidate(struct gk20a *g, struct nvgpu_mem *pdb);
37void fb_gm20b_init_fs_state(struct gk20a *g); 36void fb_gm20b_init_fs_state(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gp106.c b/drivers/gpu/nvgpu/common/fb/fb_gp106.c
index 27fce8a7..567749c9 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gp106.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gp106.c
@@ -32,7 +32,7 @@
32#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */ 32#define HW_SCRUB_TIMEOUT_DEFAULT 100 /* usec */
33#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */ 33#define HW_SCRUB_TIMEOUT_MAX 2000000 /* usec */
34 34
35void gp106_fb_reset(struct gk20a *g) 35void gp106_fb_init_fs_state(struct gk20a *g)
36{ 36{
37 u32 val; 37 u32 val;
38 38
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gp106.h b/drivers/gpu/nvgpu/common/fb/fb_gp106.h
index bb4ccd6b..25f5fce2 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gp106.h
+++ b/drivers/gpu/nvgpu/common/fb/fb_gp106.h
@@ -24,7 +24,7 @@
24#define FB_GP106_H 24#define FB_GP106_H
25struct gpu_ops; 25struct gpu_ops;
26 26
27void gp106_fb_reset(struct gk20a *g); 27void gp106_fb_init_fs_state(struct gk20a *g);
28size_t gp106_fb_get_vidmem_size(struct gk20a *g); 28size_t gp106_fb_get_vidmem_size(struct gk20a *g);
29 29
30#endif 30#endif
diff --git a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
index 75968ba6..30bf17f8 100644
--- a/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
+++ b/drivers/gpu/nvgpu/common/fb/fb_gv11b.c
@@ -73,6 +73,8 @@ void gv11b_fb_init_fs_state(struct gk20a *g)
73{ 73{
74 nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb"); 74 nvgpu_log(g, gpu_dbg_fn, "initialize gv11b fb");
75 75
76 gv11b_init_nvlink_soc_credits(g);
77
76 nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x", 78 nvgpu_log(g, gpu_dbg_info, "fbhub active ltcs %x",
77 gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); 79 gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
78 80
@@ -143,11 +145,6 @@ void gv11b_fb_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
143 145
144} 146}
145 147
146void gv11b_fb_reset(struct gk20a *g)
147{
148 gv11b_init_nvlink_soc_credits(g);
149}
150
151static const char * const invalid_str = "invalid"; 148static const char * const invalid_str = "invalid";
152 149
153static const char *const fault_type_descs_gv11b[] = { 150static const char *const fault_type_descs_gv11b[] = {
diff --git a/drivers/gpu/nvgpu/common/mm/mm.c b/drivers/gpu/nvgpu/common/mm/mm.c
index 58a435c0..c9aac4af 100644
--- a/drivers/gpu/nvgpu/common/mm/mm.c
+++ b/drivers/gpu/nvgpu/common/mm/mm.c
@@ -345,8 +345,8 @@ void nvgpu_init_mm_ce_context(struct gk20a *g)
345 345
346static int nvgpu_init_mm_reset_enable_hw(struct gk20a *g) 346static int nvgpu_init_mm_reset_enable_hw(struct gk20a *g)
347{ 347{
348 if (g->ops.fb.reset) { 348 if (g->ops.mc.fb_reset) {
349 g->ops.fb.reset(g); 349 g->ops.mc.fb_reset(g);
350 } 350 }
351 351
352 if (g->ops.clock_gating.slcg_fb_load_gating_prod) { 352 if (g->ops.clock_gating.slcg_fb_load_gating_prod) {
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 1037b11b..e4f1984a 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -330,7 +330,6 @@ static const struct gpu_ops gm20b_ops = {
330 .set_debug_mode = gm20b_gr_set_debug_mode, 330 .set_debug_mode = gm20b_gr_set_debug_mode,
331 }, 331 },
332 .fb = { 332 .fb = {
333 .reset = gm20b_fb_reset,
334 .init_hw = gm20b_fb_init_hw, 333 .init_hw = gm20b_fb_init_hw,
335 .init_fs_state = fb_gm20b_init_fs_state, 334 .init_fs_state = fb_gm20b_init_fs_state,
336 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 335 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
@@ -594,6 +593,7 @@ static const struct gpu_ops gm20b_ops = {
594 .log_pending_intrs = gm20b_mc_log_pending_intrs, 593 .log_pending_intrs = gm20b_mc_log_pending_intrs,
595 .reset_mask = gm20b_mc_reset_mask, 594 .reset_mask = gm20b_mc_reset_mask,
596 .is_enabled = gm20b_mc_is_enabled, 595 .is_enabled = gm20b_mc_is_enabled,
596 .fb_reset = gm20b_mc_fb_reset,
597 }, 597 },
598 .debug = { 598 .debug = {
599 .show_dump = gk20a_debug_show_dump, 599 .show_dump = gk20a_debug_show_dump,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 23a2177c..37d0e91e 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -406,9 +406,8 @@ static const struct gpu_ops gp106_ops = {
406 .set_debug_mode = gm20b_gr_set_debug_mode, 406 .set_debug_mode = gm20b_gr_set_debug_mode,
407 }, 407 },
408 .fb = { 408 .fb = {
409 .reset = gp106_fb_reset,
410 .init_hw = gm20b_fb_init_hw, 409 .init_hw = gm20b_fb_init_hw,
411 .init_fs_state = NULL, 410 .init_fs_state = gp106_fb_init_fs_state,
412 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 411 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
413 .set_use_full_comp_tag_line = 412 .set_use_full_comp_tag_line =
414 gm20b_fb_set_use_full_comp_tag_line, 413 gm20b_fb_set_use_full_comp_tag_line,
@@ -722,6 +721,7 @@ static const struct gpu_ops gp106_ops = {
722 .log_pending_intrs = mc_gp10b_log_pending_intrs, 721 .log_pending_intrs = mc_gp10b_log_pending_intrs,
723 .reset_mask = gm20b_mc_reset_mask, 722 .reset_mask = gm20b_mc_reset_mask,
724 .is_enabled = gm20b_mc_is_enabled, 723 .is_enabled = gm20b_mc_is_enabled,
724 .fb_reset = NULL,
725 }, 725 },
726 .debug = { 726 .debug = {
727 .show_dump = gk20a_debug_show_dump, 727 .show_dump = gk20a_debug_show_dump,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 0a285a95..b7ad9743 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -367,7 +367,6 @@ static const struct gpu_ops gp10b_ops = {
367 .set_debug_mode = gm20b_gr_set_debug_mode, 367 .set_debug_mode = gm20b_gr_set_debug_mode,
368 }, 368 },
369 .fb = { 369 .fb = {
370 .reset = gm20b_fb_reset,
371 .init_hw = gm20b_fb_init_hw, 370 .init_hw = gm20b_fb_init_hw,
372 .init_fs_state = fb_gm20b_init_fs_state, 371 .init_fs_state = fb_gm20b_init_fs_state,
373 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 372 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
@@ -656,6 +655,7 @@ static const struct gpu_ops gp10b_ops = {
656 .log_pending_intrs = mc_gp10b_log_pending_intrs, 655 .log_pending_intrs = mc_gp10b_log_pending_intrs,
657 .reset_mask = gm20b_mc_reset_mask, 656 .reset_mask = gm20b_mc_reset_mask,
658 .is_enabled = gm20b_mc_is_enabled, 657 .is_enabled = gm20b_mc_is_enabled,
658 .fb_reset = gm20b_mc_fb_reset,
659 }, 659 },
660 .debug = { 660 .debug = {
661 .show_dump = gk20a_debug_show_dump, 661 .show_dump = gk20a_debug_show_dump,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index aae2bf73..4f50b13f 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -31,6 +31,7 @@
31#include "common/ptimer/ptimer_gk20a.h" 31#include "common/ptimer/ptimer_gk20a.h"
32#include "common/fb/fb_gm20b.h" 32#include "common/fb/fb_gm20b.h"
33#include "common/fb/fb_gp10b.h" 33#include "common/fb/fb_gp10b.h"
34#include "common/fb/fb_gp106.h"
34#include "common/fb/fb_gv11b.h" 35#include "common/fb/fb_gv11b.h"
35#include "common/fb/fb_gv100.h" 36#include "common/fb/fb_gv100.h"
36#include "common/xve/xve_gp106.h" 37#include "common/xve/xve_gp106.h"
@@ -467,9 +468,8 @@ static const struct gpu_ops gv100_ops = {
467 .set_debug_mode = gm20b_gr_set_debug_mode, 468 .set_debug_mode = gm20b_gr_set_debug_mode,
468 }, 469 },
469 .fb = { 470 .fb = {
470 .reset = gv100_fb_reset,
471 .init_hw = gv11b_fb_init_hw, 471 .init_hw = gv11b_fb_init_hw,
472 .init_fs_state = NULL, 472 .init_fs_state = gp106_fb_init_fs_state,
473 .set_mmu_page_size = gm20b_fb_set_mmu_page_size, 473 .set_mmu_page_size = gm20b_fb_set_mmu_page_size,
474 .set_use_full_comp_tag_line = 474 .set_use_full_comp_tag_line =
475 gm20b_fb_set_use_full_comp_tag_line, 475 gm20b_fb_set_use_full_comp_tag_line,
@@ -819,6 +819,7 @@ static const struct gpu_ops gv100_ops = {
819 gv100_mc_is_stall_and_eng_intr_pending, 819 gv100_mc_is_stall_and_eng_intr_pending,
820 .reset_mask = gv100_mc_reset_mask, 820 .reset_mask = gv100_mc_reset_mask,
821 .is_enabled = gm20b_mc_is_enabled, 821 .is_enabled = gm20b_mc_is_enabled,
822 .fb_reset = NULL,
822 }, 823 },
823 .debug = { 824 .debug = {
824 .show_dump = gk20a_debug_show_dump, 825 .show_dump = gk20a_debug_show_dump,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 42969805..6a2dae77 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -430,7 +430,6 @@ static const struct gpu_ops gv11b_ops = {
430 .set_debug_mode = gm20b_gr_set_debug_mode, 430 .set_debug_mode = gm20b_gr_set_debug_mode,
431 }, 431 },
432 .fb = { 432 .fb = {
433 .reset = gv11b_fb_reset,
434 .init_hw = gv11b_fb_init_hw, 433 .init_hw = gv11b_fb_init_hw,
435 .init_fs_state = gv11b_fb_init_fs_state, 434 .init_fs_state = gv11b_fb_init_fs_state,
436 .init_cbc = gv11b_fb_init_cbc, 435 .init_cbc = gv11b_fb_init_cbc,
@@ -761,6 +760,7 @@ static const struct gpu_ops gv11b_ops = {
761 gv11b_mc_is_stall_and_eng_intr_pending, 760 gv11b_mc_is_stall_and_eng_intr_pending,
762 .reset_mask = gm20b_mc_reset_mask, 761 .reset_mask = gm20b_mc_reset_mask,
763 .is_enabled = gm20b_mc_is_enabled, 762 .is_enabled = gm20b_mc_is_enabled,
763 .fb_reset = NULL,
764 }, 764 },
765 .debug = { 765 .debug = {
766 .show_dump = gk20a_debug_show_dump, 766 .show_dump = gk20a_debug_show_dump,
diff --git a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
index 5a9c56e0..104d463b 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/gk20a.h
@@ -521,7 +521,6 @@ struct gpu_ops {
521 void (*init_hw)(struct gk20a *g); 521 void (*init_hw)(struct gk20a *g);
522 void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr); 522 void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
523 void (*init_fs_state)(struct gk20a *g); 523 void (*init_fs_state)(struct gk20a *g);
524 void (*reset)(struct gk20a *g);
525 void (*init_uncompressed_kind_map)(struct gk20a *g); 524 void (*init_uncompressed_kind_map)(struct gk20a *g);
526 void (*init_kind_attr)(struct gk20a *g); 525 void (*init_kind_attr)(struct gk20a *g);
527 void (*set_mmu_page_size)(struct gk20a *g); 526 void (*set_mmu_page_size)(struct gk20a *g);
@@ -1177,6 +1176,7 @@ struct gpu_ops {
1177 void (*log_pending_intrs)(struct gk20a *g); 1176 void (*log_pending_intrs)(struct gk20a *g);
1178 void (*fbpa_isr)(struct gk20a *g); 1177 void (*fbpa_isr)(struct gk20a *g);
1179 u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit); 1178 u32 (*reset_mask)(struct gk20a *g, enum nvgpu_unit unit);
1179 void (*fb_reset)(struct gk20a *g);
1180 } mc; 1180 } mc;
1181 struct { 1181 struct {
1182 void (*show_dump)(struct gk20a *g, 1182 void (*show_dump)(struct gk20a *g,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 61ab3b1b..e23595a0 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -236,7 +236,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
236 .set_debug_mode = gm20b_gr_set_debug_mode, 236 .set_debug_mode = gm20b_gr_set_debug_mode,
237 }, 237 },
238 .fb = { 238 .fb = {
239 .reset = NULL,
240 .init_hw = NULL, 239 .init_hw = NULL,
241 .init_fs_state = NULL, 240 .init_fs_state = NULL,
242 .set_mmu_page_size = NULL, 241 .set_mmu_page_size = NULL,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index a024a0ea..497c904b 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -276,7 +276,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
276 .set_debug_mode = gm20b_gr_set_debug_mode, 276 .set_debug_mode = gm20b_gr_set_debug_mode,
277 }, 277 },
278 .fb = { 278 .fb = {
279 .reset = NULL,
280 .init_hw = NULL, 279 .init_hw = NULL,
281 .init_fs_state = NULL, 280 .init_fs_state = NULL,
282 .init_cbc = NULL, 281 .init_cbc = NULL,