diff options
author | David Nieto <dmartineznie@nvidia.com> | 2017-10-12 14:35:32 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-17 02:34:04 -0400 |
commit | e78cd6c42aec3ae18f12420fd8eb4cb58d09da2d (patch) | |
tree | b40f87a48237a94dd03c65195671bb9d5de40130 /drivers/gpu | |
parent | 0c40a3e034cd9450859dfe713c4d1ca134b77b7e (diff) |
gpu: nvgpu: add missing hal defines
Due to lack of GVS coverage some defines were left out in GV100, this change
adds them back
JIRA: NVGPUGV100-9
Change-Id: I2f5778529dcad535bb56c33c38c097415dbf11e5
Signed-off-by: David Nieto <dmartineznie@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1577998
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Nirav Patel <nipatel@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 36 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | 28 |
2 files changed, 59 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 7f7ab785..7457c185 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -91,6 +91,8 @@ | |||
91 | #include "gv100/fb_gv100.h" | 91 | #include "gv100/fb_gv100.h" |
92 | #include "gv100/fifo_gv100.h" | 92 | #include "gv100/fifo_gv100.h" |
93 | #include "gv11b/fifo_gv11b.h" | 93 | #include "gv11b/fifo_gv11b.h" |
94 | #include "gv11b/regops_gv11b.h" | ||
95 | |||
94 | #include "gv11b/gv11b_gating_reglist.h" | 96 | #include "gv11b/gv11b_gating_reglist.h" |
95 | #include "gv11b/regops_gv11b.h" | 97 | #include "gv11b/regops_gv11b.h" |
96 | #include "gv11b/subctx_gv11b.h" | 98 | #include "gv11b/subctx_gv11b.h" |
@@ -100,6 +102,7 @@ | |||
100 | #include "gv100/fb_gv100.h" | 102 | #include "gv100/fb_gv100.h" |
101 | #include "gv100/mm_gv100.h" | 103 | #include "gv100/mm_gv100.h" |
102 | 104 | ||
105 | #include <nvgpu/bus.h> | ||
103 | #include <nvgpu/debug.h> | 106 | #include <nvgpu/debug.h> |
104 | #include <nvgpu/enabled.h> | 107 | #include <nvgpu/enabled.h> |
105 | 108 | ||
@@ -156,6 +159,9 @@ static int gv100_get_litter_value(struct gk20a *g, int value) | |||
156 | case GPU_LIT_PPC_IN_GPC_STRIDE: | 159 | case GPU_LIT_PPC_IN_GPC_STRIDE: |
157 | ret = proj_ppc_in_gpc_stride_v(); | 160 | ret = proj_ppc_in_gpc_stride_v(); |
158 | break; | 161 | break; |
162 | case GPU_LIT_PPC_IN_GPC_SHARED_BASE: | ||
163 | ret = proj_ppc_in_gpc_shared_base_v(); | ||
164 | break; | ||
159 | case GPU_LIT_ROP_BASE: | 165 | case GPU_LIT_ROP_BASE: |
160 | ret = proj_rop_base_v(); | 166 | ret = proj_rop_base_v(); |
161 | break; | 167 | break; |
@@ -180,13 +186,30 @@ static int gv100_get_litter_value(struct gk20a *g, int value) | |||
180 | case GPU_LIT_NUM_FBPAS: | 186 | case GPU_LIT_NUM_FBPAS: |
181 | ret = proj_scal_litter_num_fbpas_v(); | 187 | ret = proj_scal_litter_num_fbpas_v(); |
182 | break; | 188 | break; |
189 | case GPU_LIT_FBPA_SHARED_BASE: | ||
190 | ret = proj_fbpa_shared_base_v(); | ||
191 | break; | ||
192 | case GPU_LIT_FBPA_BASE: | ||
193 | ret = proj_fbpa_base_v(); | ||
194 | break; | ||
183 | case GPU_LIT_FBPA_STRIDE: | 195 | case GPU_LIT_FBPA_STRIDE: |
184 | ret = proj_fbpa_stride_v(); | 196 | ret = proj_fbpa_stride_v(); |
185 | break; | 197 | break; |
186 | case GPU_LIT_SM_PRI_STRIDE: | 198 | case GPU_LIT_SM_PRI_STRIDE: |
187 | ret = proj_sm_stride_v(); | 199 | ret = proj_sm_stride_v(); |
188 | break; | 200 | break; |
189 | 201 | case GPU_LIT_SMPC_PRI_BASE: | |
202 | ret = proj_smpc_base_v(); | ||
203 | break; | ||
204 | case GPU_LIT_SMPC_PRI_SHARED_BASE: | ||
205 | ret = proj_smpc_shared_base_v(); | ||
206 | break; | ||
207 | case GPU_LIT_SMPC_PRI_UNIQUE_BASE: | ||
208 | ret = proj_smpc_unique_base_v(); | ||
209 | break; | ||
210 | case GPU_LIT_SMPC_PRI_STRIDE: | ||
211 | ret = proj_smpc_stride_v(); | ||
212 | break; | ||
190 | default: | 213 | default: |
191 | break; | 214 | break; |
192 | } | 215 | } |
@@ -553,12 +576,10 @@ static const struct gpu_ops gv100_ops = { | |||
553 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, | 576 | .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v, |
554 | .pmu_pg_init_param = gp106_pg_param_init, | 577 | .pmu_pg_init_param = gp106_pg_param_init, |
555 | .reset_engine = gp106_pmu_engine_reset, | 578 | .reset_engine = gp106_pmu_engine_reset, |
556 | .pmu_lpwr_disable_pg = nvgpu_lpwr_disable_pg, | ||
557 | .write_dmatrfbase = gp10b_write_dmatrfbase, | 579 | .write_dmatrfbase = gp10b_write_dmatrfbase, |
558 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, | 580 | .pmu_mutex_size = pwr_pmu_mutex__size_1_v, |
559 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, | 581 | .is_engine_in_reset = gp106_pmu_is_engine_in_reset, |
560 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, | 582 | .pmu_get_queue_tail = pwr_pmu_queue_tail_r, |
561 | .pmu_lpwr_enable_pg = nvgpu_lpwr_enable_pg, | ||
562 | }, | 583 | }, |
563 | .clk = { | 584 | .clk = { |
564 | .init_clk_support = gp106_init_clk_support, | 585 | .init_clk_support = gp106_init_clk_support, |
@@ -572,6 +593,9 @@ static const struct gpu_ops gv100_ops = { | |||
572 | .get_arbiter_clk_default = gp106_get_arbiter_clk_default, | 593 | .get_arbiter_clk_default = gp106_get_arbiter_clk_default, |
573 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | 594 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, |
574 | }, | 595 | }, |
596 | .regops = { | ||
597 | .apply_smpc_war = gv11b_apply_smpc_war, | ||
598 | }, | ||
575 | .mc = { | 599 | .mc = { |
576 | .intr_enable = mc_gv11b_intr_enable, | 600 | .intr_enable = mc_gv11b_intr_enable, |
577 | .intr_unit_config = mc_gp10b_intr_unit_config, | 601 | .intr_unit_config = mc_gp10b_intr_unit_config, |
@@ -601,13 +625,14 @@ static const struct gpu_ops gv100_ops = { | |||
601 | nvgpu_check_and_set_context_reservation, | 625 | nvgpu_check_and_set_context_reservation, |
602 | .release_profiler_reservation = | 626 | .release_profiler_reservation = |
603 | nvgpu_release_profiler_reservation, | 627 | nvgpu_release_profiler_reservation, |
604 | .perfbuffer_enable = gk20a_perfbuf_enable_locked, | 628 | .perfbuffer_enable = NULL, |
605 | .perfbuffer_disable = gk20a_perfbuf_disable_locked, | 629 | .perfbuffer_disable = NULL, |
606 | }, | 630 | }, |
607 | .bus = { | 631 | .bus = { |
608 | .init_hw = gk20a_bus_init_hw, | 632 | .init_hw = gk20a_bus_init_hw, |
609 | .isr = gk20a_bus_isr, | 633 | .isr = gk20a_bus_isr, |
610 | .read_ptimer = gk20a_read_ptimer, | 634 | .read_ptimer = gk20a_read_ptimer, |
635 | .get_timestamps_zipper = nvgpu_get_timestamps_zipper, | ||
611 | .bar1_bind = NULL, | 636 | .bar1_bind = NULL, |
612 | }, | 637 | }, |
613 | #if defined(CONFIG_GK20A_CYCLE_STATS) | 638 | #if defined(CONFIG_GK20A_CYCLE_STATS) |
@@ -662,6 +687,7 @@ int gv100_init_hal(struct gk20a *g) | |||
662 | gops->pramin = gv100_ops.pramin; | 687 | gops->pramin = gv100_ops.pramin; |
663 | gops->therm = gv100_ops.therm; | 688 | gops->therm = gv100_ops.therm; |
664 | gops->pmu = gv100_ops.pmu; | 689 | gops->pmu = gv100_ops.pmu; |
690 | gops->regops = gv100_ops.regops; | ||
665 | gops->mc = gv100_ops.mc; | 691 | gops->mc = gv100_ops.mc; |
666 | gops->debug = gv100_ops.debug; | 692 | gops->debug = gv100_ops.debug; |
667 | gops->dbg_session_ops = gv100_ops.dbg_session_ops; | 693 | gops->dbg_session_ops = gv100_ops.dbg_session_ops; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h index 52a7dfc4..dc4c377d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_proj_gv100.h | |||
@@ -76,6 +76,14 @@ static inline u32 proj_lts_stride_v(void) | |||
76 | { | 76 | { |
77 | return 0x00000200U; | 77 | return 0x00000200U; |
78 | } | 78 | } |
79 | static inline u32 proj_fbpa_base_v(void) | ||
80 | { | ||
81 | return 0x00900000U; | ||
82 | } | ||
83 | static inline u32 proj_fbpa_shared_base_v(void) | ||
84 | { | ||
85 | return 0x009a0000U; | ||
86 | } | ||
79 | static inline u32 proj_fbpa_stride_v(void) | 87 | static inline u32 proj_fbpa_stride_v(void) |
80 | { | 88 | { |
81 | return 0x00004000U; | 89 | return 0x00004000U; |
@@ -84,6 +92,10 @@ static inline u32 proj_ppc_in_gpc_base_v(void) | |||
84 | { | 92 | { |
85 | return 0x00003000U; | 93 | return 0x00003000U; |
86 | } | 94 | } |
95 | static inline u32 proj_ppc_in_gpc_shared_base_v(void) | ||
96 | { | ||
97 | return 0x00003e00U; | ||
98 | } | ||
87 | static inline u32 proj_ppc_in_gpc_stride_v(void) | 99 | static inline u32 proj_ppc_in_gpc_stride_v(void) |
88 | { | 100 | { |
89 | return 0x00000200U; | 101 | return 0x00000200U; |
@@ -112,6 +124,22 @@ static inline u32 proj_tpc_in_gpc_shared_base_v(void) | |||
112 | { | 124 | { |
113 | return 0x00001800U; | 125 | return 0x00001800U; |
114 | } | 126 | } |
127 | static inline u32 proj_smpc_base_v(void) | ||
128 | { | ||
129 | return 0x00000200U; | ||
130 | } | ||
131 | static inline u32 proj_smpc_shared_base_v(void) | ||
132 | { | ||
133 | return 0x00000300U; | ||
134 | } | ||
135 | static inline u32 proj_smpc_unique_base_v(void) | ||
136 | { | ||
137 | return 0x00000600U; | ||
138 | } | ||
139 | static inline u32 proj_smpc_stride_v(void) | ||
140 | { | ||
141 | return 0x00000100U; | ||
142 | } | ||
115 | static inline u32 proj_host_num_engines_v(void) | 143 | static inline u32 proj_host_num_engines_v(void) |
116 | { | 144 | { |
117 | return 0x0000000fU; | 145 | return 0x0000000fU; |