diff options
author | Debarshi Dutta <ddutta@nvidia.com> | 2019-11-15 04:29:31 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-02-19 13:41:27 -0500 |
commit | e45e7b5cf87eaf94cf22e631c906170890233d8e (patch) | |
tree | 880fc3d736a3b8a0f595f097dd6f94ffbb0de9e9 /drivers/gpu | |
parent | 380e6b2c0c5e03f35aed68b836f64c907070e297 (diff) |
gpu: nvgpu: move cg_enable after pmu_init is complete
This patch help resolve the boot time failures happening with
pmu_exterr for porg. cg_enable can race with pmu_init thread,
cg_enable is moved post pmu init thread to avoid the above race.
Bug 200565050
Change-Id: I2192053eff8767847ea012ca20b3607d2f6cd26f
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2239959
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/common/pmu/pmu.c | 9 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/common/power_features/cg/cg.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 7 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h | 4 |
4 files changed, 45 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/common/pmu/pmu.c b/drivers/gpu/nvgpu/common/pmu/pmu.c index 8d051e5a..59d38277 100644 --- a/drivers/gpu/nvgpu/common/pmu/pmu.c +++ b/drivers/gpu/nvgpu/common/pmu/pmu.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2017-2019, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2017-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -526,6 +526,13 @@ static int nvgpu_pg_init_task(void *arg) | |||
526 | nvgpu_pmu_dbg(g, "loaded zbc"); | 526 | nvgpu_pmu_dbg(g, "loaded zbc"); |
527 | pmu_setup_hw_enable_elpg(g); | 527 | pmu_setup_hw_enable_elpg(g); |
528 | nvgpu_pmu_dbg(g, "PMU booted, thread exiting"); | 528 | nvgpu_pmu_dbg(g, "PMU booted, thread exiting"); |
529 | |||
530 | gk20a_gr_wait_initialized(g); | ||
531 | |||
532 | nvgpu_cg_blcg_enable_no_wait(g); | ||
533 | |||
534 | nvgpu_cg_elcg_enable_no_wait(g); | ||
535 | |||
529 | return 0; | 536 | return 0; |
530 | default: | 537 | default: |
531 | nvgpu_pmu_dbg(g, "invalid state"); | 538 | nvgpu_pmu_dbg(g, "invalid state"); |
diff --git a/drivers/gpu/nvgpu/common/power_features/cg/cg.c b/drivers/gpu/nvgpu/common/power_features/cg/cg.c index 39796bc8..a966c4c6 100644 --- a/drivers/gpu/nvgpu/common/power_features/cg/cg.c +++ b/drivers/gpu/nvgpu/common/power_features/cg/cg.c | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -84,6 +84,34 @@ void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g) | |||
84 | nvgpu_mutex_release(&g->cg_pg_lock); | 84 | nvgpu_mutex_release(&g->cg_pg_lock); |
85 | } | 85 | } |
86 | 86 | ||
87 | void nvgpu_cg_blcg_disable_no_wait(struct gk20a *g) { | ||
88 | nvgpu_log_fn(g, " "); | ||
89 | |||
90 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
91 | return; | ||
92 | } | ||
93 | |||
94 | nvgpu_mutex_acquire(&g->cg_pg_lock); | ||
95 | if (g->blcg_enabled) { | ||
96 | nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_RUN); | ||
97 | } | ||
98 | nvgpu_mutex_release(&g->cg_pg_lock); | ||
99 | } | ||
100 | |||
101 | void nvgpu_cg_blcg_enable_no_wait(struct gk20a *g) { | ||
102 | nvgpu_log_fn(g, " "); | ||
103 | |||
104 | if (!nvgpu_is_enabled(g, NVGPU_GPU_CAN_BLCG)) { | ||
105 | return; | ||
106 | } | ||
107 | |||
108 | nvgpu_mutex_acquire(&g->cg_pg_lock); | ||
109 | if (g->blcg_enabled) { | ||
110 | nvgpu_cg_set_mode(g, BLCG_MODE, BLCG_AUTO); | ||
111 | } | ||
112 | nvgpu_mutex_release(&g->cg_pg_lock); | ||
113 | } | ||
114 | |||
87 | void nvgpu_cg_elcg_enable(struct gk20a *g) | 115 | void nvgpu_cg_elcg_enable(struct gk20a *g) |
88 | { | 116 | { |
89 | nvgpu_log_fn(g, " "); | 117 | nvgpu_log_fn(g, " "); |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 223937c6..4f897b97 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GK20A Graphics | 2 | * GK20A Graphics |
3 | * | 3 | * |
4 | * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -4692,6 +4692,9 @@ static int gk20a_init_gr_prepare(struct gk20a *g) | |||
4692 | /* Disable elcg until it gets enabled later in the init*/ | 4692 | /* Disable elcg until it gets enabled later in the init*/ |
4693 | nvgpu_cg_elcg_disable_no_wait(g); | 4693 | nvgpu_cg_elcg_disable_no_wait(g); |
4694 | 4694 | ||
4695 | /* Disable blcg until it gets enabled later in the init*/ | ||
4696 | nvgpu_cg_blcg_disable_no_wait(g); | ||
4697 | |||
4695 | /* enable fifo access */ | 4698 | /* enable fifo access */ |
4696 | gk20a_writel(g, gr_gpfifo_ctl_r(), | 4699 | gk20a_writel(g, gr_gpfifo_ctl_r(), |
4697 | gr_gpfifo_ctl_access_enabled_f() | | 4700 | gr_gpfifo_ctl_access_enabled_f() | |
@@ -5012,7 +5015,6 @@ int gk20a_init_gr_support(struct gk20a *g) | |||
5012 | } | 5015 | } |
5013 | } | 5016 | } |
5014 | 5017 | ||
5015 | nvgpu_cg_elcg_enable_no_wait(g); | ||
5016 | /* GR is inialized, signal possible waiters */ | 5018 | /* GR is inialized, signal possible waiters */ |
5017 | g->gr.initialized = true; | 5019 | g->gr.initialized = true; |
5018 | nvgpu_cond_signal(&g->gr.init_wq); | 5020 | nvgpu_cond_signal(&g->gr.init_wq); |
@@ -5159,6 +5161,7 @@ int gk20a_gr_reset(struct gk20a *g) | |||
5159 | 5161 | ||
5160 | nvgpu_cg_init_gr_load_gating_prod(g); | 5162 | nvgpu_cg_init_gr_load_gating_prod(g); |
5161 | nvgpu_cg_elcg_enable_no_wait(g); | 5163 | nvgpu_cg_elcg_enable_no_wait(g); |
5164 | nvgpu_cg_blcg_enable_no_wait(g); | ||
5162 | 5165 | ||
5163 | /* GR is inialized, signal possible waiters */ | 5166 | /* GR is inialized, signal possible waiters */ |
5164 | g->gr.initialized = true; | 5167 | g->gr.initialized = true; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h index 7b5fe265..e2395176 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h +++ b/drivers/gpu/nvgpu/include/nvgpu/power_features/cg.h | |||
@@ -1,5 +1,5 @@ | |||
1 | /* | 1 | /* |
2 | * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved. | 2 | * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved. |
3 | * | 3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
5 | * copy of this software and associated documentation files (the "Software"), | 5 | * copy of this software and associated documentation files (the "Software"), |
@@ -35,6 +35,8 @@ void nvgpu_cg_elcg_disable(struct gk20a *g); | |||
35 | void nvgpu_cg_elcg_enable_no_wait(struct gk20a *g); | 35 | void nvgpu_cg_elcg_enable_no_wait(struct gk20a *g); |
36 | void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g); | 36 | void nvgpu_cg_elcg_disable_no_wait(struct gk20a *g); |
37 | void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable); | 37 | void nvgpu_cg_elcg_set_elcg_enabled(struct gk20a *g, bool enable); |
38 | void nvgpu_cg_blcg_disable_no_wait(struct gk20a *g); | ||
39 | void nvgpu_cg_blcg_enable_no_wait(struct gk20a *g); | ||
38 | 40 | ||
39 | void nvgpu_cg_blcg_mode_enable(struct gk20a *g); | 41 | void nvgpu_cg_blcg_mode_enable(struct gk20a *g); |
40 | void nvgpu_cg_blcg_mode_disable(struct gk20a *g); | 42 | void nvgpu_cg_blcg_mode_disable(struct gk20a *g); |