summaryrefslogtreecommitdiffstats
path: root/drivers/gpu
diff options
context:
space:
mode:
authorThomas Fleury <tfleury@nvidia.com>2019-08-27 10:09:51 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2020-01-30 02:42:46 -0500
commite41fd090315ff37fa09314a8cfde6d384385e17a (patch)
tree8d96902ff2749cd94f0630202af56a577a780a01 /drivers/gpu
parente0587aaf4d8f803004365eef2b08c0becd1042cb (diff)
gpu: nvgpu: use refcnt for ch mmu_debug_mode
Replaced ch->mmu_debug_mode_enabled with ch->mmu_debug_mode_refcnt. If channel is enabled multiple times by userspace, then ref count is updated accordingly. There is an expectation that enable/disable calls are balanced for setting channel's mmu debug mode. When unbinding the channel, decrease refcnt for the channel until it reaches 0. Also, removed tsg parameter from nvgpu_tsg_set_mmu_debug_mode as it can be retrieved from ch. Bug 2515097 Bug 2713590 Change-Id: If334e374a55bd14ae219edbfd3b1fce5ff25c226 Signed-off-by: Thomas Fleury <tfleury@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2184702 (cherry picked from commit f422aee39387a5aa337de69cc21a67f16697ae0e) Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208772 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Kajetan Dutka <kdutka@nvidia.com> Reviewed-by: Alex Waterman <alexw@nvidia.com> Reviewed-by: Winnie Hsu <whsu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: Kajetan Dutka <kdutka@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/nvgpu/common/fifo/tsg.c17
-rw-r--r--drivers/gpu/nvgpu/gk20a/fifo_gk20a.c11
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/channel.h6
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/tsg.h3
-rw-r--r--drivers/gpu/nvgpu/os/linux/ioctl_dbg.c2
5 files changed, 23 insertions, 16 deletions
diff --git a/drivers/gpu/nvgpu/common/fifo/tsg.c b/drivers/gpu/nvgpu/common/fifo/tsg.c
index 7f61b273..65cee225 100644
--- a/drivers/gpu/nvgpu/common/fifo/tsg.c
+++ b/drivers/gpu/nvgpu/common/fifo/tsg.c
@@ -446,13 +446,14 @@ void gk20a_tsg_update_sm_error_state_locked(struct tsg_gk20a *tsg,
446 sm_error_state->hww_warp_esr_report_mask; 446 sm_error_state->hww_warp_esr_report_mask;
447} 447}
448 448
449int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, 449int nvgpu_tsg_set_mmu_debug_mode(struct channel_gk20a *ch, bool enable)
450 struct channel_gk20a *ch, bool enable)
451{ 450{
452 struct gk20a *g; 451 struct gk20a *g;
453 int err = 0; 452 int err = 0;
453 u32 ch_refcnt;
454 u32 tsg_refcnt; 454 u32 tsg_refcnt;
455 u32 fb_refcnt; 455 u32 fb_refcnt;
456 struct tsg_gk20a *tsg = tsg_gk20a_from_ch(ch);
456 457
457 if ((ch == NULL) || (tsg == NULL)) { 458 if ((ch == NULL) || (tsg == NULL)) {
458 return -EINVAL; 459 return -EINVAL;
@@ -465,17 +466,11 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg,
465 } 466 }
466 467
467 if (enable) { 468 if (enable) {
468 if (ch->mmu_debug_mode_enabled) { 469 ch_refcnt = ch->mmu_debug_mode_refcnt + 1U;
469 /* already enabled for this channel */
470 return 0;
471 }
472 tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U; 470 tsg_refcnt = tsg->mmu_debug_mode_refcnt + 1U;
473 fb_refcnt = g->mmu_debug_mode_refcnt + 1U; 471 fb_refcnt = g->mmu_debug_mode_refcnt + 1U;
474 } else { 472 } else {
475 if (!ch->mmu_debug_mode_enabled) { 473 ch_refcnt = ch->mmu_debug_mode_refcnt - 1U;
476 /* already disabled for this channel */
477 return 0;
478 }
479 tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U; 474 tsg_refcnt = tsg->mmu_debug_mode_refcnt - 1U;
480 fb_refcnt = g->mmu_debug_mode_refcnt - 1U; 475 fb_refcnt = g->mmu_debug_mode_refcnt - 1U;
481 } 476 }
@@ -500,7 +495,7 @@ int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg,
500 g->ops.fb.set_mmu_debug_mode(g, fb_refcnt > 0U); 495 g->ops.fb.set_mmu_debug_mode(g, fb_refcnt > 0U);
501 } 496 }
502 497
503 ch->mmu_debug_mode_enabled = enable; 498 ch->mmu_debug_mode_refcnt = ch_refcnt;
504 tsg->mmu_debug_mode_refcnt = tsg_refcnt; 499 tsg->mmu_debug_mode_refcnt = tsg_refcnt;
505 g->mmu_debug_mode_refcnt = fb_refcnt; 500 g->mmu_debug_mode_refcnt = fb_refcnt;
506 501
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 1b18a8f9..4d62d8e9 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -1,7 +1,7 @@
1/* 1/*
2 * GK20A Graphics FIFO (gr host) 2 * GK20A Graphics FIFO (gr host)
3 * 3 *
4 * Copyright (c) 2011-2019, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2011-2020, NVIDIA CORPORATION. All rights reserved.
5 * 5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a 6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"), 7 * copy of this software and associated documentation files (the "Software"),
@@ -2250,6 +2250,15 @@ int gk20a_fifo_tsg_unbind_channel(struct channel_gk20a *ch)
2250 goto fail_enable_tsg; 2250 goto fail_enable_tsg;
2251 } 2251 }
2252 2252
2253 while (ch->mmu_debug_mode_refcnt > 0U) {
2254 err = nvgpu_tsg_set_mmu_debug_mode(ch, false);
2255 if (err != 0) {
2256 nvgpu_err(g, "disable mmu debug mode failed ch:%u",
2257 ch->chid);
2258 break;
2259 }
2260 }
2261
2253 /* Remove channel from TSG and re-enable rest of the channels */ 2262 /* Remove channel from TSG and re-enable rest of the channels */
2254 nvgpu_rwsem_down_write(&tsg->ch_list_lock); 2263 nvgpu_rwsem_down_write(&tsg->ch_list_lock);
2255 nvgpu_list_del(&ch->ch_entry); 2264 nvgpu_list_del(&ch->ch_entry);
diff --git a/drivers/gpu/nvgpu/include/nvgpu/channel.h b/drivers/gpu/nvgpu/include/nvgpu/channel.h
index e98af09b..764d047c 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/channel.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/channel.h
@@ -328,7 +328,11 @@ struct channel_gk20a {
328 bool has_os_fence_framework_support; 328 bool has_os_fence_framework_support;
329 329
330 bool is_privileged_channel; 330 bool is_privileged_channel;
331 bool mmu_debug_mode_enabled; 331
332 /**
333 * MMU Debugger Mode is enabled for this channel if refcnt > 0
334 */
335 u32 mmu_debug_mode_refcnt;
332}; 336};
333 337
334static inline struct channel_gk20a * 338static inline struct channel_gk20a *
diff --git a/drivers/gpu/nvgpu/include/nvgpu/tsg.h b/drivers/gpu/nvgpu/include/nvgpu/tsg.h
index b43a6b98..7cd97c97 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/tsg.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/tsg.h
@@ -127,7 +127,6 @@ gk20a_event_id_data_from_event_id_node(struct nvgpu_list_node *node)
127 ((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node)); 127 ((uintptr_t)node - offsetof(struct gk20a_event_id_data, event_id_node));
128}; 128};
129 129
130int nvgpu_tsg_set_mmu_debug_mode(struct tsg_gk20a *tsg, 130int nvgpu_tsg_set_mmu_debug_mode(struct channel_gk20a *ch, bool enable);
131 struct channel_gk20a *ch, bool enable);
132 131
133#endif /* TSG_GK20A_H */ 132#endif /* TSG_GK20A_H */
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
index aeed07ce..dc732dc5 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c
@@ -1112,7 +1112,7 @@ static int nvgpu_dbg_gpu_ioctl_set_mmu_debug_mode(
1112 goto clean_up; 1112 goto clean_up;
1113 } 1113 }
1114 1114
1115 err = nvgpu_tsg_set_mmu_debug_mode(tsg_gk20a_from_ch(ch), ch, enable); 1115 err = nvgpu_tsg_set_mmu_debug_mode(ch, enable);
1116 if (err) { 1116 if (err) {
1117 nvgpu_err(g, "set mmu debug mode failed, err=%d", err); 1117 nvgpu_err(g, "set mmu debug mode failed, err=%d", err);
1118 } 1118 }