diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-03-21 12:57:25 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-28 12:39:13 -0400 |
commit | e1c4d19b4cd2462c2f5b8c6653573ea0e6bbe823 (patch) | |
tree | 35b1e66c18468d7542be0e40437a6b228b6c8c9e /drivers/gpu | |
parent | c363253c4575b59466e9390943c6b8b5ccfd068f (diff) |
gpu: nvgpu: add and reorg reset_enable_hw fifo ops
fifo reset_enable_hw is reorged to clear and enable pbdma/fifo interrupts
after all the required configuration such as configuring timeouts,
enabling timeout detections are taken care of.
JIRA GPUT19X-74
JIRA GPUT19X-47
Change-Id: Id780cc11d858db18f8d748c037954ede73298506
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1325351
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 62 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.c | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 |
5 files changed, 38 insertions, 31 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index 6c4f12df..35a07439 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -726,8 +726,6 @@ clean_up_runlist: | |||
726 | return -ENOMEM; | 726 | return -ENOMEM; |
727 | } | 727 | } |
728 | 728 | ||
729 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 | ||
730 | |||
731 | u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g) | 729 | u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g) |
732 | { | 730 | { |
733 | u32 intr_0_error_mask = | 731 | u32 intr_0_error_mask = |
@@ -765,6 +763,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
765 | u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); | 763 | u32 host_num_pbdma = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_PBDMA); |
766 | 764 | ||
767 | gk20a_dbg_fn(""); | 765 | gk20a_dbg_fn(""); |
766 | |||
768 | /* enable pmc pfifo */ | 767 | /* enable pmc pfifo */ |
769 | g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); | 768 | g->ops.mc.reset(g, mc_enable_pfifo_enabled_f()); |
770 | 769 | ||
@@ -784,36 +783,10 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
784 | mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); | 783 | mask |= mc_enable_pb_sel_f(mc_enable_pb_0_enabled_v(), i); |
785 | gk20a_writel(g, mc_enable_pb_r(), mask); | 784 | gk20a_writel(g, mc_enable_pb_r(), mask); |
786 | 785 | ||
787 | /* enable pfifo interrupt */ | ||
788 | gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); | ||
789 | gk20a_writel(g, fifo_intr_en_0_r(), gk20a_fifo_intr_0_en_mask(g)); | ||
790 | gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); | ||
791 | |||
792 | /* enable pbdma interrupt */ | ||
793 | mask = 0; | ||
794 | for (i = 0; i < host_num_pbdma; i++) { | ||
795 | intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); | ||
796 | intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f(); | ||
797 | gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); | ||
798 | gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); | ||
799 | gk20a_writel(g, pbdma_intr_en_0_r(i), | ||
800 | ~pbdma_intr_en_0_lbreq_enabled_f()); | ||
801 | gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF); | ||
802 | gk20a_writel(g, pbdma_intr_en_1_r(i), | ||
803 | ~pbdma_intr_en_0_lbreq_enabled_f()); | ||
804 | } | ||
805 | |||
806 | /* TBD: apply overrides */ | ||
807 | |||
808 | /* TBD: BLCG prod */ | ||
809 | |||
810 | /* reset runlist interrupts */ | ||
811 | gk20a_writel(g, fifo_intr_runlist_r(), ~0); | ||
812 | |||
813 | /* TBD: do we need those? */ | ||
814 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); | 786 | timeout = gk20a_readl(g, fifo_fb_timeout_r()); |
815 | timeout = set_field(timeout, fifo_fb_timeout_period_m(), | 787 | timeout = set_field(timeout, fifo_fb_timeout_period_m(), |
816 | fifo_fb_timeout_period_max_f()); | 788 | fifo_fb_timeout_period_max_f()); |
789 | gk20a_dbg_info("fifo_fb_timeout reg val = 0x%08x", timeout); | ||
817 | gk20a_writel(g, fifo_fb_timeout_r(), timeout); | 790 | gk20a_writel(g, fifo_fb_timeout_r(), timeout); |
818 | 791 | ||
819 | /* write pbdma timeout value */ | 792 | /* write pbdma timeout value */ |
@@ -821,9 +794,9 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
821 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); | 794 | timeout = gk20a_readl(g, pbdma_timeout_r(i)); |
822 | timeout = set_field(timeout, pbdma_timeout_period_m(), | 795 | timeout = set_field(timeout, pbdma_timeout_period_m(), |
823 | pbdma_timeout_period_max_f()); | 796 | pbdma_timeout_period_max_f()); |
797 | gk20a_dbg_info("pbdma_timeout reg val = 0x%08x", timeout); | ||
824 | gk20a_writel(g, pbdma_timeout_r(i), timeout); | 798 | gk20a_writel(g, pbdma_timeout_r(i), timeout); |
825 | } | 799 | } |
826 | |||
827 | if (g->ops.fifo.apply_pb_timeout) | 800 | if (g->ops.fifo.apply_pb_timeout) |
828 | g->ops.fifo.apply_pb_timeout(g); | 801 | g->ops.fifo.apply_pb_timeout(g); |
829 | 802 | ||
@@ -833,6 +806,34 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
833 | timeout |= fifo_eng_timeout_detection_enabled_f(); | 806 | timeout |= fifo_eng_timeout_detection_enabled_f(); |
834 | gk20a_writel(g, fifo_eng_timeout_r(), timeout); | 807 | gk20a_writel(g, fifo_eng_timeout_r(), timeout); |
835 | 808 | ||
809 | /* clear and enable pbdma interrupt */ | ||
810 | for (i = 0; i < host_num_pbdma; i++) { | ||
811 | gk20a_writel(g, pbdma_intr_0_r(i), 0xFFFFFFFF); | ||
812 | gk20a_writel(g, pbdma_intr_1_r(i), 0xFFFFFFFF); | ||
813 | |||
814 | intr_stall = gk20a_readl(g, pbdma_intr_stall_r(i)); | ||
815 | intr_stall &= ~pbdma_intr_stall_lbreq_enabled_f(); | ||
816 | gk20a_writel(g, pbdma_intr_stall_r(i), intr_stall); | ||
817 | gk20a_dbg_info("pbdma id:%u, intr_en_0 0x%08x", i, intr_stall); | ||
818 | gk20a_writel(g, pbdma_intr_en_0_r(i), intr_stall); | ||
819 | |||
820 | gk20a_dbg_info("pbdma id:%u, intr_en_1 0x%08x", i, | ||
821 | ~pbdma_intr_en_0_lbreq_enabled_f()); | ||
822 | gk20a_writel(g, pbdma_intr_en_1_r(i), | ||
823 | ~pbdma_intr_en_0_lbreq_enabled_f()); | ||
824 | } | ||
825 | |||
826 | /* reset runlist interrupts */ | ||
827 | gk20a_writel(g, fifo_intr_runlist_r(), ~0); | ||
828 | |||
829 | /* clear and enable pfifo interrupt */ | ||
830 | gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); | ||
831 | mask = gk20a_fifo_intr_0_en_mask(g); | ||
832 | gk20a_dbg_info("fifo_intr_en_0 0x%08x", mask); | ||
833 | gk20a_writel(g, fifo_intr_en_0_r(), mask); | ||
834 | gk20a_dbg_info("fifo_intr_en_1 = 0x80000000"); | ||
835 | gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); | ||
836 | |||
836 | gk20a_dbg_fn("done"); | 837 | gk20a_dbg_fn("done"); |
837 | 838 | ||
838 | return 0; | 839 | return 0; |
@@ -3881,4 +3882,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
3881 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; | 3882 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; |
3882 | gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; | 3883 | gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; |
3883 | gops->fifo.init_pbdma_intr_descs = gk20a_fifo_init_pbdma_intr_descs; | 3884 | gops->fifo.init_pbdma_intr_descs = gk20a_fifo_init_pbdma_intr_descs; |
3885 | gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw; | ||
3884 | } | 3886 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index ae728a36..a9703385 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -38,6 +38,8 @@ | |||
38 | #define PREEMPT_TIMEOUT_RC 1 | 38 | #define PREEMPT_TIMEOUT_RC 1 |
39 | #define PREEMPT_TIMEOUT_NORC 0 | 39 | #define PREEMPT_TIMEOUT_NORC 0 |
40 | 40 | ||
41 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 | ||
42 | |||
41 | /* | 43 | /* |
42 | * Number of entries in the kickoff latency buffer, used to calculate | 44 | * Number of entries in the kickoff latency buffer, used to calculate |
43 | * the profiling and histogram. This number is calculated to be statistically | 45 | * the profiling and histogram. This number is calculated to be statistically |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c index e77986be..b715e661 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gk20a.c | |||
@@ -567,7 +567,8 @@ int gk20a_pm_finalize_poweron(struct device *dev) | |||
567 | } | 567 | } |
568 | } | 568 | } |
569 | 569 | ||
570 | err = gk20a_init_fifo_reset_enable_hw(g); | 570 | err = g->ops.fifo.reset_enable_hw(g); |
571 | |||
571 | if (err) { | 572 | if (err) { |
572 | gk20a_err(dev, "failed to reset gk20a fifo"); | 573 | gk20a_err(dev, "failed to reset gk20a fifo"); |
573 | goto done; | 574 | goto done; |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 4e1c4ff4..ce26125d 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -456,6 +456,7 @@ struct gpu_ops { | |||
456 | int (*preempt_ch_tsg)(struct gk20a *g, u32 id, | 456 | int (*preempt_ch_tsg)(struct gk20a *g, u32 id, |
457 | unsigned int id_type, unsigned int timeout_rc_type); | 457 | unsigned int id_type, unsigned int timeout_rc_type); |
458 | void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); | 458 | void (*init_pbdma_intr_descs)(struct fifo_gk20a *f); |
459 | int (*reset_enable_hw)(struct gk20a *g); | ||
459 | } fifo; | 460 | } fifo; |
460 | struct pmu_v { | 461 | struct pmu_v { |
461 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 462 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 5a0bd39e..f09da825 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -223,4 +223,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
223 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; | 223 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; |
224 | gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; | 224 | gops->fifo.is_preempt_pending = gk20a_fifo_is_preempt_pending; |
225 | gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs; | 225 | gops->fifo.init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs; |
226 | gops->fifo.reset_enable_hw = gk20a_init_fifo_reset_enable_hw; | ||
226 | } | 227 | } |