diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2014-12-09 01:15:51 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:12:31 -0400 |
commit | d37aa77ab5f0edd3225af31fef389bc066f20fda (patch) | |
tree | 8e56d9e8a9cafe8c6f912878a1466ba303561112 /drivers/gpu | |
parent | 31f47b8306232565b60d43d7d974699faa997cf3 (diff) |
gpu: nvgpu: Allow enabling/disabling MC interrupt
Added method to enable/disable MC interrupt by unit
Bug 200064127
Change-Id: I89e794d5b69a2a93642e2df437d6744bf595f021
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/661211
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/mc_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 15 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/mc_gm20b.c | 1 |
5 files changed, 33 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 75c6ef89..4333cd20 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -61,6 +61,9 @@ enum gk20a_cbc_op { | |||
61 | gk20a_cbc_op_invalidate, | 61 | gk20a_cbc_op_invalidate, |
62 | }; | 62 | }; |
63 | 63 | ||
64 | #define MC_INTR_UNIT_DISABLE false | ||
65 | #define MC_INTR_UNIT_ENABLE true | ||
66 | |||
64 | struct gpu_ops { | 67 | struct gpu_ops { |
65 | struct { | 68 | struct { |
66 | int (*determine_L2_size_bytes)(struct gk20a *gk20a); | 69 | int (*determine_L2_size_bytes)(struct gk20a *gk20a); |
@@ -360,10 +363,13 @@ struct gpu_ops { | |||
360 | } regops; | 363 | } regops; |
361 | struct { | 364 | struct { |
362 | void (*intr_enable)(struct gk20a *g); | 365 | void (*intr_enable)(struct gk20a *g); |
366 | void (*intr_unit_config)(struct gk20a *g, | ||
367 | bool enable, bool is_stalling, u32 unit); | ||
363 | irqreturn_t (*isr_stall)(struct gk20a *g); | 368 | irqreturn_t (*isr_stall)(struct gk20a *g); |
364 | irqreturn_t (*isr_nonstall)(struct gk20a *g); | 369 | irqreturn_t (*isr_nonstall)(struct gk20a *g); |
365 | irqreturn_t (*isr_thread_stall)(struct gk20a *g); | 370 | irqreturn_t (*isr_thread_stall)(struct gk20a *g); |
366 | irqreturn_t (*isr_thread_nonstall)(struct gk20a *g); | 371 | irqreturn_t (*isr_thread_nonstall)(struct gk20a *g); |
372 | u32 intr_mask_restore[4]; | ||
367 | } mc; | 373 | } mc; |
368 | }; | 374 | }; |
369 | 375 | ||
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c index 4d176403..899eeff7 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c | |||
@@ -137,9 +137,27 @@ void mc_gk20a_intr_enable(struct gk20a *g) | |||
137 | mc_intr_en_0_inta_hardware_f()); | 137 | mc_intr_en_0_inta_hardware_f()); |
138 | } | 138 | } |
139 | 139 | ||
140 | void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, | ||
141 | bool is_stalling, u32 mask) | ||
142 | { | ||
143 | u32 mask_reg = (is_stalling ? mc_intr_mask_0_r() : | ||
144 | mc_intr_mask_1_r()); | ||
145 | |||
146 | if (enable) { | ||
147 | gk20a_writel(g, mask_reg, | ||
148 | gk20a_readl(g, mask_reg) | | ||
149 | mask); | ||
150 | } else { | ||
151 | gk20a_writel(g, mask_reg, | ||
152 | gk20a_readl(g, mask_reg) & | ||
153 | ~mask); | ||
154 | } | ||
155 | } | ||
156 | |||
140 | void gk20a_init_mc(struct gpu_ops *gops) | 157 | void gk20a_init_mc(struct gpu_ops *gops) |
141 | { | 158 | { |
142 | gops->mc.intr_enable = mc_gk20a_intr_enable; | 159 | gops->mc.intr_enable = mc_gk20a_intr_enable; |
160 | gops->mc.intr_unit_config = mc_gk20a_intr_unit_config; | ||
143 | gops->mc.isr_stall = mc_gk20a_isr_stall; | 161 | gops->mc.isr_stall = mc_gk20a_isr_stall; |
144 | gops->mc.isr_nonstall = mc_gk20a_isr_nonstall; | 162 | gops->mc.isr_nonstall = mc_gk20a_isr_nonstall; |
145 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; | 163 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; |
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h index 7264ab41..4bb3e118 100644 --- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h | |||
@@ -17,6 +17,8 @@ struct gk20a; | |||
17 | 17 | ||
18 | void gk20a_init_mc(struct gpu_ops *gops); | 18 | void gk20a_init_mc(struct gpu_ops *gops); |
19 | void mc_gk20a_intr_enable(struct gk20a *g); | 19 | void mc_gk20a_intr_enable(struct gk20a *g); |
20 | void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable, | ||
21 | bool is_stalling, u32 mask); | ||
20 | irqreturn_t mc_gk20a_isr_stall(struct gk20a *g); | 22 | irqreturn_t mc_gk20a_isr_stall(struct gk20a *g); |
21 | irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g); | 23 | irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g); |
22 | irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g); | 24 | irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index 4471b0f1..27478750 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -1178,12 +1178,10 @@ void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable) | |||
1178 | 1178 | ||
1179 | gk20a_dbg_fn(""); | 1179 | gk20a_dbg_fn(""); |
1180 | 1180 | ||
1181 | gk20a_writel(g, mc_intr_mask_0_r(), | 1181 | g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_DISABLE, true, |
1182 | gk20a_readl(g, mc_intr_mask_0_r()) & | 1182 | mc_intr_mask_0_pmu_enabled_f()); |
1183 | ~mc_intr_mask_0_pmu_enabled_f()); | 1183 | g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_DISABLE, false, |
1184 | gk20a_writel(g, mc_intr_mask_1_r(), | 1184 | mc_intr_mask_1_pmu_enabled_f()); |
1185 | gk20a_readl(g, mc_intr_mask_1_r()) & | ||
1186 | ~mc_intr_mask_1_pmu_enabled_f()); | ||
1187 | 1185 | ||
1188 | gk20a_writel(g, pwr_falcon_irqmclr_r(), | 1186 | gk20a_writel(g, pwr_falcon_irqmclr_r(), |
1189 | pwr_falcon_irqmclr_gptmr_f(1) | | 1187 | pwr_falcon_irqmclr_gptmr_f(1) | |
@@ -1229,9 +1227,8 @@ void pmu_enable_irq(struct pmu_gk20a *pmu, bool enable) | |||
1229 | pwr_falcon_irqmset_swgen0_f(1) | | 1227 | pwr_falcon_irqmset_swgen0_f(1) | |
1230 | pwr_falcon_irqmset_swgen1_f(1)); | 1228 | pwr_falcon_irqmset_swgen1_f(1)); |
1231 | 1229 | ||
1232 | gk20a_writel(g, mc_intr_mask_0_r(), | 1230 | g->ops.mc.intr_unit_config(g, MC_INTR_UNIT_ENABLE, true, |
1233 | gk20a_readl(g, mc_intr_mask_0_r()) | | 1231 | mc_intr_mask_0_pmu_enabled_f()); |
1234 | mc_intr_mask_0_pmu_enabled_f()); | ||
1235 | } | 1232 | } |
1236 | 1233 | ||
1237 | gk20a_dbg_fn("done"); | 1234 | gk20a_dbg_fn("done"); |
diff --git a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c index 22dce1e7..1d2d78e3 100644 --- a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c | |||
@@ -22,6 +22,7 @@ | |||
22 | void gm20b_init_mc(struct gpu_ops *gops) | 22 | void gm20b_init_mc(struct gpu_ops *gops) |
23 | { | 23 | { |
24 | gops->mc.intr_enable = mc_gk20a_intr_enable; | 24 | gops->mc.intr_enable = mc_gk20a_intr_enable; |
25 | gops->mc.intr_unit_config = mc_gk20a_intr_unit_config; | ||
25 | gops->mc.isr_stall = mc_gk20a_isr_stall; | 26 | gops->mc.isr_stall = mc_gk20a_isr_stall; |
26 | gops->mc.isr_nonstall = mc_gk20a_isr_nonstall; | 27 | gops->mc.isr_nonstall = mc_gk20a_isr_nonstall; |
27 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; | 28 | gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall; |