gpu: nvgpu: gv11b: init suspend_all_sms gr ops

This is required to support multiple SM and t19x
sm register address changes

JIRA GPUT19X-75

Change-Id: I46b7d58ed02710339aa27cd9db999aa60fbd4dd9
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1512208
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>

1 files changed, 48 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index 4f17a33c..84ff1335 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -1772,7 +1772,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g,
                                         "CILP: Broadcasting STOP_TRIGGER from "
                                         "gpc %d tpc %d sm %d",
                                         gpc, tpc, sm);
-                                gk20a_suspend_all_sms(g, global_mask, false);
+                                g->ops.gr.suspend_all_sms(g,
+                                                global_mask, false);
 
                                 gk20a_dbg_gpu_clear_broadcast_stop_trigger(fault_ch);
                         } else {
@@ -2798,6 +2799,51 @@ static void gv11b_gr_suspend_single_sm(struct gk20a *g,
         }
 }
 
+static void gv11b_gr_suspend_all_sms(struct gk20a *g,
+                u32 global_esr_mask, bool check_errors)
+{
+        struct gr_gk20a *gr = &g->gr;
+        u32 gpc, tpc, sm;
+        int err;
+        u32 dbgr_control0;
+        u32 sm_per_tpc = nvgpu_get_litter_value(g, GPU_LIT_NUM_SM_PER_TPC);
+
+        /* if an SM debugger isn't attached, skip suspend */
+        if (!g->ops.gr.sm_debugger_attached(g)) {
+                nvgpu_err(g,
+                        "SM debugger not attached, skipping suspend!");
+                return;
+        }
+
+        nvgpu_log(g, gpu_dbg_fn | gpu_dbg_gpu_dbg, "suspending all sms");
+
+        /* assert stop trigger. uniformity assumption: all SMs will have
+         * the same state in dbg_control0.
+         */
+        dbgr_control0 =
+                gk20a_readl(g, gr_gpc0_tpc0_sm0_dbgr_control0_r());
+        dbgr_control0 |= gr_gpc0_tpc0_sm0_dbgr_control0_stop_trigger_enable_f();
+
+        /* broadcast write */
+        gk20a_writel(g,
+                gr_gpcs_tpcs_sms_dbgr_control0_r(), dbgr_control0);
+
+        for (gpc = 0; gpc < gr->gpc_count; gpc++) {
+                for (tpc = 0; tpc < gr_gk20a_get_tpc_count(gr, gpc); tpc++) {
+                        for (sm = 0; sm < sm_per_tpc; sm++) {
+                                err = gk20a_gr_wait_for_sm_lock_down(g,
+                                        gpc, tpc,
+                                        global_esr_mask, check_errors);
+                                if (err) {
+                                        nvgpu_err(g,
+                                                "SuspendAllSms failed");
+                                        return;
+                                }
+                        }
+                }
+        }
+}
+
 void gv11b_init_gr(struct gpu_ops *gops)
 {
         gp10b_init_gr(gops);
@@ -2868,4 +2914,5 @@ void gv11b_init_gr(struct gpu_ops *gops)
         gops->gr.set_hww_esr_report_mask = gv11b_gr_set_hww_esr_report_mask;
         gops->gr.sm_debugger_attached = gv11b_gr_sm_debugger_attached;
         gops->gr.suspend_single_sm = gv11b_gr_suspend_single_sm;
+        gops->gr.suspend_all_sms = gv11b_gr_suspend_all_sms;
 }