gpu: nvgpu: pmgr: fix MISRA Rule 10.4 Violations

MISRA Rule 10.4 only allows the usage of arithmetic operations on
operands of the same essential type category.

Adding "U" at the end of the integer literals to have same type of
operands when an arithmetic operation is performed.

This fixes violation where an arithmetic operation is performed on
signed and unsigned int types.

JIRA NVGPU-992

Change-Id: Id3b2c8ea1af1807087468c6978abfbfc85bee2ec
Signed-off-by: Sai Nikhil <snikhil@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1809757
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Adeel Raza <araza@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

7 files changed, 55 insertions, 55 deletions

diff --git a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h
index e9df445f..cd13b85e 100644
--- a/drivers/gpu/nvgpu/boardobj/boardobjgrp.h
+++ b/drivers/gpu/nvgpu/boardobj/boardobjgrp.h
@@ -234,17 +234,17 @@ struct boardobjgrp {
 * be inserted contiguously (i.e. w/o fear of colliding with existing objects).
 */
 #define BOARDOBJGRP_NEXT_EMPTY_IDX(_pboardobjgrp)                              \
-        ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0 :       \
-        ((((_pboardobjgrp)->objmaxidx + 1) >= (_pboardobjgrp)->objslots) ?     \
-        (u8)CTRL_BOARDOBJ_IDX_INVALID : (u8)((_pboardobjgrp)->objmaxidx + 1)))
+        ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U :      \
+        ((((_pboardobjgrp)->objmaxidx + 1U) >= (_pboardobjgrp)->objslots) ?    \
+        (u8)CTRL_BOARDOBJ_IDX_INVALID : (u8)((_pboardobjgrp)->objmaxidx + 1U)))
 
 /*
 * Helper macro to determine the number of @ref BOARDOBJ pointers
 * that are required to be allocated in PMU @ref ppObjects.
 */
 #define BOARDOBJGRP_PMU_SLOTS_GET(_pboardobjgrp)                            \
-        ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0 :    \
-        (u8)((_pboardobjgrp)->objmaxidx + 1))
+        ((CTRL_BOARDOBJ_IDX_INVALID == (_pboardobjgrp)->objmaxidx) ? 0U :    \
+        (u8)((_pboardobjgrp)->objmaxidx + 1U))
 
 #define BOARDOBJGRP_OBJ_GET_BY_IDX(_pboardobjgrp, _idx)                     \
         ((_pboardobjgrp)->objgetbyidx((_pboardobjgrp), (_idx)))
@@ -274,8 +274,8 @@ struct boardobjgrp {
 #define BOARDOBJGRP_FOR_EACH_INDEX_IN_MASK(mask_width, index, mask)        \
 {                                                           \
         u##mask_width lcl_msk = (u##mask_width)(mask);         \
-        for (index = 0; lcl_msk != 0; index++, lcl_msk >>= 1) {     \
-                if (((u##mask_width)((u64)1) & lcl_msk) == 0) {     \
+        for (index = 0; lcl_msk != 0U; index++, lcl_msk >>= 1U) {     \
+                if (((u##mask_width)((u64)1) & lcl_msk) == 0U) {     \
                         continue;                                       \
                 }
 
@@ -289,22 +289,22 @@ struct boardobjgrp {
 * @ref BOARDOBJGRP::unitId and, thus, certain BOARDOBJGRP PMU interfaces are
 * not supported.
 */
-#define BOARDOBJGRP_UNIT_ID_INVALID                                   255
+#define BOARDOBJGRP_UNIT_ID_INVALID                                   255U
 
 /*!
 * Invalid UNIT_ID.  Used to indicate that the implementing class has not set
 * @ref BOARDOBJGRP::grpType and, thus, certain BOARDOBJGRP PMU interfaces are
 * not supported.
 */
-#define BOARDOBJGRP_GRP_CLASS_ID_INVALID                              255
+#define BOARDOBJGRP_GRP_CLASS_ID_INVALID                              255U
 
 /*!
 * Invalid UNIT_ID.  Used to indicate that the implementing class has not set
 * @ref BOARDOBJGRP::grpSetCmdId and, thus, certain BOARDOBJGRP PMU interfaces
 * are not supported.
 */
-#define BOARDOBJGRP_GRP_CMD_ID_INVALID                                255
-#define BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID                           255
+#define BOARDOBJGRP_GRP_CMD_ID_INVALID                                255U
+#define BOARDOBJGRP_GRP_RPC_FUNC_ID_INVALID                           255U
 
 /*!
 * Helper macro to construct a BOARDOBJGRP's PMU SW state.
@@ -379,14 +379,14 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask);
 
 #define HIGHESTBITIDX_32(n32)   \
 {                               \
-        u32 count = 0;        \
-        while (n32 >>= 1) {       \
+        u32 count = 0U;        \
+        while (n32 >>= 1U) {       \
                 count++;       \
         }                      \
         n32 = count;            \
 }
 
-#define LOWESTBIT(x)            ((x) &  (((x)-1) ^ (x)))
+#define LOWESTBIT(x)            ((x) &  (((x)-1U) ^ (x)))
 
 #define HIGHESTBIT(n32)     \
 {                           \
@@ -394,7 +394,7 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask);
         n32 = NVBIT(n32);       \
 }
 
-#define ONEBITSET(x)            ((x) && (((x) & ((x)-1)) == 0))
+#define ONEBITSET(x)            ((x) && (((x) & ((x)-1U)) == 0U))
 
 #define LOWESTBITIDX_32(n32)  \
 {                             \
@@ -404,24 +404,24 @@ void boardobjgrpe32hdrset(struct nv_pmu_boardobjgrp *hdr, u32 objmask);
 
 #define NUMSETBITS_32(n32)                                         \
 {                                                                  \
-        n32 = n32 - ((n32 >> 1) & 0x55555555);                         \
-        n32 = (n32 & 0x33333333) + ((n32 >> 2) & 0x33333333);          \
-        n32 = (((n32 + (n32 >> 4)) & 0x0F0F0F0F) * 0x01010101) >> 24;  \
+        n32 = n32 - ((n32 >> 1U) & 0x55555555U);                         \
+        n32 = (n32 & 0x33333333U) + ((n32 >> 2U) & 0x33333333U);          \
+        n32 = (((n32 + (n32 >> 4U)) & 0x0F0F0F0FU) * 0x01010101U) >> 24U;  \
 }
 
 #define IDX_32(n32)                     \
 {                                       \
-        u32 idx = 0;                      \
-        if ((n32) & 0xFFFF0000)             \
-                idx += 16;                  \
-        if ((n32) & 0xFF00FF00)             \
-                idx += 8;                   \
-        if ((n32) & 0xF0F0F0F0)             \
-                idx += 4;                   \
-        if ((n32) & 0xCCCCCCCC)             \
-                idx += 2;                   \
-        if ((n32) & 0xAAAAAAAA)             \
-                idx += 1;                   \
+        u32 idx = 0U;                      \
+        if ((n32) & 0xFFFF0000U)             \
+                idx += 16U;                  \
+        if ((n32) & 0xFF00FF00U)             \
+                idx += 8U;                   \
+        if ((n32) & 0xF0F0F0F0U)             \
+                idx += 4U;                   \
+        if ((n32) & 0xCCCCCCCCU)             \
+                idx += 2U;                   \
+        if ((n32) & 0xAAAAAAAAU)             \
+                idx += 1U;                   \
         (n32) = idx;                        \
 }
 
diff --git a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
index 165bbd5d..90f6501b 100644
--- a/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
+++ b/drivers/gpu/nvgpu/ctrl/ctrlpmgr.h
@@ -27,23 +27,23 @@
 #include "ctrlboardobj.h"
 
 /* valid power domain values */
-#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES 32
-#define CTRL_PMGR_PWR_VIOLATION_MAX 0x06
+#define CTRL_PMGR_PWR_DEVICES_MAX_DEVICES                       32U
+#define CTRL_PMGR_PWR_VIOLATION_MAX                             0x06U
 
-#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221                            0x4E
+#define CTRL_PMGR_PWR_DEVICE_TYPE_INA3221                       0x4EU
 
-#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID                          0xFF
-#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR                            0x08
+#define CTRL_PMGR_PWR_CHANNEL_INDEX_INVALID                     0xFFU
+#define CTRL_PMGR_PWR_CHANNEL_TYPE_SENSOR                       0x08U
 
-#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X                        0x30
-#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD                       0x04
-#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD                       0x0C
+#define CTRL_PMGR_PWR_POLICY_TABLE_VERSION_3X                   0x30U
+#define CTRL_PMGR_PWR_POLICY_TYPE_HW_THRESHOLD                  0x04U
+#define CTRL_PMGR_PWR_POLICY_TYPE_SW_THRESHOLD                  0x0CU
 
-#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS                       0x8
-#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES                         0x08
-#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID                           0xFF
-#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM                 0xFE
-#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX                       (0xFFFFFFFF)
+#define CTRL_PMGR_PWR_POLICY_MAX_LIMIT_INPUTS                   0x8U
+#define CTRL_PMGR_PWR_POLICY_IDX_NUM_INDEXES                    0x08U
+#define CTRL_PMGR_PWR_POLICY_INDEX_INVALID                      0xFFU
+#define CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM          0xFEU
+#define CTRL_PMGR_PWR_POLICY_LIMIT_MAX                          (0xFFFFFFFFU)
 
 struct ctrl_pmgr_pwr_device_info_rshunt {
         bool use_fxp8_8;
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index 411550be..b6947f20 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -52,7 +52,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
 
         if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_SET_OBJECT) {
                 if ((msg->msg.pmgr.set_object.b_success != 1) ||
-                        (msg->msg.pmgr.set_object.flcnstatus != 0) ) {
+                        (msg->msg.pmgr.set_object.flcnstatus != 0U)) {
                         nvgpu_err(g, "pmgr msg failed %x %x %x %x",
                                 msg->msg.pmgr.set_object.msg_type,
                                 msg->msg.pmgr.set_object.b_success,
@@ -62,7 +62,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
                 }
         } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_QUERY) {
                 if ((msg->msg.pmgr.query.b_success != 1) ||
-                        (msg->msg.pmgr.query.flcnstatus != 0) ) {
+                        (msg->msg.pmgr.query.flcnstatus != 0U)) {
                         nvgpu_err(g, "pmgr msg failed %x %x %x %x",
                                 msg->msg.pmgr.query.msg_type,
                                 msg->msg.pmgr.query.b_success,
@@ -72,7 +72,7 @@ static void pmgr_pmucmdhandler(struct gk20a *g, struct pmu_msg *msg,
                 }
         } else if (msg->msg.pmgr.msg_type == NV_PMU_PMGR_MSG_ID_LOAD) {
                 if ((msg->msg.pmgr.query.b_success != 1) ||
-                        (msg->msg.pmgr.query.flcnstatus != 0) ) {
+                        (msg->msg.pmgr.query.flcnstatus != 0U)) {
                         nvgpu_err(g, "pmgr msg failed %x %x %x",
                                 msg->msg.pmgr.load.msg_type,
                                 msg->msg.pmgr.load.b_success,
@@ -133,7 +133,7 @@ static u32 pmgr_pmu_set_object(struct gk20a *g,
                         gk20a_get_gr_idle_timeout(g),
                         &handlerparams.success, 1);
 
-        if (handlerparams.success == 0) {
+        if (handlerparams.success == 0U) {
                 nvgpu_err(g, "could not process cmd");
                 status = -ETIMEDOUT;
                 goto exit;
@@ -431,7 +431,7 @@ u32 pmgr_pmu_pwr_devices_query_blocking(
                         gk20a_get_gr_idle_timeout(g),
                         &handlerparams.success, 1);
 
-        if (handlerparams.success == 0) {
+        if (handlerparams.success == 0U) {
                 nvgpu_err(g, "could not process cmd");
                 status = -ETIMEDOUT;
                 goto exit;
@@ -475,7 +475,7 @@ static u32 pmgr_pmu_load_blocking(struct gk20a *g)
                         gk20a_get_gr_idle_timeout(g),
                         &handlerparams.success, 1);
 
-        if (handlerparams.success == 0) {
+        if (handlerparams.success == 0U) {
                 nvgpu_err(g, "could not process cmd");
                 status = -ETIMEDOUT;
                 goto exit;
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c
index cf45f723..c1bf0844 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrdev.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c
@@ -40,7 +40,7 @@ static int _pwr_device_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0) {
+                ppmgrdevice->hdr.data.super.obj_mask.super.data[0]) == 0U) {
                 return -EINVAL;
         }
 
@@ -191,7 +191,7 @@ static int devinit_get_pwr_device_table(struct gk20a *g,
 
                 memcpy(&pwr_sensor_table_entry.class_param0,
                         (curr_pwr_device_table_ptr + 1),
-                        (VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 - 1));
+                        (VBIOS_POWER_SENSORS_2X_ENTRY_SIZE_15 - 1U));
 
                 device_type = (u8)BIOS_GET_FIELD(
                         pwr_sensor_table_entry.flags0,
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
index 28074afb..710ae85b 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
@@ -40,7 +40,7 @@ static int _pwr_channel_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0) {
+                ppmgrchannel->hdr.data.super.obj_mask.super.data[0]) == 0U) {
                 return -EINVAL;
         }
 
@@ -67,7 +67,7 @@ static int _pwr_channel_rels_pmudata_instget(struct gk20a *g,
 
         /*check whether pmuboardobjgrp has a valid boardobj in index*/
         if (((u32)BIT(idx) &
-                ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0) {
+                ppmgrchrels->hdr.data.super.obj_mask.super.data[0]) == 0U) {
                 return -EINVAL;
         }
 
@@ -241,7 +241,7 @@ static int devinit_get_pwr_topology_table(struct gk20a *g,
 
                 memcpy(&pwr_topology_table_entry.param0,
                         (curr_pwr_topology_table_ptr + 2),
-                        (VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 - 2));
+                        (VBIOS_POWER_TOPOLOGY_2X_ENTRY_SIZE_16 - 2U));
 
                 class_type = (u8)BIOS_GET_FIELD(
                         pwr_topology_table_entry.flags0,
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
index 82cf0e78..3bf6f328 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
@@ -338,7 +338,7 @@ static struct boardobj *construct_pwr_policy(struct gk20a *g,
                         pwrpolicy,
                         PWR_POLICY_LIMIT_ID_BATT,
                         CTRL_PMGR_PWR_POLICY_LIMIT_INPUT_CLIENT_IDX_RM,
-                        ((pwrpolicyparams->limit_batt != 0) ?
+                        ((pwrpolicyparams->limit_batt != 0U) ?
                                 pwrpolicyparams->limit_batt:
                                 CTRL_PMGR_PWR_POLICY_LIMIT_MAX));
 
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
index 868bc2cb..74f4937d 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.h
@@ -29,7 +29,7 @@
 #include "boardobj/boardobj.h"
 #include "ctrl/ctrlpmgr.h"
 
-#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4
+#define PWR_POLICY_EXT_POWER_STATE_ID_COUNT 0x4U
 
 enum pwr_policy_limit_id {
         PWR_POLICY_LIMIT_ID_MIN    = 0x00000000,