diff options
author | Sam Payne <spayne@nvidia.com> | 2015-04-02 15:27:03 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 22:17:37 -0400 |
commit | c2a7d0304c317195ac1cdbb7e35f46da26120c58 (patch) | |
tree | 8807eaab48c205f7c6e717f6178a1e8e2a231bc7 /drivers/gpu | |
parent | 9974201d610c7f3cc43e34a9db942da0f71917c4 (diff) |
Revert "gpu: nvgpu: zbc: disable activity only ...
This reverts commit 83bc90620f863977101a164780de360bcd0aa088.
bug 1628118
Change-Id: I478f9dd3685b55b4fce18354d475ee0b817a7775
Signed-off-by: Sam Payne <spayne@nvidia.com>
Reviewed-on: http://git-master/r/727152
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 125 |
1 files changed, 87 insertions, 38 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 86a069b2..49b70767 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -3439,7 +3439,26 @@ static void gr_gk20a_detect_sm_arch(struct gk20a *g) | |||
3439 | int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | 3439 | int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, |
3440 | struct zbc_entry *color_val, u32 index) | 3440 | struct zbc_entry *color_val, u32 index) |
3441 | { | 3441 | { |
3442 | struct fifo_gk20a *f = &g->fifo; | ||
3443 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
3442 | u32 i; | 3444 | u32 i; |
3445 | unsigned long end_jiffies = jiffies + | ||
3446 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3447 | u32 ret; | ||
3448 | |||
3449 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3450 | if (ret) { | ||
3451 | gk20a_err(dev_from_gk20a(g), | ||
3452 | "failed to disable gr engine activity\n"); | ||
3453 | return ret; | ||
3454 | } | ||
3455 | |||
3456 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3457 | if (ret) { | ||
3458 | gk20a_err(dev_from_gk20a(g), | ||
3459 | "failed to idle graphics\n"); | ||
3460 | goto clean_up; | ||
3461 | } | ||
3443 | 3462 | ||
3444 | /* update l2 table */ | 3463 | /* update l2 table */ |
3445 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); | 3464 | g->ops.ltc.set_zbc_color_entry(g, color_val, index); |
@@ -3474,12 +3493,39 @@ int gr_gk20a_add_zbc_color(struct gk20a *g, struct gr_gk20a *gr, | |||
3474 | gr->zbc_col_tbl[index].format = color_val->format; | 3493 | gr->zbc_col_tbl[index].format = color_val->format; |
3475 | gr->zbc_col_tbl[index].ref_cnt++; | 3494 | gr->zbc_col_tbl[index].ref_cnt++; |
3476 | 3495 | ||
3477 | return 0; | 3496 | clean_up: |
3497 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
3498 | if (ret) { | ||
3499 | gk20a_err(dev_from_gk20a(g), | ||
3500 | "failed to enable gr engine activity\n"); | ||
3501 | } | ||
3502 | |||
3503 | return ret; | ||
3478 | } | 3504 | } |
3479 | 3505 | ||
3480 | int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | 3506 | int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, |
3481 | struct zbc_entry *depth_val, u32 index) | 3507 | struct zbc_entry *depth_val, u32 index) |
3482 | { | 3508 | { |
3509 | struct fifo_gk20a *f = &g->fifo; | ||
3510 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
3511 | unsigned long end_jiffies = jiffies + | ||
3512 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3513 | u32 ret; | ||
3514 | |||
3515 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3516 | if (ret) { | ||
3517 | gk20a_err(dev_from_gk20a(g), | ||
3518 | "failed to disable gr engine activity\n"); | ||
3519 | return ret; | ||
3520 | } | ||
3521 | |||
3522 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3523 | if (ret) { | ||
3524 | gk20a_err(dev_from_gk20a(g), | ||
3525 | "failed to idle graphics\n"); | ||
3526 | goto clean_up; | ||
3527 | } | ||
3528 | |||
3483 | /* update l2 table */ | 3529 | /* update l2 table */ |
3484 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); | 3530 | g->ops.ltc.set_zbc_depth_entry(g, depth_val, index); |
3485 | 3531 | ||
@@ -3504,12 +3550,50 @@ int gr_gk20a_add_zbc_depth(struct gk20a *g, struct gr_gk20a *gr, | |||
3504 | gr->zbc_dep_tbl[index].format = depth_val->format; | 3550 | gr->zbc_dep_tbl[index].format = depth_val->format; |
3505 | gr->zbc_dep_tbl[index].ref_cnt++; | 3551 | gr->zbc_dep_tbl[index].ref_cnt++; |
3506 | 3552 | ||
3507 | return 0; | 3553 | clean_up: |
3554 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
3555 | if (ret) { | ||
3556 | gk20a_err(dev_from_gk20a(g), | ||
3557 | "failed to enable gr engine activity\n"); | ||
3558 | } | ||
3559 | |||
3560 | return ret; | ||
3508 | } | 3561 | } |
3509 | 3562 | ||
3510 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) | 3563 | void gr_gk20a_pmu_save_zbc(struct gk20a *g, u32 entries) |
3511 | { | 3564 | { |
3565 | struct fifo_gk20a *f = &g->fifo; | ||
3566 | struct fifo_engine_info_gk20a *gr_info = | ||
3567 | f->engine_info + ENGINE_GR_GK20A; | ||
3568 | unsigned long end_jiffies = jiffies + | ||
3569 | msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3570 | u32 ret; | ||
3571 | |||
3572 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3573 | if (ret) { | ||
3574 | gk20a_err(dev_from_gk20a(g), | ||
3575 | "failed to disable gr engine activity\n"); | ||
3576 | return; | ||
3577 | } | ||
3578 | |||
3579 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3580 | if (ret) { | ||
3581 | gk20a_err(dev_from_gk20a(g), | ||
3582 | "failed to idle graphics\n"); | ||
3583 | goto clean_up; | ||
3584 | } | ||
3585 | |||
3586 | /* update zbc */ | ||
3512 | gk20a_pmu_save_zbc(g, entries); | 3587 | gk20a_pmu_save_zbc(g, entries); |
3588 | |||
3589 | clean_up: | ||
3590 | ret = gk20a_fifo_enable_engine_activity(g, gr_info); | ||
3591 | if (ret) { | ||
3592 | gk20a_err(dev_from_gk20a(g), | ||
3593 | "failed to enable gr engine activity\n"); | ||
3594 | } | ||
3595 | |||
3596 | return; | ||
3513 | } | 3597 | } |
3514 | 3598 | ||
3515 | int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, | 3599 | int gr_gk20a_add_zbc(struct gk20a *g, struct gr_gk20a *gr, |
@@ -3759,48 +3843,13 @@ int gr_gk20a_load_zbc_default_table(struct gk20a *g, struct gr_gk20a *gr) | |||
3759 | return 0; | 3843 | return 0; |
3760 | } | 3844 | } |
3761 | 3845 | ||
3762 | static int _gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | ||
3763 | struct zbc_entry *zbc_val) | ||
3764 | { | ||
3765 | struct fifo_gk20a *f = &g->fifo; | ||
3766 | struct fifo_engine_info_gk20a *gr_info = f->engine_info + ENGINE_GR_GK20A; | ||
3767 | unsigned long end_jiffies; | ||
3768 | int ret; | ||
3769 | |||
3770 | ret = gk20a_fifo_disable_engine_activity(g, gr_info, true); | ||
3771 | if (ret) { | ||
3772 | gk20a_err(dev_from_gk20a(g), | ||
3773 | "failed to disable gr engine activity\n"); | ||
3774 | return ret; | ||
3775 | } | ||
3776 | |||
3777 | end_jiffies = jiffies + msecs_to_jiffies(gk20a_get_gr_idle_timeout(g)); | ||
3778 | ret = gr_gk20a_wait_idle(g, end_jiffies, GR_IDLE_CHECK_DEFAULT); | ||
3779 | if (ret) { | ||
3780 | gk20a_err(dev_from_gk20a(g), | ||
3781 | "failed to idle graphics\n"); | ||
3782 | goto clean_up; | ||
3783 | } | ||
3784 | |||
3785 | ret = gr_gk20a_elpg_protected_call(g, | ||
3786 | gr_gk20a_add_zbc(g, gr, zbc_val)); | ||
3787 | |||
3788 | clean_up: | ||
3789 | if (gk20a_fifo_enable_engine_activity(g, gr_info)) { | ||
3790 | gk20a_err(dev_from_gk20a(g), | ||
3791 | "failed to enable gr engine activity\n"); | ||
3792 | } | ||
3793 | |||
3794 | return ret; | ||
3795 | } | ||
3796 | |||
3797 | int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, | 3846 | int gk20a_gr_zbc_set_table(struct gk20a *g, struct gr_gk20a *gr, |
3798 | struct zbc_entry *zbc_val) | 3847 | struct zbc_entry *zbc_val) |
3799 | { | 3848 | { |
3800 | gk20a_dbg_fn(""); | 3849 | gk20a_dbg_fn(""); |
3801 | 3850 | ||
3802 | return gr_gk20a_elpg_protected_call(g, | 3851 | return gr_gk20a_elpg_protected_call(g, |
3803 | _gk20a_gr_zbc_set_table(g, gr, zbc_val)); | 3852 | gr_gk20a_add_zbc(g, gr, zbc_val)); |
3804 | } | 3853 | } |
3805 | 3854 | ||
3806 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) | 3855 | void gr_gk20a_init_blcg_mode(struct gk20a *g, u32 mode, u32 engine) |