diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-06-22 16:39:45 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-06 15:04:41 -0400 |
commit | 99aeb5ae3b5606ffbeb168d25bec4adc541e1236 (patch) | |
tree | 4b6e41556f13ce1c1012ff178aa3ba11b6621fb5 /drivers/gpu | |
parent | 013ead1587b47c296b0328ef076b0ee4628160aa (diff) |
gpu: nvgpu: gv11b: init clear_sm_hww gr ops
Required for multiple SM support and SM register
address changes
JIRA GPUT19X-75
Change-Id: I552bae890a416dc4a430b907641b5b3d09b638c7
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master/r/1514038
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 24 |
1 files changed, 23 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 63107cfc..9da270ac 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1788,7 +1788,8 @@ static int gr_gv11b_pre_process_sm_exception(struct gk20a *g, | |||
1788 | /* reset the HWW errors after locking down */ | 1788 | /* reset the HWW errors after locking down */ |
1789 | global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, | 1789 | global_esr_copy = g->ops.gr.get_sm_hww_global_esr(g, |
1790 | gpc, tpc, sm); | 1790 | gpc, tpc, sm); |
1791 | gk20a_gr_clear_sm_hww(g, gpc, tpc, global_esr_copy); | 1791 | g->ops.gr.clear_sm_hww(g, |
1792 | gpc, tpc, sm, global_esr_copy); | ||
1792 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | 1793 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, |
1793 | "CILP: HWWs cleared for " | 1794 | "CILP: HWWs cleared for " |
1794 | "gpc %d tpc %d sm %d", | 1795 | "gpc %d tpc %d sm %d", |
@@ -3176,6 +3177,26 @@ static int gv11b_gr_lock_down_sm(struct gk20a *g, | |||
3176 | check_errors); | 3177 | check_errors); |
3177 | } | 3178 | } |
3178 | 3179 | ||
3180 | static void gv11b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | ||
3181 | u32 global_esr) | ||
3182 | { | ||
3183 | u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc) + | ||
3184 | gv11b_gr_sm_offset(g, sm); | ||
3185 | |||
3186 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + offset, | ||
3187 | global_esr); | ||
3188 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
3189 | "Cleared HWW global esr, current reg val: 0x%x", | ||
3190 | gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_global_esr_r() + | ||
3191 | offset)); | ||
3192 | |||
3193 | gk20a_writel(g, gr_gpc0_tpc0_sm0_hww_warp_esr_r() + offset, 0); | ||
3194 | gk20a_dbg(gpu_dbg_fn | gpu_dbg_gpu_dbg, | ||
3195 | "Cleared HWW warp esr, current reg val: 0x%x", | ||
3196 | gk20a_readl(g, gr_gpc0_tpc0_sm0_hww_warp_esr_r() + | ||
3197 | offset)); | ||
3198 | } | ||
3199 | |||
3179 | void gv11b_init_gr(struct gpu_ops *gops) | 3200 | void gv11b_init_gr(struct gpu_ops *gops) |
3180 | { | 3201 | { |
3181 | gp10b_init_gr(gops); | 3202 | gp10b_init_gr(gops); |
@@ -3255,4 +3276,5 @@ void gv11b_init_gr(struct gpu_ops *gops) | |||
3255 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask; | 3276 | gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask; |
3256 | gops->gr.lock_down_sm = gv11b_gr_lock_down_sm; | 3277 | gops->gr.lock_down_sm = gv11b_gr_lock_down_sm; |
3257 | gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down; | 3278 | gops->gr.wait_for_sm_lock_down = gv11b_gr_wait_for_sm_lock_down; |
3279 | gops->gr.clear_sm_hww = gv11b_gr_clear_sm_hww; | ||
3258 | } | 3280 | } |