gpu: nvgpu: add hal op to handle post event id

The vserver variant for gr post event id needs different
functionality to send interrupt to VM. Add HAL operation
to allow overriding vserver usecase.

Jira VQRM-2982

Change-Id: I915d089ef751023968c1e8ab181c21afeec997a5
Signed-off-by: Aparna Das <aparnad@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1658382
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

11 files changed, 16 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
index 2c98797d..f9b9c6e6 100644
--- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c
@@ -2229,7 +2229,7 @@ void gk20a_channel_semaphore_wakeup(struct gk20a *g, bool post_events)
                                                 struct tsg_gk20a *tsg =
                                                         &g->fifo.tsg[c->tsgid];
 
-                                                gk20a_tsg_event_id_post_event(tsg,
+                                                g->ops.fifo.post_event_id(tsg,
                                                     NVGPU_EVENT_ID_BLOCKING_SYNC);
                                         }
                                 }
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index d9e3c97d..6f99b3f9 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -610,6 +610,7 @@ struct gpu_ops {
                 void (*deinit_eng_method_buffers)(struct gk20a *g,
                                                 struct tsg_gk20a *tsg);
                 u32 (*get_preempt_timeout)(struct gk20a *g);
+                void (*post_event_id)(struct tsg_gk20a *tsg, int event_id);
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 int (*alloc_syncpt_buf)(struct channel_gk20a *c,
                                 u32 syncpt_id, struct nvgpu_mem *syncpt_buf);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 8f263e67..c64900bd 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -5274,7 +5274,7 @@ static int gk20a_gr_handle_semaphore_pending(struct gk20a *g,
         struct channel_gk20a *ch = &f->channel[isr_data->chid];
         struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
 
-        gk20a_tsg_event_id_post_event(tsg,
+        g->ops.fifo.post_event_id(tsg,
                 NVGPU_EVENT_ID_GR_SEMAPHORE_WRITE_AWAKEN);
 
         nvgpu_cond_broadcast(&ch->semaphore_wq);
@@ -5818,14 +5818,12 @@ static int gk20a_gr_post_bpt_events(struct gk20a *g, struct channel_gk20a *ch,
         if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_int_pending_f()) {
                 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
 
-                gk20a_tsg_event_id_post_event(tsg,
-                        NVGPU_EVENT_ID_BPT_INT);
+                g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_INT);
         }
         if (global_esr & gr_gpc0_tpc0_sm_hww_global_esr_bpt_pause_pending_f()) {
                 struct tsg_gk20a *tsg = &g->fifo.tsg[ch->tsgid];
 
-                gk20a_tsg_event_id_post_event(tsg,
-                        NVGPU_EVENT_ID_BPT_PAUSE);
+                g->ops.fifo.post_event_id(tsg, NVGPU_EVENT_ID_BPT_PAUSE);
         }
 
         return 0;
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 2d53a926..e390e4dd 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -431,6 +431,7 @@ static const struct gpu_ops gm20b_ops = {
                 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
                 .tsg_bind_channel = gk20a_tsg_bind_channel,
                 .tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
+                .post_event_id = gk20a_tsg_event_id_post_event,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
                 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index a0068a6f..82ef0461 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -491,6 +491,7 @@ static const struct gpu_ops gp106_ops = {
                 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
                 .tsg_bind_channel = gk20a_tsg_bind_channel,
                 .tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
+                .post_event_id = gk20a_tsg_event_id_post_event,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
                 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 17685f59..8cbda409 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -1814,8 +1814,8 @@ int gr_gp10b_set_cilp_preempt_pending(struct gk20a *g,
 
         tsg = &g->fifo.tsg[fault_ch->tsgid];
 
-        gk20a_tsg_event_id_post_event(tsg,
-                        NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED);
+        g->ops.fifo.post_event_id(tsg,
+                                NVGPU_EVENT_ID_CILP_PREEMPTION_STARTED);
 
         return 0;
 }
@@ -2036,8 +2036,8 @@ int gr_gp10b_handle_fecs_error(struct gk20a *g,
 
                 tsg = &g->fifo.tsg[ch->tsgid];
 
-                gk20a_tsg_event_id_post_event(tsg,
-                        NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE);
+                g->ops.fifo.post_event_id(tsg,
+                                        NVGPU_EVENT_ID_CILP_PREEMPTION_COMPLETE);
 
                 gk20a_channel_put(ch);
         }
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index 65fdf714..783dfcdd 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -464,6 +464,7 @@ static const struct gpu_ops gp10b_ops = {
                 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
                 .tsg_bind_channel = gk20a_tsg_bind_channel,
                 .tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
+                .post_event_id = gk20a_tsg_event_id_post_event,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
                 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 6598d7f6..677f2a89 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -506,6 +506,7 @@ static const struct gpu_ops gv100_ops = {
                         gv11b_fifo_deinit_eng_method_buffers,
                 .tsg_bind_channel = gk20a_tsg_bind_channel,
                 .tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
+                .post_event_id = gk20a_tsg_event_id_post_event,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
                 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 700dc7fc..d55d51ba 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -522,6 +522,7 @@ static const struct gpu_ops gv11b_ops = {
                         gv11b_fifo_deinit_eng_method_buffers,
                 .tsg_bind_channel = gk20a_tsg_bind_channel,
                 .tsg_unbind_channel = gk20a_fifo_tsg_unbind_channel,
+                .post_event_id = gk20a_tsg_event_id_post_event,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = gv11b_fifo_alloc_syncpt_buf,
                 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index f1ced1c8..bfdd0788 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -340,6 +340,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1,
                 .tsg_bind_channel = vgpu_tsg_bind_channel,
                 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
+                .post_event_id = gk20a_tsg_event_id_post_event,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf,
                 .free_syncpt_buf = gk20a_fifo_free_syncpt_buf,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 76f7b389..b4e03ecd 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -383,6 +383,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                         gv11b_fifo_deinit_eng_method_buffers,
                 .tsg_bind_channel = vgpu_gv11b_tsg_bind_channel,
                 .tsg_unbind_channel = vgpu_tsg_unbind_channel,
+                .post_event_id = gk20a_tsg_event_id_post_event,
 #ifdef CONFIG_TEGRA_GK20A_NVHOST
                 .alloc_syncpt_buf = vgpu_gv11b_fifo_alloc_syncpt_buf,
                 .free_syncpt_buf = gv11b_fifo_free_syncpt_buf,