gpu: nvgpu: Move ltc HAL to common

Move implementation of ltc HAL to common/ltc.

JIRA NVGPU-956

Change-Id: Id78d74e8612d7dacfb8d322d491abecd798e42b5
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1798461
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

23 files changed, 182 insertions, 172 deletions

diff --git a/drivers/gpu/nvgpu/Makefile b/drivers/gpu/nvgpu/Makefile
index 7a21d294..9da20802 100644
--- a/drivers/gpu/nvgpu/Makefile
+++ b/drivers/gpu/nvgpu/Makefile
@@ -185,7 +185,10 @@ nvgpu-y += \
         common/pmu/pmu_pg.o \
         common/pmu/pmu_perfmon.o \
         common/pmu/pmu_debug.o \
-        common/ltc.o \
+        common/ltc/ltc.o \
+        common/ltc/ltc_gm20b.o \
+        common/ltc/ltc_gp10b.o \
+        common/ltc/ltc_gv11b.o  \
         common/io_common.o \
         common/clock_gating/gm20b_gating_reglist.o \
         common/clock_gating/gp106_gating_reglist.o \
@@ -216,7 +219,6 @@ nvgpu-y += \
         gk20a/fecs_trace_gk20a.o \
         gk20a/mc_gk20a.o \
         gm20b/hal_gm20b.o \
-        gm20b/ltc_gm20b.o \
         gm20b/gr_gm20b.o \
         gm20b/clk_gm20b.o \
         gm20b/fifo_gm20b.o \
@@ -267,7 +269,6 @@ nvgpu-y += \
         gp10b/ce_gp10b.o \
         gp10b/mc_gp10b.o  \
         gp10b/fifo_gp10b.o  \
-        gp10b/ltc_gp10b.o \
         gp10b/mm_gp10b.o \
         gp10b/pmu_gp10b.o \
         gp10b/hal_gp10b.o \
@@ -293,7 +294,6 @@ nvgpu-y += \
         gv11b/css_gr_gv11b.o  \
         gv11b/dbg_gpu_gv11b.o  \
         gv11b/mc_gv11b.o  \
-        gv11b/ltc_gv11b.o  \
         gv11b/hal_gv11b.o \
         gv11b/gr_gv11b.o \
         gv11b/fifo_gv11b.o \
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
index e4080013..2d7efd98 100644
--- a/drivers/gpu/nvgpu/Makefile.sources
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -55,7 +55,10 @@ srcs :=	common/mm/nvgpu_allocator.c \
         common/semaphore.c \
         common/as.c \
         common/rbtree.c \
-        common/ltc.c \
+        common/ltc/ltc.c \
+        common/ltc/ltc_gm20b.c \
+        common/ltc/ltc_gp10b.c \
+        common/ltc/ltc_gv11b.c  \
         common/io_common.c \
         common/ecc.c \
         common/ce2.c \
@@ -149,7 +152,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gk20a/tsg_gk20a.c \
         gk20a/mc_gk20a.c \
         gm20b/hal_gm20b.c \
-        gm20b/ltc_gm20b.c \
         gm20b/gr_gm20b.c \
         gm20b/clk_gm20b.c \
         gm20b/fifo_gm20b.c \
@@ -164,7 +166,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gp10b/ce_gp10b.c \
         gp10b/mc_gp10b.c  \
         gp10b/fifo_gp10b.c  \
-        gp10b/ltc_gp10b.c \
         gp10b/mm_gp10b.c \
         gp10b/pmu_gp10b.c \
         gp10b/hal_gp10b.c \
@@ -176,7 +177,6 @@ srcs :=	common/mm/nvgpu_allocator.c \
         gv11b/gv11b.c  \
         gv11b/dbg_gpu_gv11b.c  \
         gv11b/mc_gv11b.c  \
-        gv11b/ltc_gv11b.c  \
         gv11b/hal_gv11b.c \
         gv11b/gr_gv11b.c \
         gv11b/fifo_gv11b.c \
diff --git a/drivers/gpu/nvgpu/common/ltc.c b/drivers/gpu/nvgpu/common/ltc/ltc.c
index 1beb1974..1beb1974 100644
--- a/drivers/gpu/nvgpu/common/ltc.c
+++ b/drivers/gpu/nvgpu/common/ltc/ltc.c
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c
index 65945fad..28d63e82 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.c
@@ -487,3 +487,86 @@ void gm20b_ltc_set_enabled(struct gk20a *g, bool enabled)
 
         gk20a_writel(g, ltc_ltcs_ltss_tstg_set_mgmt_2_r(), reg);
 }
+
+/*
+ * LTC pri addressing
+ */
+bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr)
+{
+        return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v()));
+}
+
+bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
+{
+        u32 ltc_shared_base = ltc_ltcs_ltss_v();
+        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+        return (addr >= ltc_shared_base) &&
+                (addr < (ltc_shared_base + lts_stride));
+}
+
+bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr)
+{
+        u32 lts_shared_base = ltc_ltc0_ltss_v();
+        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+        u32 addr_mask = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) - 1;
+        u32 base_offset = lts_shared_base & addr_mask;
+        u32 end_offset = base_offset + lts_stride;
+
+        return (!gm20b_ltc_is_ltcs_ltss_addr(g, addr)) &&
+                ((addr & addr_mask) >= base_offset) &&
+                ((addr & addr_mask) < end_offset);
+}
+
+static void gm20b_ltc_update_ltc_lts_addr(struct gk20a *g, u32 addr, u32 ltc_num,
+                                        u32 *priv_addr_table,
+                                        u32 *priv_addr_table_index)
+{
+        u32 num_ltc_slices = g->ops.gr.get_max_lts_per_ltc(g);
+        u32 index = *priv_addr_table_index;
+        u32 lts_num;
+        u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
+
+        for (lts_num = 0; lts_num < num_ltc_slices; lts_num++) {
+                priv_addr_table[index++] = ltc_ltc0_lts0_v() +
+                                                ltc_num * ltc_stride +
+                                                lts_num * lts_stride +
+                                                (addr & (lts_stride - 1));
+        }
+
+        *priv_addr_table_index = index;
+}
+
+void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
+                                        u32 *priv_addr_table,
+                                        u32 *priv_addr_table_index)
+{
+        u32 num_ltc = g->ltc_count;
+        u32 i, start, ltc_num = 0;
+        u32 pltcg_base = ltc_pltcg_base_v();
+        u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
+
+        for (i = 0; i < num_ltc; i++) {
+                start = pltcg_base + i * ltc_stride;
+                if ((addr >= start) && (addr < (start + ltc_stride))) {
+                        ltc_num = i;
+                        break;
+                }
+        }
+        gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num, priv_addr_table,
+                                priv_addr_table_index);
+}
+
+void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
+                                        u32 *priv_addr_table,
+                                        u32 *priv_addr_table_index)
+{
+        u32 num_ltc = g->ltc_count;
+        u32 ltc_num;
+
+        for (ltc_num = 0; ltc_num < num_ltc; ltc_num++) {
+                gm20b_ltc_update_ltc_lts_addr(g, addr, ltc_num,
+                                        priv_addr_table, priv_addr_table_index);
+        }
+}
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h
index 0f9145be..cc92c70a 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.h
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gm20b.h
@@ -22,9 +22,16 @@
  * DEALINGS IN THE SOFTWARE.
  */
 
-#ifndef _NVHOST_GM20B_LTC
-#define _NVHOST_GM20B_LTC
+#ifndef NVGPU_LTC_GM20B
+#define NVGPU_LTC_GM20B
+
+#include <nvgpu/types.h>
+
+struct gk20a;
+struct gr_gk20a;
 struct gpu_ops;
+struct zbc_entry;
+enum gk20a_cbc_op;
 
 int gm20b_ltc_init_comptags(struct gk20a *g, struct gr_gk20a *gr);
 int gm20b_determine_L2_size_bytes(struct gk20a *g);
@@ -46,4 +53,14 @@ int gm20b_ltc_alloc_phys_cbc(struct gk20a *g,
                              size_t compbit_backing_size);
 int gm20b_ltc_alloc_virt_cbc(struct gk20a *g,
                              size_t compbit_backing_size);
+bool gm20b_ltc_pri_is_ltc_addr(struct gk20a *g, u32 addr);
+bool gm20b_ltc_is_ltcs_ltss_addr(struct gk20a *g, u32 addr);
+bool gm20b_ltc_is_ltcn_ltss_addr(struct gk20a *g, u32 addr);
+void gm20b_ltc_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
+                                        u32 *priv_addr_table,
+                                        u32 *priv_addr_table_index);
+void gm20b_ltc_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
+                                        u32 *priv_addr_table,
+                                        u32 *priv_addr_table_index);
+
 #endif
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c
index 79ebe86d..eb262add 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.c
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.c
@@ -33,8 +33,8 @@
 #include <nvgpu/hw/gp10b/hw_ltc_gp10b.h>
 
 #include "gk20a/gk20a.h"
-#include "gm20b/ltc_gm20b.h"
 
+#include "ltc_gm20b.h"
 #include "ltc_gp10b.h"
 
 int gp10b_determine_L2_size_bytes(struct gk20a *g)
diff --git a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.h
index c1a2bf64..c1a2bf64 100644
--- a/drivers/gpu/nvgpu/gp10b/ltc_gp10b.h
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gp10b.h
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c
index d7c385a9..98306079 100644
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.c
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.c
@@ -24,8 +24,8 @@
 
 #include <nvgpu/io.h>
 #include "gk20a/gk20a.h"
-#include "gp10b/ltc_gp10b.h"
 
+#include "ltc_gp10b.h"
 #include "ltc_gv11b.h"
 
 #include <nvgpu/hw/gv11b/hw_ltc_gv11b.h>
diff --git a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h
index 9d33b9fb..9d33b9fb 100644
--- a/drivers/gpu/nvgpu/gv11b/ltc_gv11b.h
+++ b/drivers/gpu/nvgpu/common/ltc/ltc_gv11b.h
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 5bb91f62..f802cd56 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -194,6 +194,15 @@ struct gpu_ops {
                 u32 (*cbc_fix_config)(struct gk20a *g, int base);
                 void (*flush)(struct gk20a *g);
                 void (*intr_en_illegal_compstat)(struct gk20a *g, bool enable);
+                bool (*pri_is_ltc_addr)(struct gk20a *g, u32 addr);
+                bool (*is_ltcs_ltss_addr)(struct gk20a *g, u32 addr);
+                bool (*is_ltcn_ltss_addr)(struct gk20a *g, u32 addr);
+                void (*split_lts_broadcast_addr)(struct gk20a *g, u32 addr,
+                                                        u32 *priv_addr_table,
+                                                        u32 *priv_addr_table_index);
+                void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr,
+                                                        u32 *priv_addr_table,
+                                                        u32 *priv_addr_table_index);
         } ltc;
         struct {
                 void (*isr_stall)(struct gk20a *g, u32 inst_id, u32 pri_base);
@@ -274,15 +283,6 @@ struct gpu_ops {
                                 u32 *gpc_num, u32 *tpc_num);
                 u32 (*get_tpc_num)(struct gk20a *g, u32 addr);
                 u32 (*get_egpc_base)(struct gk20a *g);
-                bool (*is_ltcs_ltss_addr)(struct gk20a *g, u32 addr);
-                bool (*is_ltcn_ltss_addr)(struct gk20a *g, u32 addr);
-                bool (*get_lts_in_ltc_shared_base)(void);
-                void (*split_lts_broadcast_addr)(struct gk20a *g, u32 addr,
-                                        u32 *priv_addr_table,
-                                        u32 *priv_addr_table_index);
-                void (*split_ltc_broadcast_addr)(struct gk20a *g, u32 addr,
-                                        u32 *priv_addr_table,
-                                        u32 *priv_addr_table_index);
                 void (*detect_sm_arch)(struct gk20a *g);
                 int (*add_zbc_color)(struct gk20a *g, struct gr_gk20a *gr,
                                   struct zbc_entry *color_val, u32 index);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index bb54e00e..fbba02ca 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -59,7 +59,6 @@
 #include <nvgpu/hw/gk20a/hw_ram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pri_ringmaster_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_pbdma_gk20a.h>
 
@@ -6256,11 +6255,11 @@ int gr_gk20a_decode_priv_addr(struct gk20a *g, u32 addr,
                 }
                 *be_num = pri_get_be_num(g, addr);
                 return 0;
-        } else if (pri_is_ltc_addr(addr)) {
+        } else if (g->ops.ltc.pri_is_ltc_addr(g, addr)) {
                 *addr_type = CTXSW_ADDR_TYPE_LTCS;
-                if (g->ops.gr.is_ltcs_ltss_addr(g, addr))
+                if (g->ops.ltc.is_ltcs_ltss_addr(g, addr))
                         *broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS;
-                else if (g->ops.gr.is_ltcn_ltss_addr(g, addr))
+                else if (g->ops.ltc.is_ltcn_ltss_addr(g, addr))
                         *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS;
                 return 0;
         } else if (pri_is_fbpa_addr(g, addr)) {
@@ -6398,10 +6397,10 @@ int gr_gk20a_create_priv_addr_table(struct gk20a *g,
                 g->ops.gr.egpc_etpc_priv_addr_table(g, addr, gpc_num, tpc_num,
                                 broadcast_flags, priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTSS) {
-                g->ops.gr.split_lts_broadcast_addr(g, addr,
+                g->ops.ltc.split_lts_broadcast_addr(g, addr,
                                                         priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTCS) {
-                g->ops.gr.split_ltc_broadcast_addr(g, addr,
+                g->ops.ltc.split_ltc_broadcast_addr(g, addr,
                                                         priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_FBPA) {
                 g->ops.gr.split_fbpa_broadcast_addr(g, addr,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
index af390833..32a30d78 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_pri_gk20a.h
@@ -29,8 +29,6 @@
  * of the context state store for gr/compute contexts.
  */
 
-#include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
-
 /*
  * GPC pri addressing
  */
@@ -227,14 +225,6 @@ static inline u32 pri_ppc_addr(struct gk20a *g, u32 addr, u32 gpc, u32 ppc)
                 ppc_in_gpc_base + (ppc * ppc_in_gpc_stride) + addr;
 }
 
-/*
- * LTC pri addressing
- */
-static inline bool pri_is_ltc_addr(u32 addr)
-{
-        return ((addr >= ltc_pltcg_base_v()) && (addr < ltc_pltcg_extent_v()));
-}
-
 enum ctxsw_addr_type {
         CTXSW_ADDR_TYPE_SYS  = 0,
         CTXSW_ADDR_TYPE_GPC  = 1,
diff --git a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
index 5bba5d9c..ee63489e 100644
--- a/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mm_gk20a.c
@@ -52,7 +52,6 @@
 #include <nvgpu/hw/gk20a/hw_pram_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_flush_gk20a.h>
-#include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 
 /*
  * GPU mapping life cycle
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 49b81783..abc39362 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -39,7 +39,6 @@
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_top_gm20b.h>
-#include <nvgpu/hw/gm20b/hw_ltc_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_perf_gm20b.h>
@@ -1438,81 +1437,6 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
         return 0;
 }
 
-bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
-{
-        u32 ltc_shared_base = ltc_ltcs_ltss_v();
-        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
-
-        return (addr >= ltc_shared_base) &&
-                (addr < (ltc_shared_base + lts_stride));
-}
-
-bool gr_gm20b_is_ltcn_ltss_addr(struct gk20a *g, u32 addr)
-{
-        u32 lts_shared_base = ltc_ltc0_ltss_v();
-        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
-        u32 addr_mask = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE) - 1;
-        u32 base_offset = lts_shared_base & addr_mask;
-        u32 end_offset = base_offset + lts_stride;
-
-        return (!gr_gm20b_is_ltcs_ltss_addr(g, addr)) &&
-                ((addr & addr_mask) >= base_offset) &&
-                ((addr & addr_mask) < end_offset);
-}
-
-static void gr_gm20b_update_ltc_lts_addr(struct gk20a *g, u32 addr, u32 ltc_num,
-                                        u32 *priv_addr_table,
-                                        u32 *priv_addr_table_index)
-{
-        u32 num_ltc_slices = g->ops.gr.get_max_lts_per_ltc(g);
-        u32 index = *priv_addr_table_index;
-        u32 lts_num;
-        u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
-        u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
-
-        for (lts_num = 0; lts_num < num_ltc_slices; lts_num++) {
-                priv_addr_table[index++] = ltc_ltc0_lts0_v() +
-                                                ltc_num * ltc_stride +
-                                                lts_num * lts_stride +
-                                                (addr & (lts_stride - 1));
-        }
-
-        *priv_addr_table_index = index;
-}
-
-void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
-                                        u32 *priv_addr_table,
-                                        u32 *priv_addr_table_index)
-{
-        u32 num_ltc = g->ltc_count;
-        u32 i, start, ltc_num = 0;
-        u32 pltcg_base = ltc_pltcg_base_v();
-        u32 ltc_stride = nvgpu_get_litter_value(g, GPU_LIT_LTC_STRIDE);
-
-        for (i = 0; i < num_ltc; i++) {
-                start = pltcg_base + i * ltc_stride;
-                if ((addr >= start) && (addr < (start + ltc_stride))) {
-                        ltc_num = i;
-                        break;
-                }
-        }
-        gr_gm20b_update_ltc_lts_addr(g, addr, ltc_num, priv_addr_table,
-                                priv_addr_table_index);
-}
-
-void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
-                                        u32 *priv_addr_table,
-                                        u32 *priv_addr_table_index)
-{
-        u32 num_ltc = g->ltc_count;
-        u32 ltc_num;
-
-        for (ltc_num = 0; ltc_num < num_ltc; ltc_num++) {
-                gr_gm20b_update_ltc_lts_addr(g, addr, ltc_num,
-                                        priv_addr_table, priv_addr_table_index);
-        }
-}
-
 void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
                         u32 global_esr)
 {
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 5c82fd65..9d8e5cdf 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -124,14 +124,6 @@ int gm20b_gr_clear_sm_error_state(struct gk20a *g,
                 struct channel_gk20a *ch, u32 sm_id);
 int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
                 struct nvgpu_preemption_modes_rec *preemption_modes_rec);
-bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr);
-bool gr_gm20b_is_ltcn_ltss_addr(struct gk20a *g, u32 addr);
-void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
-                                        u32 *priv_addr_table,
-                                        u32 *priv_addr_table_index);
-void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
-                                        u32 *priv_addr_table,
-                                        u32 *priv_addr_table_index);
 void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
                         u32 global_esr);
 u32 gr_gm20b_get_pmm_per_chiplet_offset(void);
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 05acc0cf..3b164f9c 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -31,6 +31,7 @@
 #include "common/fb/fb_gm20b.h"
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gm20b.h"
+#include "common/ltc/ltc_gm20b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/ce2_gk20a.h"
@@ -45,9 +46,7 @@
 #include "gk20a/gr_gk20a.h"
 #include "gk20a/tsg_gk20a.h"
 
-#include "ltc_gm20b.h"
 #include "gr_gm20b.h"
-#include "ltc_gm20b.h"
 #include "fifo_gm20b.h"
 #include "gr_ctx_gm20b.h"
 #include "mm_gm20b.h"
@@ -200,6 +199,11 @@ static const struct gpu_ops gm20b_ops = {
                 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
                 .flush = gm20b_flush_ltc,
                 .set_enabled = gm20b_ltc_set_enabled,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gk20a_ce2_isr,
@@ -281,10 +285,6 @@ static const struct gpu_ops gm20b_ops = {
                 .init_sm_id_table = gr_gk20a_init_sm_id_table,
                 .load_smid_config = gr_gm20b_load_smid_config,
                 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
                 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
                 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index 02a2f0a6..1c5e1800 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -36,6 +36,8 @@
 #include "common/xve/xve_gp106.h"
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gp106.h"
+#include "common/ltc/ltc_gm20b.h"
+#include "common/ltc/ltc_gp10b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -49,7 +51,6 @@
 #include "gk20a/pmu_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
-#include "gp10b/ltc_gp10b.h"
 #include "gp10b/gr_gp10b.h"
 #include "gp10b/fecs_trace_gp10b.h"
 #include "gp10b/mc_gp10b.h"
@@ -64,7 +65,6 @@
 #include "gp106/fifo_gp106.h"
 #include "gp106/regops_gp106.h"
 
-#include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/mm_gm20b.h"
@@ -256,6 +256,11 @@ static const struct gpu_ops gp106_ops = {
                 .cbc_fix_config = NULL,
                 .flush = gm20b_flush_ltc,
                 .set_enabled = gp10b_ltc_set_enabled,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gp10b_ce_isr,
@@ -340,10 +345,6 @@ static const struct gpu_ops gp106_ops = {
                 .init_sm_id_table = gr_gk20a_init_sm_id_table,
                 .load_smid_config = gr_gp10b_load_smid_config,
                 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
                 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
                 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index cfbdc6ce..b9d8c81a 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -34,6 +34,8 @@
 #include "common/fb/fb_gp10b.h"
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gp10b.h"
+#include "common/ltc/ltc_gm20b.h"
+#include "common/ltc/ltc_gp10b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -51,7 +53,6 @@
 #include "gp10b/gr_gp10b.h"
 #include "gp10b/fecs_trace_gp10b.h"
 #include "gp10b/mc_gp10b.h"
-#include "gp10b/ltc_gp10b.h"
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/pmu_gp10b.h"
@@ -60,7 +61,6 @@
 #include "gp10b/regops_gp10b.h"
 #include "gp10b/ecc_gp10b.h"
 
-#include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/acr_gm20b.h"
@@ -214,6 +214,11 @@ static const struct gpu_ops gp10b_ops = {
                 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
                 .flush = gm20b_flush_ltc,
                 .set_enabled = gp10b_ltc_set_enabled,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gp10b_ce_isr,
@@ -299,10 +304,6 @@ static const struct gpu_ops gp10b_ops = {
                 .init_sm_id_table = gr_gk20a_init_sm_id_table,
                 .load_smid_config = gr_gp10b_load_smid_config,
                 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
                 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
                 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 7926c35c..6904313b 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -39,6 +39,9 @@
 #include "common/therm/therm_gp106.h"
 #include "common/therm/therm_gp10b.h"
 #include "common/therm/therm_gv11b.h"
+#include "common/ltc/ltc_gm20b.h"
+#include "common/ltc/ltc_gp10b.h"
+#include "common/ltc/ltc_gv11b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -52,7 +55,6 @@
 #include "gk20a/pmu_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
-#include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/mm_gm20b.h"
@@ -69,7 +71,6 @@
 #include "gp106/flcn_gp106.h"
 
 #include "gp10b/gr_gp10b.h"
-#include "gp10b/ltc_gp10b.h"
 #include "gp10b/mc_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
@@ -83,7 +84,6 @@
 #include "gv11b/hal_gv11b.h"
 #include "gv11b/gr_gv11b.h"
 #include "gv11b/mc_gv11b.h"
-#include "gv11b/ltc_gv11b.h"
 #include "gv11b/gv11b.h"
 #include "gv11b/ce_gv11b.h"
 #include "gv11b/mm_gv11b.h"
@@ -288,6 +288,11 @@ static const struct gpu_ops gv100_ops = {
                 .flush = gm20b_flush_ltc,
                 .set_enabled = gp10b_ltc_set_enabled,
                 .intr_en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gv11b_ce_isr,
@@ -377,10 +382,6 @@ static const struct gpu_ops gv100_ops = {
                 .init_sm_id_table = gr_gv100_init_sm_id_table,
                 .load_smid_config = gr_gv11b_load_smid_config,
                 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
                 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
                 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
index c2cf909a..41d2f695 100644
--- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c
@@ -4716,11 +4716,11 @@ int gr_gv11b_decode_priv_addr(struct gk20a *g, u32 addr,
                 }
                 *be_num = pri_get_be_num(g, addr);
                 return 0;
-        } else if (pri_is_ltc_addr(addr)) {
+        } else if (g->ops.ltc.pri_is_ltc_addr(g, addr)) {
                 *addr_type = CTXSW_ADDR_TYPE_LTCS;
-                if (g->ops.gr.is_ltcs_ltss_addr(g, addr))
+                if (g->ops.ltc.is_ltcs_ltss_addr(g, addr))
                         *broadcast_flags |= PRI_BROADCAST_FLAGS_LTCS;
-                else if (g->ops.gr.is_ltcn_ltss_addr(g, addr))
+                else if (g->ops.ltc.is_ltcn_ltss_addr(g, addr))
                         *broadcast_flags |= PRI_BROADCAST_FLAGS_LTSS;
                 return 0;
         } else if (pri_is_fbpa_addr(g, addr)) {
@@ -4928,10 +4928,10 @@ int gr_gv11b_create_priv_addr_table(struct gk20a *g,
                 g->ops.gr.egpc_etpc_priv_addr_table(g, addr, gpc_num, tpc_num,
                                 broadcast_flags, priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTSS) {
-                g->ops.gr.split_lts_broadcast_addr(g, addr,
+                g->ops.ltc.split_lts_broadcast_addr(g, addr,
                                                         priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_LTCS) {
-                g->ops.gr.split_ltc_broadcast_addr(g, addr,
+                g->ops.ltc.split_ltc_broadcast_addr(g, addr,
                                                         priv_addr_table, &t);
         } else if (broadcast_flags & PRI_BROADCAST_FLAGS_FBPA) {
                 g->ops.gr.split_fbpa_broadcast_addr(g, addr,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 111a1ea2..3772649e 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -36,6 +36,9 @@
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gp10b.h"
 #include "common/therm/therm_gv11b.h"
+#include "common/ltc/ltc_gm20b.h"
+#include "common/ltc/ltc_gp10b.h"
+#include "common/ltc/ltc_gv11b.h"
 
 #include "gk20a/gk20a.h"
 #include "gk20a/fifo_gk20a.h"
@@ -49,14 +52,12 @@
 #include "gk20a/pmu_gk20a.h"
 #include "gk20a/gr_gk20a.h"
 
-#include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/mm_gm20b.h"
 #include "gm20b/acr_gm20b.h"
 #include "gm20b/pmu_gm20b.h"
 
-#include "gp10b/ltc_gp10b.h"
 #include "gp10b/mc_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/fifo_gp10b.h"
@@ -76,7 +77,6 @@
 #include "css_gr_gv11b.h"
 #include "gr_gv11b.h"
 #include "mc_gv11b.h"
-#include "ltc_gv11b.h"
 #include "gv11b.h"
 #include "ce_gv11b.h"
 #include "gr_ctx_gv11b.h"
@@ -245,6 +245,11 @@ static const struct gpu_ops gv11b_ops = {
                 .flush = gm20b_flush_ltc,
                 .set_enabled = gp10b_ltc_set_enabled,
                 .intr_en_illegal_compstat = gv11b_ltc_intr_en_illegal_compstat,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gv11b_ce_isr,
@@ -332,10 +337,6 @@ static const struct gpu_ops gv11b_ops = {
                 .init_sm_id_table = gr_gv100_init_sm_id_table,
                 .load_smid_config = gr_gv11b_load_smid_config,
                 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
                 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
                 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index aadd17d6..a4ad64a8 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -30,6 +30,8 @@
 #include "common/fb/fb_gp10b.h"
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gp10b.h"
+#include "common/ltc/ltc_gm20b.h"
+#include "common/ltc/ltc_gp10b.h"
 
 #include "vgpu/fifo_vgpu.h"
 #include "vgpu/gr_vgpu.h"
@@ -50,7 +52,6 @@
 #include "gk20a/dbg_gpu_gk20a.h"
 
 #include "gp10b/mc_gp10b.h"
-#include "gp10b/ltc_gp10b.h"
 #include "gp10b/mm_gp10b.h"
 #include "gp10b/ce_gp10b.h"
 #include "gp10b/pmu_gp10b.h"
@@ -60,7 +61,6 @@
 #include "gp10b/regops_gp10b.h"
 #include "gp10b/fuse_gp10b.h"
 
-#include "gm20b/ltc_gm20b.h"
 #include "gm20b/gr_gm20b.h"
 #include "gm20b/fifo_gm20b.h"
 #include "gm20b/acr_gm20b.h"
@@ -91,6 +91,11 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .cbc_fix_config = gm20b_ltc_cbc_fix_config,
                 .flush = gm20b_flush_ltc,
                 .set_enabled = NULL,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gp10b_ce_isr,
@@ -173,10 +178,6 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                 .init_sm_id_table = vgpu_gr_init_sm_id_table,
                 .load_smid_config = gr_gp10b_load_smid_config,
                 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
                 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
                 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index e2410e4e..a02c47f2 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -32,6 +32,9 @@
 #include "common/therm/therm_gm20b.h"
 #include "common/therm/therm_gp10b.h"
 #include "common/therm/therm_gv11b.h"
+#include "common/ltc/ltc_gm20b.h"
+#include "common/ltc/ltc_gp10b.h"
+#include "common/ltc/ltc_gv11b.h"
 
 #include <gk20a/gk20a.h>
 #include <gv11b/hal_gv11b.h>
@@ -58,7 +61,6 @@
 #include <gm20b/pmu_gm20b.h>
 #include <gm20b/mm_gm20b.h>
 #include <gm20b/acr_gm20b.h>
-#include <gm20b/ltc_gm20b.h>
 
 #include <gp10b/pmu_gp10b.h>
 #include <gp10b/mm_gp10b.h>
@@ -66,7 +68,6 @@
 #include <gp10b/ce_gp10b.h>
 #include "gp10b/gr_gp10b.h"
 #include <gp10b/fifo_gp10b.h>
-#include <gp10b/ltc_gp10b.h>
 #include <gp10b/fuse_gp10b.h>
 
 #include <gp106/pmu_gp106.h>
@@ -80,7 +81,6 @@
 #include <gv11b/fifo_gv11b.h>
 #include <gv11b/regops_gv11b.h>
 #include <gv11b/gr_ctx_gv11b.h>
-#include <gv11b/ltc_gv11b.h>
 #include <gv11b/gr_gv11b.h>
 
 #include <nvgpu/enabled.h>
@@ -110,6 +110,11 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .isr = gv11b_ltc_isr,
                 .flush = gm20b_flush_ltc,
                 .set_enabled = NULL,
+                .pri_is_ltc_addr = gm20b_ltc_pri_is_ltc_addr,
+                .is_ltcs_ltss_addr = gm20b_ltc_is_ltcs_ltss_addr,
+                .is_ltcn_ltss_addr = gm20b_ltc_is_ltcn_ltss_addr,
+                .split_lts_broadcast_addr = gm20b_ltc_split_lts_broadcast_addr,
+                .split_ltc_broadcast_addr = gm20b_ltc_split_ltc_broadcast_addr,
         },
         .ce2 = {
                 .isr_stall = gv11b_ce_isr,
@@ -191,10 +196,6 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                 .init_sm_id_table = vgpu_gr_init_sm_id_table,
                 .load_smid_config = gr_gv11b_load_smid_config,
                 .program_sm_id_numbering = gr_gv11b_program_sm_id_numbering,
-                .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
-                .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
-                .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
-                .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
                 .setup_rop_mapping = gr_gv11b_setup_rop_mapping,
                 .program_zcull_mapping = gr_gv11b_program_zcull_mapping,
                 .commit_global_timeslice = gr_gv11b_commit_global_timeslice,