diff options
author | Richard Zhao <rizhao@nvidia.com> | 2016-01-14 20:40:48 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-01-25 18:22:22 -0500 |
commit | 8fb33d92b03b9ee2db421c69252822d09477cce5 (patch) | |
tree | ca3708bc20bb13a743a50a0a5660f42e487dea9f /drivers/gpu | |
parent | 42b0f49d42eeadffc221bd4d9990010dfebd4a10 (diff) |
gpu: nvgpu: vgpu: add channel_set_priority support
- add gops.fifo.channel_set_priority and move current code
as native callback.
- implement the callback for vgpu
Bug 1701079
Change-Id: If1cd13ea4478d11d578da2f682598e0c4522bcaf
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: http://git-master/r/932829
Reviewed-by: Aingara Paramakuru <aparamakuru@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/channel_gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | 32 |
5 files changed, 37 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c index 45501d4f..5e5bbcb0 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.c | |||
@@ -2539,8 +2539,7 @@ unsigned int gk20a_channel_poll(struct file *filep, poll_table *wait) | |||
2539 | return mask; | 2539 | return mask; |
2540 | } | 2540 | } |
2541 | 2541 | ||
2542 | static int gk20a_channel_set_priority(struct channel_gk20a *ch, | 2542 | int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority) |
2543 | u32 priority) | ||
2544 | { | 2543 | { |
2545 | u32 timeslice_timeout; | 2544 | u32 timeslice_timeout; |
2546 | bool interleave = false; | 2545 | bool interleave = false; |
@@ -2723,6 +2722,7 @@ void gk20a_init_channel(struct gpu_ops *gops) | |||
2723 | gops->fifo.alloc_inst = channel_gk20a_alloc_inst; | 2722 | gops->fifo.alloc_inst = channel_gk20a_alloc_inst; |
2724 | gops->fifo.free_inst = channel_gk20a_free_inst; | 2723 | gops->fifo.free_inst = channel_gk20a_free_inst; |
2725 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; | 2724 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; |
2725 | gops->fifo.channel_set_priority = gk20a_channel_set_priority; | ||
2726 | } | 2726 | } |
2727 | 2727 | ||
2728 | long gk20a_channel_ioctl(struct file *filp, | 2728 | long gk20a_channel_ioctl(struct file *filp, |
@@ -2897,7 +2897,7 @@ long gk20a_channel_ioctl(struct file *filp, | |||
2897 | __func__, cmd); | 2897 | __func__, cmd); |
2898 | break; | 2898 | break; |
2899 | } | 2899 | } |
2900 | err = gk20a_channel_set_priority(ch, | 2900 | err = ch->g->ops.fifo.channel_set_priority(ch, |
2901 | ((struct nvgpu_set_priority_args *)buf)->priority); | 2901 | ((struct nvgpu_set_priority_args *)buf)->priority); |
2902 | gk20a_idle(dev); | 2902 | gk20a_idle(dev); |
2903 | break; | 2903 | break; |
diff --git a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h index 24a2fe11..0f796ffe 100644 --- a/drivers/gpu/nvgpu/gk20a/channel_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/channel_gk20a.h | |||
@@ -268,5 +268,6 @@ void gk20a_channel_timeout_restart_all_channels(struct gk20a *g); | |||
268 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, | 268 | int gk20a_channel_get_timescale_from_timeslice(struct gk20a *g, |
269 | int timeslice_period, | 269 | int timeslice_period, |
270 | int *__timeslice_timeout, int *__timeslice_scale); | 270 | int *__timeslice_timeout, int *__timeslice_scale); |
271 | int gk20a_channel_set_priority(struct channel_gk20a *ch, u32 priority); | ||
271 | 272 | ||
272 | #endif /* CHANNEL_GK20A_H */ | 273 | #endif /* CHANNEL_GK20A_H */ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 2b4c3237..a58a1eed 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -260,6 +260,7 @@ struct gpu_ops { | |||
260 | int (*wait_engine_idle)(struct gk20a *g); | 260 | int (*wait_engine_idle)(struct gk20a *g); |
261 | u32 (*get_num_fifos)(struct gk20a *g); | 261 | u32 (*get_num_fifos)(struct gk20a *g); |
262 | u32 (*get_pbdma_signature)(struct gk20a *g); | 262 | u32 (*get_pbdma_signature)(struct gk20a *g); |
263 | int (*channel_set_priority)(struct channel_gk20a *ch, u32 priority); | ||
263 | } fifo; | 264 | } fifo; |
264 | struct pmu_v { | 265 | struct pmu_v { |
265 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 266 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 0e736373..d1deffb9 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -113,6 +113,7 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
113 | gops->fifo.alloc_inst = channel_gk20a_alloc_inst; | 113 | gops->fifo.alloc_inst = channel_gk20a_alloc_inst; |
114 | gops->fifo.free_inst = channel_gk20a_free_inst; | 114 | gops->fifo.free_inst = channel_gk20a_free_inst; |
115 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; | 115 | gops->fifo.setup_ramfc = channel_gk20a_setup_ramfc; |
116 | gops->fifo.channel_set_priority = gk20a_channel_set_priority; | ||
116 | 117 | ||
117 | gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; | 118 | gops->fifo.preempt_channel = gk20a_fifo_preempt_channel; |
118 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; | 119 | gops->fifo.update_runlist = gk20a_fifo_update_runlist; |
diff --git a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c index 3db215bc..e776e97c 100644 --- a/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c +++ b/drivers/gpu/nvgpu/vgpu/fifo_vgpu.c | |||
@@ -194,6 +194,12 @@ static int init_runlist(struct gk20a *g, struct fifo_gk20a *f) | |||
194 | if (!runlist->active_channels) | 194 | if (!runlist->active_channels) |
195 | goto clean_up_runlist_info; | 195 | goto clean_up_runlist_info; |
196 | 196 | ||
197 | runlist->high_prio_channels = | ||
198 | kzalloc(DIV_ROUND_UP(f->num_channels, BITS_PER_BYTE), | ||
199 | GFP_KERNEL); | ||
200 | if (!runlist->high_prio_channels) | ||
201 | goto clean_up_runlist_info; | ||
202 | |||
197 | runlist_size = sizeof(u16) * f->num_channels; | 203 | runlist_size = sizeof(u16) * f->num_channels; |
198 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { | 204 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) { |
199 | int err = gk20a_gmmu_alloc(g, runlist_size, &runlist->mem[i]); | 205 | int err = gk20a_gmmu_alloc(g, runlist_size, &runlist->mem[i]); |
@@ -215,10 +221,13 @@ clean_up_runlist: | |||
215 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) | 221 | for (i = 0; i < MAX_RUNLIST_BUFFERS; i++) |
216 | gk20a_gmmu_free(g, &runlist->mem[i]); | 222 | gk20a_gmmu_free(g, &runlist->mem[i]); |
217 | 223 | ||
224 | clean_up_runlist_info: | ||
225 | kfree(runlist->high_prio_channels); | ||
226 | runlist->high_prio_channels = NULL; | ||
227 | |||
218 | kfree(runlist->active_channels); | 228 | kfree(runlist->active_channels); |
219 | runlist->active_channels = NULL; | 229 | runlist->active_channels = NULL; |
220 | 230 | ||
221 | clean_up_runlist_info: | ||
222 | kfree(f->runlist_info); | 231 | kfree(f->runlist_info); |
223 | f->runlist_info = NULL; | 232 | f->runlist_info = NULL; |
224 | 233 | ||
@@ -521,6 +530,26 @@ static int vgpu_fifo_wait_engine_idle(struct gk20a *g) | |||
521 | return 0; | 530 | return 0; |
522 | } | 531 | } |
523 | 532 | ||
533 | static int vgpu_channel_set_priority(struct channel_gk20a *ch, u32 priority) | ||
534 | { | ||
535 | struct gk20a_platform *platform = gk20a_get_platform(ch->g->dev); | ||
536 | struct tegra_vgpu_cmd_msg msg; | ||
537 | struct tegra_vgpu_channel_priority_params *p = | ||
538 | &msg.params.channel_priority; | ||
539 | int err; | ||
540 | |||
541 | gk20a_dbg_info("channel %d set priority %u", ch->hw_chid, priority); | ||
542 | |||
543 | msg.cmd = TEGRA_VGPU_CMD_CHANNEL_SET_PRIORITY; | ||
544 | msg.handle = platform->virt_handle; | ||
545 | p->handle = ch->virt_ctx; | ||
546 | p->priority = priority; | ||
547 | err = vgpu_comm_sendrecv(&msg, sizeof(msg), sizeof(msg)); | ||
548 | WARN_ON(err || msg.ret); | ||
549 | |||
550 | return err ? err : msg.ret; | ||
551 | } | ||
552 | |||
524 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, | 553 | static void vgpu_fifo_set_ctx_mmu_error(struct gk20a *g, |
525 | struct channel_gk20a *ch) | 554 | struct channel_gk20a *ch) |
526 | { | 555 | { |
@@ -605,5 +634,6 @@ void vgpu_init_fifo_ops(struct gpu_ops *gops) | |||
605 | gops->fifo.preempt_channel = vgpu_fifo_preempt_channel; | 634 | gops->fifo.preempt_channel = vgpu_fifo_preempt_channel; |
606 | gops->fifo.update_runlist = vgpu_fifo_update_runlist; | 635 | gops->fifo.update_runlist = vgpu_fifo_update_runlist; |
607 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; | 636 | gops->fifo.wait_engine_idle = vgpu_fifo_wait_engine_idle; |
637 | gops->fifo.channel_set_priority = vgpu_channel_set_priority; | ||
608 | } | 638 | } |
609 | 639 | ||