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authorVijayakumar <vsubbu@nvidia.com>2016-10-27 09:46:36 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2016-12-15 13:15:10 -0500
commit8ef013e36ec2dc3be878d057024290e00b7aad49 (patch)
tree0570c8eaac96774f0e49000dd3fb5ba4e29475df /drivers/gpu
parent68eeda3ebdd6ca20289fb0af22a0ca593198bc63 (diff)
gpu: nvgpu: handle vf curve change due to temp
JIRA DNVGPU-129 1)Add function hook for PMU VFE event handler which will do for VF curve re-evaluation 2)Add function hook to send temperature limit of GPU sensor 3)Call VFE event handler from PMU's event handle function Change-Id: I2e3577d3d895e97e6ad06e92f0f4827f9855d0b6 Signed-off-by: Vijayakumar <vsubbu@nvidia.com> Reviewed-on: http://git-master/r/1245393 (cherry picked from commit 1a5c6c32cdec73fb23735430f43577eda675e5af) Reviewed-on: http://git-master/r/1268060 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h5
-rw-r--r--drivers/gpu/nvgpu/gk20a/pmu_gk20a.c10
-rw-r--r--drivers/gpu/nvgpu/pmuif/gpmuifperf.h1
3 files changed, 15 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 02d3ffe0..ed3a1d2d 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -589,6 +589,8 @@ struct gpu_ops {
589 int (*elcg_init_idle_filters)(struct gk20a *g); 589 int (*elcg_init_idle_filters)(struct gk20a *g);
590 void (*therm_debugfs_init)(struct gk20a *g); 590 void (*therm_debugfs_init)(struct gk20a *g);
591 int (*get_internal_sensor_curr_temp)(struct gk20a *g, u32 *temp_f24_8); 591 int (*get_internal_sensor_curr_temp)(struct gk20a *g, u32 *temp_f24_8);
592 void (*get_internal_sensor_limits)(s32 *max_24_8,
593 s32 *min_24_8);
592 } therm; 594 } therm;
593 struct { 595 struct {
594 bool (*is_pmu_supported)(struct gk20a *g); 596 bool (*is_pmu_supported)(struct gk20a *g);
@@ -642,6 +644,9 @@ struct gpu_ops {
642 int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain, 644 int (*get_arbiter_clk_default)(struct gk20a *g, u32 api_domain,
643 u16 *default_mhz); 645 u16 *default_mhz);
644 } clk_arb; 646 } clk_arb;
647 struct {
648 int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg);
649 } perf;
645 bool privsecurity; 650 bool privsecurity;
646 bool securegpccs; 651 bool securegpccs;
647 bool pmupstate; 652 bool pmupstate;
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index 1e9f291f..1d580dae 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -3976,14 +3976,22 @@ static int pmu_handle_perfmon_event(struct pmu_gk20a *pmu,
3976static int pmu_handle_event(struct pmu_gk20a *pmu, struct pmu_msg *msg) 3976static int pmu_handle_event(struct pmu_gk20a *pmu, struct pmu_msg *msg)
3977{ 3977{
3978 int err = 0; 3978 int err = 0;
3979 struct gk20a *g = gk20a_from_pmu(pmu);
3979 3980
3980 gk20a_dbg_fn(""); 3981 gk20a_dbg_fn("");
3981
3982 switch (msg->hdr.unit_id) { 3982 switch (msg->hdr.unit_id) {
3983 case PMU_UNIT_PERFMON: 3983 case PMU_UNIT_PERFMON:
3984 case PMU_UNIT_PERFMON_T18X: 3984 case PMU_UNIT_PERFMON_T18X:
3985 err = pmu_handle_perfmon_event(pmu, &msg->msg.perfmon); 3985 err = pmu_handle_perfmon_event(pmu, &msg->msg.perfmon);
3986 break; 3986 break;
3987 case PMU_UNIT_PERF:
3988 if (g->ops.perf.handle_pmu_perf_event != NULL) {
3989 err = g->ops.perf.handle_pmu_perf_event(g,
3990 (void *)&msg->msg.perf);
3991 } else {
3992 WARN_ON(1);
3993 }
3994 break;
3987 default: 3995 default:
3988 break; 3996 break;
3989 } 3997 }
diff --git a/drivers/gpu/nvgpu/pmuif/gpmuifperf.h b/drivers/gpu/nvgpu/pmuif/gpmuifperf.h
index b1d2f3fd..181a65f5 100644
--- a/drivers/gpu/nvgpu/pmuif/gpmuifperf.h
+++ b/drivers/gpu/nvgpu/pmuif/gpmuifperf.h
@@ -87,6 +87,7 @@ struct nv_pmu_perf_rpc {
87#define NV_PMU_PERF_MSG_ID_RPC (0x00000003) 87#define NV_PMU_PERF_MSG_ID_RPC (0x00000003)
88#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004) 88#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_SET (0x00000004)
89#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006) 89#define NV_PMU_PERF_MSG_ID_BOARDOBJ_GRP_GET_STATUS (0x00000006)
90#define NV_PMU_PERF_MSG_ID_VFE_CALLBACK (0x00000005)
90 91
91/*! 92/*!
92* Message carrying the result of the perf RPC execution. 93* Message carrying the result of the perf RPC execution.