diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-10-06 15:44:37 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-12-07 12:52:47 -0500 |
commit | 8cdd72996c3973490589819e9b462283369bd77b (patch) | |
tree | ed2ab0f9d09d4c800d865eeeacee62ed76edcd2e /drivers/gpu | |
parent | 1ee25b11c519089da3fdfb299c37eb64d39a2213 (diff) |
gpu: nvgpu: gm20b: Add tile caching registers
Add tile caching related registers to access map.
Bug 1692373
Change-Id: I4516812dd571bed3be2dfa2b210abe3177e794fe
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/812354
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 81067f0a..d6f56d78 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1133,7 +1133,31 @@ static void gr_gm20b_get_access_map(struct gk20a *g, | |||
1133 | static u32 wl_addr_gm20b[] = { | 1133 | static u32 wl_addr_gm20b[] = { |
1134 | /* this list must be sorted (low to high) */ | 1134 | /* this list must be sorted (low to high) */ |
1135 | 0x404468, /* gr_pri_mme_max_instructions */ | 1135 | 0x404468, /* gr_pri_mme_max_instructions */ |
1136 | 0x418300, /* gr_pri_gpcs_rasterarb_line_class */ | ||
1136 | 0x418800, /* gr_pri_gpcs_setup_debug */ | 1137 | 0x418800, /* gr_pri_gpcs_setup_debug */ |
1138 | 0x418e00, /* gr_pri_gpcs_swdx_config */ | ||
1139 | 0x418e40, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ | ||
1140 | 0x418e44, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ | ||
1141 | 0x418e48, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ | ||
1142 | 0x418e4c, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ | ||
1143 | 0x418e50, /* gr_pri_gpcs_swdx_tc_bundle_ctrl */ | ||
1144 | 0x418e58, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1145 | 0x418e5c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1146 | 0x418e60, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1147 | 0x418e64, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1148 | 0x418e68, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1149 | 0x418e6c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1150 | 0x418e70, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1151 | 0x418e74, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1152 | 0x418e78, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1153 | 0x418e7c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1154 | 0x418e80, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1155 | 0x418e84, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1156 | 0x418e88, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1157 | 0x418e8c, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1158 | 0x418e90, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1159 | 0x418e94, /* gr_pri_gpcs_swdx_tc_bundle_addr */ | ||
1160 | 0x419864, /* gr_pri_gpcs_tpcs_pe_l2_evict_policy */ | ||
1137 | 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ | 1161 | 0x419a04, /* gr_pri_gpcs_tpcs_tex_lod_dbg */ |
1138 | 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ | 1162 | 0x419a08, /* gr_pri_gpcs_tpcs_tex_samp_dbg */ |
1139 | 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ | 1163 | 0x419e10, /* gr_pri_gpcs_tpcs_sm_dbgr_control0 */ |