diff options
author | seshendra Gadagottu <sgadagottu@nvidia.com> | 2018-04-26 21:33:06 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-05-04 00:44:25 -0400 |
commit | 8b666b0bd6987781611103f7bb74cbdd44ef80b5 (patch) | |
tree | 5e34fcbebf76e218a5bbbf3d32e380fd4e02898e /drivers/gpu | |
parent | c9463fdbb31324cc8eaa7fbed69f8d4b98ef38b5 (diff) |
gpu: nvgpu: add sw method for SHADER_CUT_COLLECTOR
Added sw method for NVC397_SET_SHADER_CUT_COLLECTOR
to enable/disable SHADER_CUT_COLLECTOR_STATE.
Added support for this sw method in gv11b and gv100.
Bug 2108381
Change-Id: Ief2c2bf5d9c99779dad3b1243041c5efe56287d3
Signed-off-by: seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1703662
GVS: Gerrit_Virtual_Submit
Reviewed-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 22 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.h | 4 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | 12 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | 12 |
4 files changed, 50 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 3ae09058..52e442f3 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1202,6 +1202,25 @@ static void gv11b_gr_set_shader_exceptions(struct gk20a *g, u32 data) | |||
1202 | } | 1202 | } |
1203 | } | 1203 | } |
1204 | 1204 | ||
1205 | static void gr_gv11b_set_shader_cut_collector(struct gk20a *g, u32 data) | ||
1206 | { | ||
1207 | u32 val; | ||
1208 | |||
1209 | nvgpu_log_fn(g, "gr_gv11b_set_shader_cut_collector"); | ||
1210 | |||
1211 | val = gk20a_readl(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r()); | ||
1212 | if (data & NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE) | ||
1213 | val = set_field(val, | ||
1214 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(), | ||
1215 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f()); | ||
1216 | else | ||
1217 | val = set_field(val, | ||
1218 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(), | ||
1219 | gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f()); | ||
1220 | gk20a_writel(g, gr_gpcs_tpcs_sm_l1tag_ctrl_r(), val); | ||
1221 | } | ||
1222 | |||
1223 | |||
1205 | int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | 1224 | int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, |
1206 | u32 class_num, u32 offset, u32 data) | 1225 | u32 class_num, u32 offset, u32 data) |
1207 | { | 1226 | { |
@@ -1249,6 +1268,9 @@ int gr_gv11b_handle_sw_method(struct gk20a *g, u32 addr, | |||
1249 | case NVC397_SET_BES_CROP_DEBUG4: | 1268 | case NVC397_SET_BES_CROP_DEBUG4: |
1250 | g->ops.gr.set_bes_crop_debug4(g, data); | 1269 | g->ops.gr.set_bes_crop_debug4(g, data); |
1251 | break; | 1270 | break; |
1271 | case NVC397_SET_SHADER_CUT_COLLECTOR: | ||
1272 | gr_gv11b_set_shader_cut_collector(g, data); | ||
1273 | break; | ||
1252 | default: | 1274 | default: |
1253 | goto fail; | 1275 | goto fail; |
1254 | } | 1276 | } |
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h index 398731a4..dac82677 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.h +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.h | |||
@@ -63,6 +63,7 @@ enum { | |||
63 | #define NVC397_SET_SKEDCHECK 0x10c0 | 63 | #define NVC397_SET_SKEDCHECK 0x10c0 |
64 | #define NVC397_SET_BES_CROP_DEBUG3 0x10c4 | 64 | #define NVC397_SET_BES_CROP_DEBUG3 0x10c4 |
65 | #define NVC397_SET_BES_CROP_DEBUG4 0x10b0 | 65 | #define NVC397_SET_BES_CROP_DEBUG4 0x10b0 |
66 | #define NVC397_SET_SHADER_CUT_COLLECTOR 0x10c8 | ||
66 | 67 | ||
67 | #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 | 68 | #define NVC397_SET_TEX_IN_DBG_TSL1_RVCH_INVALIDATE 0x1 |
68 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 | 69 | #define NVC397_SET_TEX_IN_DBG_SM_L1TAG_CTRL_CACHE_SURFACE_LD 0x2 |
@@ -73,6 +74,9 @@ enum { | |||
73 | #define NVC397_SET_SKEDCHECK_18_DISABLE 0x1 | 74 | #define NVC397_SET_SKEDCHECK_18_DISABLE 0x1 |
74 | #define NVC397_SET_SKEDCHECK_18_ENABLE 0x2 | 75 | #define NVC397_SET_SKEDCHECK_18_ENABLE 0x2 |
75 | 76 | ||
77 | #define NVC397_SET_SHADER_CUT_COLLECTOR_STATE_DISABLE 0x0 | ||
78 | #define NVC397_SET_SHADER_CUT_COLLECTOR_STATE_ENABLE 0x1 | ||
79 | |||
76 | #define NVC3C0_SET_SKEDCHECK 0x23c | 80 | #define NVC3C0_SET_SKEDCHECK 0x23c |
77 | 81 | ||
78 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 | 82 | #define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h index f5f09cdf..29fd9a6f 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv100/hw_gr_gv100.h | |||
@@ -3884,6 +3884,18 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) | |||
3884 | { | 3884 | { |
3885 | return 0x1U << 10U; | 3885 | return 0x1U << 10U; |
3886 | } | 3886 | } |
3887 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) | ||
3888 | { | ||
3889 | return 0x1U << 28U; | ||
3890 | } | ||
3891 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) | ||
3892 | { | ||
3893 | return 0x0U; | ||
3894 | } | ||
3895 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) | ||
3896 | { | ||
3897 | return 0x10000000U; | ||
3898 | } | ||
3887 | static inline u32 gr_fe_pwr_mode_r(void) | 3899 | static inline u32 gr_fe_pwr_mode_r(void) |
3888 | { | 3900 | { |
3889 | return 0x00404170U; | 3901 | return 0x00404170U; |
diff --git a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h index f7968089..17c7e77d 100644 --- a/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h +++ b/drivers/gpu/nvgpu/include/nvgpu/hw/gv11b/hw_gr_gv11b.h | |||
@@ -4640,6 +4640,18 @@ static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_cache_surface_st_m(void) | |||
4640 | { | 4640 | { |
4641 | return 0x1U << 10U; | 4641 | return 0x1U << 10U; |
4642 | } | 4642 | } |
4643 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_m(void) | ||
4644 | { | ||
4645 | return 0x1U << 28U; | ||
4646 | } | ||
4647 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_disable_f(void) | ||
4648 | { | ||
4649 | return 0x0U; | ||
4650 | } | ||
4651 | static inline u32 gr_gpcs_tpcs_sm_l1tag_ctrl_always_cut_collector_enable_f(void) | ||
4652 | { | ||
4653 | return 0x10000000U; | ||
4654 | } | ||
4643 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) | 4655 | static inline u32 gr_egpc0_etpc0_sm_dsm_perf_counter_control_sel0_r(void) |
4644 | { | 4656 | { |
4645 | return 0x00584200U; | 4657 | return 0x00584200U; |