gpu: nvgpu: gp10b: Program TEX RM registers

Program CB base to new gp10b registers.

Change-Id: I1ab39a487dade58d3a024fb1aba1af5c878f31bb
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/752634

2 files changed, 81 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
index 240bab81..973653a0 100644
--- a/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/gr_gp10b.c
@@ -844,6 +844,34 @@ static int gr_gp10b_wait_empty(struct gk20a *g, unsigned long end_jiffies,
         return -EAGAIN;
 }
 
+static void gr_gp10b_commit_global_attrib_cb(struct gk20a *g,
+                                             struct channel_ctx_gk20a *ch_ctx,
+                                             u64 addr, bool patch)
+{
+        struct gr_ctx_desc *gr_ctx = ch_ctx->gr_ctx;
+        int attrBufferSize;
+
+        if (gr_ctx->t18x.preempt_ctxsw_buffer.gpu_va)
+                attrBufferSize = gr_ctx->t18x.preempt_ctxsw_buffer.size;
+        else
+                attrBufferSize = g->ops.gr.calc_global_ctx_buffer_size(g);
+
+        attrBufferSize /= gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f();
+
+        gr_gm20b_commit_global_attrib_cb(g, ch_ctx, addr, patch);
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_r(),
+                gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_v_f(addr) |
+                gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch);
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_0_r(),
+                gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(addr), patch);
+
+        gr_gk20a_ctx_patch_write(g, ch_ctx, gr_gpcs_tpcs_tex_rm_cb_1_r(),
+                gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(attrBufferSize) |
+                gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(), patch);
+}
+
 void gp10b_init_gr(struct gpu_ops *gops)
 {
         gm20b_init_gr(gops);
@@ -855,6 +883,7 @@ void gp10b_init_gr(struct gpu_ops *gops)
         gops->gr.pagepool_default_size = gr_gp10b_pagepool_default_size;
         gops->gr.calc_global_ctx_buffer_size =
                 gr_gp10b_calc_global_ctx_buffer_size;
+        gops->gr.commit_global_attrib_cb = gr_gp10b_commit_global_attrib_cb;
         gops->gr.handle_sw_method = gr_gp10b_handle_sw_method;
         gops->gr.cb_size_default = gr_gp10b_cb_size_default;
         gops->gr.set_alpha_circular_buffer_size =
diff --git a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
index b185604e..32903fba 100644
--- a/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
+++ b/drivers/gpu/nvgpu/gp10b/hw_gr_gp10b.h
@@ -2206,6 +2206,58 @@ static inline u32 gr_gpc0_ppc0_cbm_beta_steady_state_cb_size_v_default_v(void)
 {
         return 0x00030000;
 }
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_r(void)
+{
+        return 0x00419b00;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_0_base_addr_43_12_f(u32 v)
+{
+        return (v & 0xffffffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_r(void)
+{
+        return 0x00419b04;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_s(void)
+{
+        return 21;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_f(u32 v)
+{
+        return (v & 0x1fffff) << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_m(void)
+{
+        return 0x1fffff << 0;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_v(u32 r)
+{
+        return (r >> 0) & 0x1fffff;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_size_div_128b_granularity_f(void)
+{
+        return 0x80;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_s(void)
+{
+        return 1;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_f(u32 v)
+{
+        return (v & 0x1) << 31;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_m(void)
+{
+        return 0x1 << 31;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_v(u32 r)
+{
+        return (r >> 31) & 0x1;
+}
+static inline u32 gr_gpcs_tpcs_tex_rm_cb_1_valid_true_f(void)
+{
+        return 0x80000000;
+}
 static inline u32 gr_gpccs_falcon_addr_r(void)
 {
         return 0x0041a0ac;