diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2018-08-08 05:23:08 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-10 11:15:46 -0400 |
commit | 84c0ab81ab28b349c5477b0512b8bbfdb24edc3d (patch) | |
tree | 5dff4816e5be641d7293e1c4dff1bb5d39653059 /drivers/gpu | |
parent | 542e6a0ab4fe3839633a3a86c80b394fd046ac79 (diff) |
gpu: nvgpu: move exec_reg_ops() to regops HAL
We right now define HAL exec_reg_ops() under gops.dbg_session_ops operations
But we have separate gops.regops operations for all the regops and this would
be logically correct place for exec_reg_ops()
Move exec_reg_ops() from gops.dbg_session_ops to gops.regops
Also rename it to exec_regops()
Jira NVGPU-620
Change-Id: If4f70639ffbc892c605f7540a83bce12ed821b52
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1794999
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | 2 |
9 files changed, 11 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index ffa5e318..e8815b53 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -1100,6 +1100,9 @@ struct gpu_ops { | |||
1100 | int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); | 1100 | int (*handle_pmu_perf_event)(struct gk20a *g, void *pmu_msg); |
1101 | } perf; | 1101 | } perf; |
1102 | struct { | 1102 | struct { |
1103 | int (*exec_regops)(struct dbg_session_gk20a *dbg_s, | ||
1104 | struct nvgpu_dbg_reg_op *ops, | ||
1105 | u64 num_ops); | ||
1103 | const struct regop_offset_range* ( | 1106 | const struct regop_offset_range* ( |
1104 | *get_global_whitelist_ranges)(void); | 1107 | *get_global_whitelist_ranges)(void); |
1105 | int (*get_global_whitelist_ranges_count)(void); | 1108 | int (*get_global_whitelist_ranges_count)(void); |
@@ -1147,9 +1150,6 @@ struct gpu_ops { | |||
1147 | struct gk20a_debug_output *o); | 1150 | struct gk20a_debug_output *o); |
1148 | } debug; | 1151 | } debug; |
1149 | struct { | 1152 | struct { |
1150 | int (*exec_reg_ops)(struct dbg_session_gk20a *dbg_s, | ||
1151 | struct nvgpu_dbg_reg_op *ops, | ||
1152 | u64 num_ops); | ||
1153 | int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, | 1153 | int (*dbg_set_powergate)(struct dbg_session_gk20a *dbg_s, |
1154 | bool disable_powergate); | 1154 | bool disable_powergate); |
1155 | bool (*check_and_set_global_reservation)( | 1155 | bool (*check_and_set_global_reservation)( |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 7e94d6c7..b37f6244 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -555,6 +555,7 @@ static const struct gpu_ops gm20b_ops = { | |||
555 | .get_pll_debug_data = gm20b_clk_get_pll_debug_data, | 555 | .get_pll_debug_data = gm20b_clk_get_pll_debug_data, |
556 | }, | 556 | }, |
557 | .regops = { | 557 | .regops = { |
558 | .exec_regops = exec_regops_gk20a, | ||
558 | .get_global_whitelist_ranges = | 559 | .get_global_whitelist_ranges = |
559 | gm20b_get_global_whitelist_ranges, | 560 | gm20b_get_global_whitelist_ranges, |
560 | .get_global_whitelist_ranges_count = | 561 | .get_global_whitelist_ranges_count = |
@@ -603,7 +604,6 @@ static const struct gpu_ops gm20b_ops = { | |||
603 | .post_events = gk20a_dbg_gpu_post_events, | 604 | .post_events = gk20a_dbg_gpu_post_events, |
604 | }, | 605 | }, |
605 | .dbg_session_ops = { | 606 | .dbg_session_ops = { |
606 | .exec_reg_ops = exec_regops_gk20a, | ||
607 | .dbg_set_powergate = dbg_set_powergate, | 607 | .dbg_set_powergate = dbg_set_powergate, |
608 | .check_and_set_global_reservation = | 608 | .check_and_set_global_reservation = |
609 | nvgpu_check_and_set_global_reservation, | 609 | nvgpu_check_and_set_global_reservation, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index 07846337..a2e76a00 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -672,6 +672,7 @@ static const struct gpu_ops gp106_ops = { | |||
672 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | 672 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, |
673 | }, | 673 | }, |
674 | .regops = { | 674 | .regops = { |
675 | .exec_regops = exec_regops_gk20a, | ||
675 | .get_global_whitelist_ranges = | 676 | .get_global_whitelist_ranges = |
676 | gp106_get_global_whitelist_ranges, | 677 | gp106_get_global_whitelist_ranges, |
677 | .get_global_whitelist_ranges_count = | 678 | .get_global_whitelist_ranges_count = |
@@ -720,7 +721,6 @@ static const struct gpu_ops gp106_ops = { | |||
720 | .post_events = gk20a_dbg_gpu_post_events, | 721 | .post_events = gk20a_dbg_gpu_post_events, |
721 | }, | 722 | }, |
722 | .dbg_session_ops = { | 723 | .dbg_session_ops = { |
723 | .exec_reg_ops = exec_regops_gk20a, | ||
724 | .dbg_set_powergate = dbg_set_powergate, | 724 | .dbg_set_powergate = dbg_set_powergate, |
725 | .check_and_set_global_reservation = | 725 | .check_and_set_global_reservation = |
726 | nvgpu_check_and_set_global_reservation, | 726 | nvgpu_check_and_set_global_reservation, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index 2b0c07d8..3d5eb231 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -600,6 +600,7 @@ static const struct gpu_ops gp10b_ops = { | |||
600 | .get_irqdest = gk20a_pmu_get_irqdest, | 600 | .get_irqdest = gk20a_pmu_get_irqdest, |
601 | }, | 601 | }, |
602 | .regops = { | 602 | .regops = { |
603 | .exec_regops = exec_regops_gk20a, | ||
603 | .get_global_whitelist_ranges = | 604 | .get_global_whitelist_ranges = |
604 | gp10b_get_global_whitelist_ranges, | 605 | gp10b_get_global_whitelist_ranges, |
605 | .get_global_whitelist_ranges_count = | 606 | .get_global_whitelist_ranges_count = |
@@ -648,7 +649,6 @@ static const struct gpu_ops gp10b_ops = { | |||
648 | .post_events = gk20a_dbg_gpu_post_events, | 649 | .post_events = gk20a_dbg_gpu_post_events, |
649 | }, | 650 | }, |
650 | .dbg_session_ops = { | 651 | .dbg_session_ops = { |
651 | .exec_reg_ops = exec_regops_gk20a, | ||
652 | .dbg_set_powergate = dbg_set_powergate, | 652 | .dbg_set_powergate = dbg_set_powergate, |
653 | .check_and_set_global_reservation = | 653 | .check_and_set_global_reservation = |
654 | nvgpu_check_and_set_global_reservation, | 654 | nvgpu_check_and_set_global_reservation, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index 0f7fb370..f6c3ec67 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -763,6 +763,7 @@ static const struct gpu_ops gv100_ops = { | |||
763 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, | 763 | .get_current_pstate = nvgpu_clk_arb_get_current_pstate, |
764 | }, | 764 | }, |
765 | .regops = { | 765 | .regops = { |
766 | .exec_regops = exec_regops_gk20a, | ||
766 | .get_global_whitelist_ranges = | 767 | .get_global_whitelist_ranges = |
767 | gv100_get_global_whitelist_ranges, | 768 | gv100_get_global_whitelist_ranges, |
768 | .get_global_whitelist_ranges_count = | 769 | .get_global_whitelist_ranges_count = |
@@ -815,7 +816,6 @@ static const struct gpu_ops gv100_ops = { | |||
815 | .post_events = gk20a_dbg_gpu_post_events, | 816 | .post_events = gk20a_dbg_gpu_post_events, |
816 | }, | 817 | }, |
817 | .dbg_session_ops = { | 818 | .dbg_session_ops = { |
818 | .exec_reg_ops = exec_regops_gk20a, | ||
819 | .dbg_set_powergate = dbg_set_powergate, | 819 | .dbg_set_powergate = dbg_set_powergate, |
820 | .check_and_set_global_reservation = | 820 | .check_and_set_global_reservation = |
821 | nvgpu_check_and_set_global_reservation, | 821 | nvgpu_check_and_set_global_reservation, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index f93f977b..20a0b34f 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -696,6 +696,7 @@ static const struct gpu_ops gv11b_ops = { | |||
696 | .handle_ext_irq = gv11b_pmu_handle_ext_irq, | 696 | .handle_ext_irq = gv11b_pmu_handle_ext_irq, |
697 | }, | 697 | }, |
698 | .regops = { | 698 | .regops = { |
699 | .exec_regops = exec_regops_gk20a, | ||
699 | .get_global_whitelist_ranges = | 700 | .get_global_whitelist_ranges = |
700 | gv11b_get_global_whitelist_ranges, | 701 | gv11b_get_global_whitelist_ranges, |
701 | .get_global_whitelist_ranges_count = | 702 | .get_global_whitelist_ranges_count = |
@@ -747,7 +748,6 @@ static const struct gpu_ops gv11b_ops = { | |||
747 | .post_events = gk20a_dbg_gpu_post_events, | 748 | .post_events = gk20a_dbg_gpu_post_events, |
748 | }, | 749 | }, |
749 | .dbg_session_ops = { | 750 | .dbg_session_ops = { |
750 | .exec_reg_ops = exec_regops_gk20a, | ||
751 | .dbg_set_powergate = dbg_set_powergate, | 751 | .dbg_set_powergate = dbg_set_powergate, |
752 | .check_and_set_global_reservation = | 752 | .check_and_set_global_reservation = |
753 | nvgpu_check_and_set_global_reservation, | 753 | nvgpu_check_and_set_global_reservation, |
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c index b2c7a362..0e7bbf24 100644 --- a/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c +++ b/drivers/gpu/nvgpu/os/linux/ioctl_dbg.c | |||
@@ -935,7 +935,7 @@ static int nvgpu_ioctl_channel_reg_ops(struct dbg_session_gk20a *dbg_s, | |||
935 | if (err) | 935 | if (err) |
936 | break; | 936 | break; |
937 | 937 | ||
938 | err = g->ops.dbg_session_ops.exec_reg_ops( | 938 | err = g->ops.regops.exec_regops( |
939 | dbg_s, g->dbg_regops_tmp_buf, num_ops); | 939 | dbg_s, g->dbg_regops_tmp_buf, num_ops); |
940 | 940 | ||
941 | if (err) { | 941 | if (err) { |
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c index 45b907ac..a8aa023b 100644 --- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c +++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c | |||
@@ -466,6 +466,7 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
466 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, | 466 | .is_engine_in_reset = gk20a_pmu_is_engine_in_reset, |
467 | }, | 467 | }, |
468 | .regops = { | 468 | .regops = { |
469 | .exec_regops = vgpu_exec_regops, | ||
469 | .get_global_whitelist_ranges = | 470 | .get_global_whitelist_ranges = |
470 | gp10b_get_global_whitelist_ranges, | 471 | gp10b_get_global_whitelist_ranges, |
471 | .get_global_whitelist_ranges_count = | 472 | .get_global_whitelist_ranges_count = |
@@ -514,7 +515,6 @@ static const struct gpu_ops vgpu_gp10b_ops = { | |||
514 | .post_events = gk20a_dbg_gpu_post_events, | 515 | .post_events = gk20a_dbg_gpu_post_events, |
515 | }, | 516 | }, |
516 | .dbg_session_ops = { | 517 | .dbg_session_ops = { |
517 | .exec_reg_ops = vgpu_exec_regops, | ||
518 | .dbg_set_powergate = vgpu_dbg_set_powergate, | 518 | .dbg_set_powergate = vgpu_dbg_set_powergate, |
519 | .check_and_set_global_reservation = | 519 | .check_and_set_global_reservation = |
520 | vgpu_check_and_set_global_reservation, | 520 | vgpu_check_and_set_global_reservation, |
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c index f38585f4..b91691e2 100644 --- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c +++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c | |||
@@ -535,6 +535,7 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
535 | .is_pmu_supported = gv11b_is_pmu_supported, | 535 | .is_pmu_supported = gv11b_is_pmu_supported, |
536 | }, | 536 | }, |
537 | .regops = { | 537 | .regops = { |
538 | .exec_regops = vgpu_exec_regops, | ||
538 | .get_global_whitelist_ranges = | 539 | .get_global_whitelist_ranges = |
539 | gv11b_get_global_whitelist_ranges, | 540 | gv11b_get_global_whitelist_ranges, |
540 | .get_global_whitelist_ranges_count = | 541 | .get_global_whitelist_ranges_count = |
@@ -584,7 +585,6 @@ static const struct gpu_ops vgpu_gv11b_ops = { | |||
584 | .post_events = gk20a_dbg_gpu_post_events, | 585 | .post_events = gk20a_dbg_gpu_post_events, |
585 | }, | 586 | }, |
586 | .dbg_session_ops = { | 587 | .dbg_session_ops = { |
587 | .exec_reg_ops = vgpu_exec_regops, | ||
588 | .dbg_set_powergate = vgpu_dbg_set_powergate, | 588 | .dbg_set_powergate = vgpu_dbg_set_powergate, |
589 | .check_and_set_global_reservation = | 589 | .check_and_set_global_reservation = |
590 | vgpu_check_and_set_global_reservation, | 590 | vgpu_check_and_set_global_reservation, |