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authorAlex Frid <afrid@nvidia.com>2014-08-20 23:37:40 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:01 -0400
commit7687e551e8fc3987ad3294484437bd67f00500c0 (patch)
tree65feb10cea8b5952b0fd093a590fca4f0cb0b8b5 /drivers/gpu
parentc8a0edc2255a0c4a0a97657fda989216a7e982d4 (diff)
gpu: nvgpu: Add clock idle slowdown register
Added clock idle slowdown register. Fixed duplicated/overlapping therm_peakpower_config8_r and therm_peakpower_config1_r definitions. Change-Id: I37dad714ce5a6730a2f0b7c1b31b509bb1823975 Signed-off-by: Alex Frid <afrid@nvidia.com> Reviewed-on: http://git-master/r/486323 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h34
1 files changed, 25 insertions, 9 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h
index 3431116e..09bd5830 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h
@@ -90,23 +90,23 @@ static inline u32 therm_peakpower_config1_window_en_enabled_f(void)
90{ 90{
91 return 0x80000000; 91 return 0x80000000;
92} 92}
93static inline u32 therm_peakpower_config1_r(u32 i) 93static inline u32 therm_peakpower_config8_r(u32 i)
94{ 94{
95 return 0x000202e8 + i*4; 95 return 0x000202e8 + i*4;
96} 96}
97static inline u32 therm_peakpower_config1_ba_sum_shift_s(void) 97static inline u32 therm_peakpower_config8_ba_sum_shift_s(void)
98{ 98{
99 return 5; 99 return 5;
100} 100}
101static inline u32 therm_peakpower_config1_ba_sum_shift_f(u32 v) 101static inline u32 therm_peakpower_config8_ba_sum_shift_f(u32 v)
102{ 102{
103 return (v & 0x1f) << 8; 103 return (v & 0x1f) << 8;
104} 104}
105static inline u32 therm_peakpower_config1_ba_sum_shift_m(void) 105static inline u32 therm_peakpower_config8_ba_sum_shift_m(void)
106{ 106{
107 return 0x1f << 8; 107 return 0x1f << 8;
108} 108}
109static inline u32 therm_peakpower_config1_ba_sum_shift_v(u32 r) 109static inline u32 therm_peakpower_config8_ba_sum_shift_v(u32 r)
110{ 110{
111 return (r >> 8) & 0x1f; 111 return (r >> 8) & 0x1f;
112} 112}
@@ -122,10 +122,6 @@ static inline u32 therm_peakpower_config6_r(u32 i)
122{ 122{
123 return 0x00020270 + i*4; 123 return 0x00020270 + i*4;
124} 124}
125static inline u32 therm_peakpower_config8_r(u32 i)
126{
127 return 0x000202e8 + i*4;
128}
129static inline u32 therm_peakpower_config9_r(u32 i) 125static inline u32 therm_peakpower_config9_r(u32 i)
130{ 126{
131 return 0x000202f4 + i*4; 127 return 0x000202f4 + i*4;
@@ -222,4 +218,24 @@ static inline u32 therm_hubmmu_idle_filter_value_m(void)
222{ 218{
223 return 0xffffffff << 0; 219 return 0xffffffff << 0;
224} 220}
221static inline u32 therm_clk_slowdown_r(u32 i)
222{
223 return 0x00020160 + i*4;
224}
225static inline u32 therm_clk_slowdown_idle_factor_f(u32 v)
226{
227 return (v & 0x3f) << 16;
228}
229static inline u32 therm_clk_slowdown_idle_factor_m(void)
230{
231 return 0x3f << 16;
232}
233static inline u32 therm_clk_slowdown_idle_factor_v(u32 r)
234{
235 return (r >> 16) & 0x3f;
236}
237static inline u32 therm_clk_slowdown_idle_factor_disabled_f(void)
238{
239 return 0x0;
240}
225#endif 241#endif