diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2016-11-15 06:47:23 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-10 23:16:05 -0500 |
commit | 7552780739e3bf55402c5a845f230975fc4f3d27 (patch) | |
tree | 0ed8459c576063a422989417b4685d9694312b62 /drivers/gpu | |
parent | d8049d384fab27de0075aa5dff9dbf4874b19eb9 (diff) |
gpu: nvgpu: pg mscg state update
- Added mscg_transition_state to know
mscg allow/disallow status
- reused ELPG state transition defines
for mscg state transition
JIRA DNVGPU-71
Change-Id: Ie0214a174ceecf7e97a1086f53fd965b0b655d14
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: http://git-master/r/1253508
(cherry picked from commit 726dde9cff1da38525518a91e756598a5ab71f73)
Reviewed-on: http://git-master/r/1271617
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | 39 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | 1 |
2 files changed, 22 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c index af6ff1da..f9072cec 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c | |||
@@ -3347,7 +3347,6 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, | |||
3347 | { | 3347 | { |
3348 | struct pmu_gk20a *pmu = param; | 3348 | struct pmu_gk20a *pmu = param; |
3349 | struct pmu_pg_msg_elpg_msg *elpg_msg = &msg->msg.pg.elpg_msg; | 3349 | struct pmu_pg_msg_elpg_msg *elpg_msg = &msg->msg.pg.elpg_msg; |
3350 | u32 *ack_status = param; | ||
3351 | 3350 | ||
3352 | gk20a_dbg_fn(""); | 3351 | gk20a_dbg_fn(""); |
3353 | 3352 | ||
@@ -3367,14 +3366,18 @@ static void pmu_handle_pg_elpg_msg(struct gk20a *g, struct pmu_msg *msg, | |||
3367 | elpg_msg->engine_id); | 3366 | elpg_msg->engine_id); |
3368 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 3367 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
3369 | pmu->elpg_stat = PMU_ELPG_STAT_ON; | 3368 | pmu->elpg_stat = PMU_ELPG_STAT_ON; |
3369 | else if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | ||
3370 | pmu->mscg_transition_state = PMU_ELPG_STAT_ON; | ||
3370 | break; | 3371 | break; |
3371 | case PMU_PG_ELPG_MSG_DISALLOW_ACK: | 3372 | case PMU_PG_ELPG_MSG_DISALLOW_ACK: |
3372 | gk20a_dbg_pmu("DISALLOW is ack from PMU, eng - %d", | 3373 | gk20a_dbg_pmu("DISALLOW is ack from PMU, eng - %d", |
3373 | elpg_msg->engine_id); | 3374 | elpg_msg->engine_id); |
3375 | |||
3374 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 3376 | if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
3375 | pmu->elpg_stat = PMU_ELPG_STAT_OFF; | 3377 | pmu->elpg_stat = PMU_ELPG_STAT_OFF; |
3376 | else if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | 3378 | else if (elpg_msg->engine_id == PMU_PG_ELPG_ENGINE_ID_MS) |
3377 | *ack_status = 1; | 3379 | pmu->mscg_transition_state = PMU_ELPG_STAT_OFF; |
3380 | |||
3378 | if (pmu->pmu_state == PMU_STATE_ELPG_BOOTING) { | 3381 | if (pmu->pmu_state == PMU_STATE_ELPG_BOOTING) { |
3379 | if (g->ops.pmu.pmu_pg_engines_feature_list && | 3382 | if (g->ops.pmu.pmu_pg_engines_feature_list && |
3380 | g->ops.pmu.pmu_pg_engines_feature_list(g, | 3383 | g->ops.pmu.pmu_pg_engines_feature_list(g, |
@@ -3477,6 +3480,8 @@ static int pmu_pg_init_send(struct gk20a *g, u32 pg_engine_id) | |||
3477 | /* set for wait_event PMU_ELPG_STAT_OFF */ | 3480 | /* set for wait_event PMU_ELPG_STAT_OFF */ |
3478 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 3481 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
3479 | pmu->elpg_stat = PMU_ELPG_STAT_OFF; | 3482 | pmu->elpg_stat = PMU_ELPG_STAT_OFF; |
3483 | else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | ||
3484 | pmu->mscg_transition_state = PMU_ELPG_STAT_OFF; | ||
3480 | memset(&cmd, 0, sizeof(struct pmu_cmd)); | 3485 | memset(&cmd, 0, sizeof(struct pmu_cmd)); |
3481 | cmd.hdr.unit_id = PMU_UNIT_PG; | 3486 | cmd.hdr.unit_id = PMU_UNIT_PG; |
3482 | cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_pg_cmd_elpg_cmd); | 3487 | cmd.hdr.size = PMU_CMD_HDR_SIZE + sizeof(struct pmu_pg_cmd_elpg_cmd); |
@@ -4783,6 +4788,9 @@ static int gk20a_pmu_enable_elpg_locked(struct gk20a *g, u32 pg_engine_id) | |||
4783 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 4788 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
4784 | pmu->elpg_stat = PMU_ELPG_STAT_ON_PENDING; | 4789 | pmu->elpg_stat = PMU_ELPG_STAT_ON_PENDING; |
4785 | 4790 | ||
4791 | else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | ||
4792 | pmu->mscg_transition_state = PMU_ELPG_STAT_ON_PENDING; | ||
4793 | |||
4786 | gk20a_dbg_pmu("cmd post PMU_PG_ELPG_CMD_ALLOW"); | 4794 | gk20a_dbg_pmu("cmd post PMU_PG_ELPG_CMD_ALLOW"); |
4787 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, | 4795 | status = gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, |
4788 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, | 4796 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, |
@@ -4859,10 +4867,7 @@ int gk20a_pmu_disable_elpg(struct gk20a *g) | |||
4859 | int ret = 0; | 4867 | int ret = 0; |
4860 | u32 pg_engine_id; | 4868 | u32 pg_engine_id; |
4861 | u32 pg_engine_id_list = 0; | 4869 | u32 pg_engine_id_list = 0; |
4862 | u32 ack_status = 0; | 4870 | u32 *ptr = NULL; |
4863 | u32 *wait_msg_cond_ptr = NULL; | ||
4864 | u32 wait_msg_cond = 0; | ||
4865 | void *cb_param = NULL; | ||
4866 | 4871 | ||
4867 | gk20a_dbg_fn(""); | 4872 | gk20a_dbg_fn(""); |
4868 | 4873 | ||
@@ -4931,26 +4936,24 @@ int gk20a_pmu_disable_elpg(struct gk20a *g) | |||
4931 | 4936 | ||
4932 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) | 4937 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
4933 | pmu->elpg_stat = PMU_ELPG_STAT_OFF_PENDING; | 4938 | pmu->elpg_stat = PMU_ELPG_STAT_OFF_PENDING; |
4939 | else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) | ||
4940 | pmu->mscg_transition_state = | ||
4941 | PMU_ELPG_STAT_OFF_PENDING; | ||
4934 | 4942 | ||
4935 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) { | 4943 | if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_GRAPHICS) |
4936 | wait_msg_cond_ptr = &pmu->elpg_stat; | 4944 | ptr = &pmu->elpg_stat; |
4937 | wait_msg_cond = PMU_ELPG_STAT_OFF; | 4945 | else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) |
4938 | cb_param = pmu; | 4946 | ptr = &pmu->mscg_transition_state; |
4939 | } else if (pg_engine_id == PMU_PG_ELPG_ENGINE_ID_MS) { | ||
4940 | wait_msg_cond_ptr = &ack_status; | ||
4941 | wait_msg_cond = 0x1; | ||
4942 | cb_param = &ack_status; | ||
4943 | } | ||
4944 | 4947 | ||
4945 | gk20a_dbg_pmu("cmd post PMU_PG_ELPG_CMD_DISALLOW"); | 4948 | gk20a_dbg_pmu("cmd post PMU_PG_ELPG_CMD_DISALLOW"); |
4946 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, | 4949 | gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, |
4947 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, | 4950 | PMU_COMMAND_QUEUE_HPQ, pmu_handle_pg_elpg_msg, |
4948 | cb_param, &seq, ~0); | 4951 | pmu, &seq, ~0); |
4949 | 4952 | ||
4950 | pmu_wait_message_cond(pmu, | 4953 | pmu_wait_message_cond(pmu, |
4951 | gk20a_get_gr_idle_timeout(g), | 4954 | gk20a_get_gr_idle_timeout(g), |
4952 | wait_msg_cond_ptr, wait_msg_cond); | 4955 | ptr, PMU_ELPG_STAT_OFF); |
4953 | if (*wait_msg_cond_ptr != wait_msg_cond) { | 4956 | if (*ptr != PMU_ELPG_STAT_OFF) { |
4954 | gk20a_err(dev_from_gk20a(g), | 4957 | gk20a_err(dev_from_gk20a(g), |
4955 | "ELPG_DISALLOW_ACK failed"); | 4958 | "ELPG_DISALLOW_ACK failed"); |
4956 | pmu_dump_elpg_stats(pmu); | 4959 | pmu_dump_elpg_stats(pmu); |
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h index d7ab928b..0a1d2ba3 100644 --- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.h | |||
@@ -748,6 +748,7 @@ struct pmu_gk20a { | |||
748 | u32 elpg_stat; | 748 | u32 elpg_stat; |
749 | 749 | ||
750 | u32 mscg_stat; | 750 | u32 mscg_stat; |
751 | u32 mscg_transition_state; | ||
751 | 752 | ||
752 | int pmu_state; | 753 | int pmu_state; |
753 | 754 | ||