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authorAlex Waterman <alexw@nvidia.com>2018-01-22 19:30:53 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2018-05-07 07:41:26 -0400
commit6e739d924fe9b778fa82396e0e941143f498acb8 (patch)
treef112ede8573c2f8bf76e0bdaadf33c6c71343820 /drivers/gpu
parente6b3bb4e6b3d4013f83ba6d31c780947f16cf410 (diff)
gpu: nvgpu: Userspace POSIX support
Add support for compiling nvgpu in a POSIX compliant userspace. This code adds all of the necessary abstraction interfaces (mostly stubbed) to enabled extremely limited and basic functionality in nvgpu. The goal of this code is to facilitate unit testing of the nvgpu common core. By doing this in userspace it is much easier to write tests that rely on very particular states within nvgpu since a user can very precisely control the state of nvgpu. JIRA NVGPU-525 Change-Id: I30e95016df14997d951075777e0585f912dc5960 Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1683914 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/nvgpu/Makefile.interface.tmk27
-rw-r--r--drivers/gpu/nvgpu/Makefile.sources209
-rw-r--r--drivers/gpu/nvgpu/Makefile.tmk34
-rw-r--r--drivers/gpu/nvgpu/common/posix/bitmap.c268
-rw-r--r--drivers/gpu/nvgpu/common/posix/bug.c67
-rw-r--r--drivers/gpu/nvgpu/common/posix/channel.c32
-rw-r--r--drivers/gpu/nvgpu/common/posix/clk_arb.c148
-rw-r--r--drivers/gpu/nvgpu/common/posix/cond.c55
-rw-r--r--drivers/gpu/nvgpu/common/posix/dma.c220
-rw-r--r--drivers/gpu/nvgpu/common/posix/error_notifier.c40
-rw-r--r--drivers/gpu/nvgpu/common/posix/firmware.c35
-rw-r--r--drivers/gpu/nvgpu/common/posix/fuse.c54
-rw-r--r--drivers/gpu/nvgpu/common/posix/io.c82
-rw-r--r--drivers/gpu/nvgpu/common/posix/kmem.c134
-rw-r--r--drivers/gpu/nvgpu/common/posix/lock.c79
-rw-r--r--drivers/gpu/nvgpu/common/posix/log.c95
-rw-r--r--drivers/gpu/nvgpu/common/posix/nvgpu.c137
-rw-r--r--drivers/gpu/nvgpu/common/posix/nvlink.c33
-rw-r--r--drivers/gpu/nvgpu/common/posix/os_posix.h32
-rw-r--r--drivers/gpu/nvgpu/common/posix/posix-comptags.c49
-rw-r--r--drivers/gpu/nvgpu/common/posix/posix-nvgpu_mem.c209
-rw-r--r--drivers/gpu/nvgpu/common/posix/posix-vm.c52
-rw-r--r--drivers/gpu/nvgpu/common/posix/rwsem.c117
-rw-r--r--drivers/gpu/nvgpu/common/posix/soc.c48
-rw-r--r--drivers/gpu/nvgpu/common/posix/stubs.c32
-rw-r--r--drivers/gpu/nvgpu/common/posix/thread.c96
-rw-r--r--drivers/gpu/nvgpu/common/posix/timers.c169
-rw-r--r--drivers/gpu/nvgpu/common/posix/tsg.c28
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/atomic.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/barrier.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/bitops.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/bsearch.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/bug.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/circ_buf.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/cond.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/kmem.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/lock.h4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/log.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/log2.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h191
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/barrier.h44
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h92
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/bug.h56
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/circ_buf.h44
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/cond.h59
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/kmem.h36
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/lock.h69
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/log2.h37
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/nvgpu_mem.h32
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/probe.h31
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/rwsem.h35
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/sizes.h38
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/sort.h35
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/thread.h51
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/types.h219
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/posix/vm.h41
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/rwsem.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/sizes.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/sort.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/thread.h4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/types.h2
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/vm.h2
-rw-r--r--drivers/gpu/nvgpu/libnvgpu-drv.export1581
64 files changed, 5310 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.interface.tmk b/drivers/gpu/nvgpu/Makefile.interface.tmk
new file mode 100644
index 00000000..f836de19
--- /dev/null
+++ b/drivers/gpu/nvgpu/Makefile.interface.tmk
@@ -0,0 +1,27 @@
1################################### tell Emacs this is a -*- makefile-gmake -*-
2#
3# Copyright (c) 2018, NVIDIA CORPORATION. All Rights Reserved.
4#
5# NVIDIA CORPORATION and its licensors retain all intellectual property
6# and proprietary rights in and to this software, related documentation
7# and any modifications thereto. Any use, reproduction, disclosure or
8# distribution of this software and related documentation without an express
9# license agreement from NVIDIA CORPORATION is strictly prohibited.
10#
11# tmake for SW Mobile component makefile
12#
13# libnvgpu-drv interface makefile fragment
14#
15###############################################################################
16
17ifdef NV_INTERFACE_FLAG_SHARED_LIBRARY_SECTION
18NV_INTERFACE_NAME := nvgpu-drv
19NV_INTERFACE_EXPORTS := libnvgpu-drv
20NV_INTERFACE_PUBLIC_INCLUDES := . include
21endif
22
23# Local Variables:
24# indent-tabs-mode: t
25# tab-width: 8
26# End:
27# vi: set tabstop=8 noexpandtab:
diff --git a/drivers/gpu/nvgpu/Makefile.sources b/drivers/gpu/nvgpu/Makefile.sources
new file mode 100644
index 00000000..676ca05b
--- /dev/null
+++ b/drivers/gpu/nvgpu/Makefile.sources
@@ -0,0 +1,209 @@
1# -*- mode: makefile -*-
2#
3# Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
4#
5# Permission is hereby granted, free of charge, to any person obtaining a
6# copy of this software and associated documentation files (the "Software"),
7# to deal in the Software without restriction, including without limitation
8# the rights to use, copy, modify, merge, publish, distribute, sublicense,
9# and/or sell copies of the Software, and to permit persons to whom the
10# Software is furnished to do so, subject to the following conditions:
11#
12# The above copyright notice and this permission notice shall be included in
13# all copies or substantial portions of the Software.
14#
15# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18# THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20# FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21# DEALINGS IN THE SOFTWARE.
22
23srcs := common/mm/nvgpu_allocator.c \
24 common/mm/bitmap_allocator.c \
25 common/mm/buddy_allocator.c \
26 common/mm/page_allocator.c \
27 common/mm/lockless_allocator.c \
28 common/mm/gmmu.c \
29 common/mm/pd_cache.c \
30 common/mm/vm.c \
31 common/mm/vm_area.c \
32 common/mm/nvgpu_mem.c \
33 common/mm/comptags.c \
34 common/mm/mm.c \
35 common/bus.c \
36 common/enabled.c \
37 common/pramin.c \
38 common/semaphore.c \
39 common/as.c \
40 common/rbtree.c \
41 common/ltc.c \
42 common/vbios/bios.c \
43 common/falcon/falcon.c \
44 common/pmu/pmu.c \
45 common/pmu/pmu_ipc.c \
46 common/pmu/pmu_fw.c \
47 common/pmu/pmu_pg.c \
48 common/pmu/pmu_perfmon.c \
49 common/pmu/pmu_debug.c \
50 common/posix/nvgpu.c \
51 common/posix/bitmap.c \
52 common/posix/bug.c \
53 common/posix/log.c \
54 common/posix/kmem.c \
55 common/posix/io.c \
56 common/posix/posix-nvgpu_mem.c \
57 common/posix/dma.c \
58 common/posix/posix-vm.c \
59 common/posix/timers.c \
60 common/posix/posix-comptags.c \
61 common/posix/firmware.c \
62 common/posix/soc.c \
63 common/posix/rwsem.c \
64 common/posix/cond.c \
65 common/posix/thread.c \
66 common/posix/error_notifier.c \
67 common/posix/fuse.c \
68 common/posix/clk_arb.c \
69 common/posix/channel.c \
70 common/posix/tsg.c \
71 common/posix/nvlink.c \
72 common/posix/lock.c \
73 common/posix/stubs.c \
74 boardobj/boardobj.c \
75 boardobj/boardobjgrp.c \
76 boardobj/boardobjgrpmask.c \
77 boardobj/boardobjgrp_e255.c \
78 boardobj/boardobjgrp_e32.c \
79 pstate/pstate.c \
80 volt/volt_dev.c \
81 volt/volt_pmu.c \
82 volt/volt_policy.c \
83 volt/volt_rail.c \
84 clk/clk.c \
85 clk/clk_domain.c \
86 clk/clk_fll.c \
87 clk/clk_freq_controller.c \
88 clk/clk_prog.c \
89 clk/clk_vf_point.c \
90 clk/clk_vin.c \
91 therm/thrm.c \
92 therm/thrmchannel.c \
93 therm/thrmdev.c \
94 therm/thrmpmu.c \
95 perf/perf.c \
96 perf/vfe_equ.c \
97 perf/vfe_var.c \
98 pmgr/pmgr.c \
99 pmgr/pmgrpmu.c \
100 pmgr/pwrdev.c \
101 pmgr/pwrmonitor.c \
102 pmgr/pwrpolicy.c \
103 lpwr/lpwr.c \
104 lpwr/rppg.c \
105 gk20a/gk20a.c \
106 gk20a/bus_gk20a.c \
107 gk20a/pramin_gk20a.c \
108 gk20a/ce2_gk20a.c \
109 gk20a/fifo_gk20a.c \
110 gk20a/channel_gk20a.c \
111 gk20a/channel_sync_gk20a.c \
112 gk20a/dbg_gpu_gk20a.c \
113 gk20a/regops_gk20a.c \
114 gk20a/gr_gk20a.c \
115 gk20a/mm_gk20a.c \
116 gk20a/pmu_gk20a.c \
117 gk20a/flcn_gk20a.c \
118 gk20a/priv_ring_gk20a.c \
119 gk20a/fence_gk20a.c \
120 gk20a/therm_gk20a.c \
121 gk20a/gr_ctx_gk20a_sim.c \
122 gk20a/gr_ctx_gk20a.c \
123 gk20a/gk20a_gating_reglist.c \
124 gk20a/fb_gk20a.c \
125 gk20a/hal.c \
126 gk20a/tsg_gk20a.c \
127 gk20a/mc_gk20a.c \
128 gm20b/hal_gm20b.c \
129 gm20b/bus_gm20b.c \
130 gm20b/ltc_gm20b.c \
131 gm20b/gr_gm20b.c \
132 gm20b/clk_gm20b.c \
133 gm20b/fb_gm20b.c \
134 gm20b/fifo_gm20b.c \
135 gm20b/gr_ctx_gm20b.c \
136 gm20b/gm20b_gating_reglist.c \
137 gm20b/acr_gm20b.c \
138 gm20b/pmu_gm20b.c \
139 gm20b/mm_gm20b.c \
140 gm20b/regops_gm20b.c \
141 gm20b/therm_gm20b.c \
142 gm20b/fuse_gm20b.c \
143 gp10b/gr_gp10b.c \
144 gp10b/gr_ctx_gp10b.c \
145 gp10b/ce_gp10b.c \
146 gp10b/mc_gp10b.c \
147 gp10b/fifo_gp10b.c \
148 gp10b/ltc_gp10b.c \
149 gp10b/mm_gp10b.c \
150 gp10b/fb_gp10b.c \
151 gp10b/pmu_gp10b.c \
152 gp10b/hal_gp10b.c \
153 gp10b/rpfb_gp10b.c \
154 gp10b/gp10b_gating_reglist.c \
155 gp10b/regops_gp10b.c \
156 gp10b/therm_gp10b.c \
157 gp10b/fecs_trace_gp10b.c \
158 gp10b/priv_ring_gp10b.c \
159 gp10b/gp10b.c \
160 gp10b/fuse_gp10b.c \
161 gv11b/gv11b.c \
162 gv11b/dbg_gpu_gv11b.c \
163 gv11b/mc_gv11b.c \
164 gv11b/ltc_gv11b.c \
165 gv11b/hal_gv11b.c \
166 gv11b/gv11b_gating_reglist.c \
167 gv11b/gr_gv11b.c \
168 gv11b/fb_gv11b.c \
169 gv11b/fifo_gv11b.c \
170 gv11b/mm_gv11b.c \
171 gv11b/ce_gv11b.c \
172 gv11b/gr_ctx_gv11b.c \
173 gv11b/pmu_gv11b.c \
174 gv11b/acr_gv11b.c \
175 gv11b/subctx_gv11b.c \
176 gv11b/regops_gv11b.c \
177 gv11b/therm_gv11b.c \
178 gp106/hal_gp106.c \
179 gp106/mm_gp106.c \
180 gp106/flcn_gp106.c \
181 gp106/pmu_gp106.c \
182 gp106/mclk_gp106.c \
183 gp106/gr_gp106.c \
184 gp106/gr_ctx_gp106.c \
185 gp106/acr_gp106.c \
186 gp106/sec2_gp106.c \
187 gp106/fifo_gp106.c \
188 gp106/fb_gp106.c \
189 gp106/regops_gp106.c \
190 gp106/bios_gp106.c \
191 gp106/fuse_gp106.c \
192 gp106/clk_gp106.c \
193 gp106/clk_arb_gp106.c \
194 gp106/gp106_gating_reglist.c \
195 gp106/xve_gp106.c \
196 gp106/therm_gp106.c \
197 gv100/mm_gv100.c \
198 gv100/gr_ctx_gv100.c \
199 gv100/fb_gv100.c \
200 gv100/bios_gv100.c \
201 gv100/fifo_gv100.c \
202 gv100/gr_gv100.c \
203 gv100/regops_gv100.c \
204 gv100/flcn_gv100.c \
205 gv100/mc_gv100.c \
206 gv100/nvlink_gv100.c \
207 gv100/hal_gv100.c \
208 gv100/pmu_gv100.c \
209 gv100/gv100_gating_reglist.c
diff --git a/drivers/gpu/nvgpu/Makefile.tmk b/drivers/gpu/nvgpu/Makefile.tmk
new file mode 100644
index 00000000..25775d39
--- /dev/null
+++ b/drivers/gpu/nvgpu/Makefile.tmk
@@ -0,0 +1,34 @@
1################################### tell Emacs this is a -*- makefile-gmake -*-
2#
3# Copyright (c) 2018 NVIDIA CORPORATION. All Rights Reserved.
4#
5# NVIDIA CORPORATION and its licensors retain all intellectual property
6# and proprietary rights in and to this software, related documentation
7# and any modifications thereto. Any use, reproduction, disclosure or
8# distribution of this software and related documentation without an express
9# license agreement from NVIDIA CORPORATION is strictly prohibited.
10#
11# tmake for SW Mobile component makefile
12#
13###############################################################################
14
15ifdef NV_COMPONENT_FLAG_SHARED_LIBRARY_SECTION
16include $(NV_BUILD_START_COMPONENT)
17
18include $(NV_COMPONENT_DIR)/Makefile.sources
19
20NV_COMPONENT_NAME := nvgpu-drv
21NV_COMPONENT_OWN_INTERFACE_DIR := .
22NV_COMPONENT_SOURCES := $(srcs)
23NV_COMPONENT_INCLUDES := . include ../../../include
24NV_COMPONENT_SYSTEM_SHARED_LIBRARIES += pthread
25NV_COMPONENT_CFLAGS += -D__NVGPU_POSIX__
26
27include $(NV_BUILD_SHARED_LIBRARY)
28endif
29
30# Local Variables:
31# indent-tabs-mode: t
32# tab-width: 8
33# End:
34# vi: set tabstop=8 noexpandtab:
diff --git a/drivers/gpu/nvgpu/common/posix/bitmap.c b/drivers/gpu/nvgpu/common/posix/bitmap.c
new file mode 100644
index 00000000..51361777
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/bitmap.c
@@ -0,0 +1,268 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <stdio.h>
24#include <stdlib.h>
25
26#include <nvgpu/posix/bitops.h>
27#include <nvgpu/posix/atomic.h>
28
29#define BIT_MASK(nr) (1UL << ((nr) % BITS_PER_LONG))
30#define BIT_WORD(nr) ((nr) / BITS_PER_LONG)
31
32unsigned long __nvgpu_posix_fls(unsigned long word)
33{
34 int num = BITS_PER_LONG - 1;
35
36#if BITS_PER_LONG == 64
37 if (!(word & (~0ul << 32))) {
38 num -= 32;
39 word <<= 32;
40 }
41#endif
42 if (!(word & (~0ul << (BITS_PER_LONG-16)))) {
43 num -= 16;
44 word <<= 16;
45 }
46 if (!(word & (~0ul << (BITS_PER_LONG-8)))) {
47 num -= 8;
48 word <<= 8;
49 }
50 if (!(word & (~0ul << (BITS_PER_LONG-4)))) {
51 num -= 4;
52 word <<= 4;
53 }
54 if (!(word & (~0ul << (BITS_PER_LONG-2)))) {
55 num -= 2;
56 word <<= 2;
57 }
58 if (!(word & (~0ul << (BITS_PER_LONG-1))))
59 num -= 1;
60 return num;
61}
62
63unsigned long __nvgpu_posix_ffs(unsigned long word)
64{
65 int num = 0;
66
67#if BITS_PER_LONG == 64
68 if ((word & 0xffffffff) == 0) {
69 num += 32;
70 word >>= 32;
71 }
72#endif
73 if ((word & 0xffff) == 0) {
74 num += 16;
75 word >>= 16;
76 }
77 if ((word & 0xff) == 0) {
78 num += 8;
79 word >>= 8;
80 }
81 if ((word & 0xf) == 0) {
82 num += 4;
83 word >>= 4;
84 }
85 if ((word & 0x3) == 0) {
86 num += 2;
87 word >>= 2;
88 }
89 if ((word & 0x1) == 0)
90 num += 1;
91
92 return num;
93}
94
95static unsigned long __find_next_bit(const unsigned long *addr,
96 unsigned long n,
97 unsigned long start,
98 bool invert)
99{
100 unsigned long idx;
101 unsigned long w;
102 unsigned long start_mask;
103
104 /*
105 * We make a mask we can XOR into the word so that we can invert the
106 * word without requiring a branch. I.e instead of doing:
107 *
108 * w = invert ? ~addr[idx] : addr[idx]
109 *
110 * We can do:
111 *
112 * w = addr[idx] ^= invert_mask
113 *
114 * This saves us a branch every iteration through the loop. Now we can
115 * always just look for 1s.
116 */
117 unsigned long invert_mask = invert ? ~0UL : 0UL;
118
119 if (start >= n)
120 return n;
121
122 start_mask = ~0UL << (start & (BITS_PER_LONG - 1));
123
124 idx = start / BITS_PER_LONG;
125 w = (addr[idx] ^ invert_mask) & start_mask;
126
127 start = round_up(start, BITS_PER_LONG);
128
129 /*
130 * Find the first non-zero word taking into account start and
131 * invert.
132 */
133 while (!w) {
134 idx++;
135 start += BITS_PER_LONG;
136
137 w = addr[idx] ^ invert_mask;
138 }
139
140 return min(n, ffs(w) + idx * BITS_PER_LONG);
141}
142
143unsigned long find_first_bit(const unsigned long *addr, unsigned long size)
144{
145 return __find_next_bit(addr, size, 0, false);
146}
147
148unsigned long find_first_zero_bit(const unsigned long *addr, unsigned long size)
149{
150 return __find_next_bit(addr, size, 0, true);
151}
152
153unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
154 unsigned long offset)
155{
156 return __find_next_bit(addr, size, offset, false);
157}
158
159static unsigned long find_next_zero_bit(const unsigned long *addr,
160 unsigned long size,
161 unsigned long offset)
162{
163 return __find_next_bit(addr, size, offset, true);
164}
165
166void bitmap_set(unsigned long *map, unsigned int start, int len)
167{
168 unsigned int end = start + len;
169
170 /*
171 * Super slow naive implementation. But speed isn't what matters here.
172 */
173 while (start < end)
174 set_bit(start++, map);
175}
176
177void bitmap_clear(unsigned long *map, unsigned int start, int len)
178{
179 unsigned int end = start + len;
180
181 while (start < end)
182 clear_bit(start++, map);
183}
184
185/*
186 * This is essentially a find-first-fit allocator: this searches a bitmap for
187 * the first space that is large enough to satisfy the requested size of bits.
188 * That means that this is not a vary smart allocator. But it is fast relative
189 * to an allocator that goes looking for an optimal location.
190 */
191unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
192 unsigned long size,
193 unsigned long start,
194 unsigned int nr,
195 unsigned long align_mask,
196 unsigned long align_offset)
197{
198 unsigned long offs;
199
200 while (start + nr <= size) {
201 start = find_next_zero_bit(map, size, start);
202
203 start = ALIGN_MASK(start + align_offset, align_mask) -
204 align_offset;
205
206 /*
207 * Not enough space left to satisfy the requested area.
208 */
209 if ((start + nr) > size)
210 return size;
211
212 offs = find_next_bit(map, size, start);
213
214 if ((offs - start) >= nr)
215 return start;
216
217 start = offs + 1;
218 }
219
220 return size;
221}
222
223unsigned long bitmap_find_next_zero_area(unsigned long *map,
224 unsigned long size,
225 unsigned long start,
226 unsigned int nr,
227 unsigned long align_mask)
228{
229 return bitmap_find_next_zero_area_off(map, size, start, nr,
230 align_mask, 0);
231}
232
233bool test_bit(int nr, const volatile unsigned long *addr)
234{
235 return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1)));
236}
237
238bool test_and_set_bit(int nr, volatile unsigned long *addr)
239{
240 unsigned long mask = BIT_MASK(nr);
241 volatile unsigned long *p = addr + BIT_WORD(nr);
242
243 return !!(__sync_fetch_and_or(p, mask) & mask);
244}
245
246bool test_and_clear_bit(int nr, volatile unsigned long *addr)
247{
248 unsigned long mask = BIT_MASK(nr);
249 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
250
251 return !!(__sync_fetch_and_and(p, ~mask) & mask);
252}
253
254void set_bit(int nr, volatile unsigned long *addr)
255{
256 unsigned long mask = BIT_MASK(nr);
257 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
258
259 __atomic_or(p, mask);
260}
261
262void clear_bit(int nr, volatile unsigned long *addr)
263{
264 unsigned long mask = BIT_MASK(nr);
265 unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr);
266
267 __atomic_and(p, ~mask);
268}
diff --git a/drivers/gpu/nvgpu/common/posix/bug.c b/drivers/gpu/nvgpu/common/posix/bug.c
new file mode 100644
index 00000000..64f4a6f6
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/bug.c
@@ -0,0 +1,67 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/log.h>
24
25#include <nvgpu/posix/bug.h>
26
27__attribute__ ((noreturn))
28static void __hang(void)
29{
30 nvgpu_err(NULL, "Hanging!");
31
32 while (1)
33 ;
34}
35
36static void __dump_stack(unsigned int skip_frames)
37{
38 return;
39}
40
41void dump_stack(void)
42{
43 __dump_stack(0);
44}
45
46/*
47 * Ahhh! A bug!
48 */
49void __bug(const char *fmt, ...)
50{
51 nvgpu_err(NULL, "BUG detected!");
52
53 __hang();
54}
55
56bool __warn(bool cond, const char *fmt, ...)
57{
58 if (!cond)
59 goto done;
60
61 nvgpu_warn(NULL, "WARNING detected!");
62
63 dump_stack();
64
65done:
66 return cond;
67}
diff --git a/drivers/gpu/nvgpu/common/posix/channel.c b/drivers/gpu/nvgpu/common/posix/channel.c
new file mode 100644
index 00000000..05697159
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/channel.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include "gk20a/channel_gk20a.h"
24
25u32 nvgpu_get_gpfifo_entry_size(void)
26{
27 /*
28 * There is no struct nvgpu_gpfifo for us to use yet. But when it's
29 * defined in userspace this is how big it will be.
30 */
31 return 8;
32}
diff --git a/drivers/gpu/nvgpu/common/posix/clk_arb.c b/drivers/gpu/nvgpu/common/posix/clk_arb.c
new file mode 100644
index 00000000..f41383cd
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/clk_arb.c
@@ -0,0 +1,148 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/clk_arb.h>
24
25/**
26 * Stub imlementation of the clk_arb code. Yikes. Much of this probably could be
27 * commonized if one were to think through the implementation but that is
28 * probably weeks of work at a minimum.
29 *
30 * So for POSIX it will be stubbed.
31 */
32
33int nvgpu_clk_arb_init_arbiter(struct gk20a *g)
34{
35 return -ENOSYS;
36}
37
38int nvgpu_clk_arb_get_arbiter_clk_range(struct gk20a *g, u32 api_domain,
39 u16 *min_mhz, u16 *max_mhz)
40{
41 return -ENOSYS;
42}
43
44int nvgpu_clk_arb_get_arbiter_actual_mhz(struct gk20a *g,
45 u32 api_domain, u16 *actual_mhz)
46{
47 return -ENOSYS;
48}
49
50int nvgpu_clk_arb_get_arbiter_effective_mhz(struct gk20a *g,
51 u32 api_domain, u16 *effective_mhz)
52{
53 return -ENOSYS;
54}
55
56
57int nvgpu_clk_arb_get_arbiter_clk_f_points(struct gk20a *g,
58 u32 api_domain,
59 u32 *max_points, u16 *fpoints)
60{
61 return -ENOSYS;
62}
63
64u32 nvgpu_clk_arb_get_arbiter_clk_domains(struct gk20a *g)
65{
66 return 0;
67}
68
69bool nvgpu_clk_arb_is_valid_domain(struct gk20a *g, u32 api_domain)
70{
71 return false;
72}
73
74void nvgpu_clk_arb_cleanup_arbiter(struct gk20a *g)
75{
76}
77
78int nvgpu_clk_arb_install_session_fd(struct gk20a *g,
79 struct nvgpu_clk_session *session)
80{
81 return -ENOSYS;
82}
83
84
85int nvgpu_clk_arb_init_session(struct gk20a *g,
86 struct nvgpu_clk_session **_session)
87{
88 return -ENOSYS;
89}
90
91void nvgpu_clk_arb_release_session(struct gk20a *g,
92 struct nvgpu_clk_session *session)
93{
94}
95
96int nvgpu_clk_arb_commit_request_fd(struct gk20a *g,
97 struct nvgpu_clk_session *session,
98 int request_fd)
99{
100 return -ENOSYS;
101}
102
103int nvgpu_clk_arb_set_session_target_mhz(struct nvgpu_clk_session *session,
104 int fd, u32 api_domain, u16 target_mhz)
105{
106 return -ENOSYS;
107}
108
109int nvgpu_clk_arb_get_session_target_mhz(struct nvgpu_clk_session *session,
110 u32 api_domain, u16 *target_mhz)
111{
112 return -ENOSYS;
113}
114
115int nvgpu_clk_arb_install_event_fd(struct gk20a *g,
116 struct nvgpu_clk_session *session,
117 int *event_fd, u32 alarm_mask)
118{
119 return -ENOSYS;
120}
121
122int nvgpu_clk_arb_install_request_fd(struct gk20a *g,
123 struct nvgpu_clk_session *session,
124 int *event_fd)
125{
126 return -ENOSYS;
127}
128
129void nvgpu_clk_arb_schedule_vf_table_update(struct gk20a *g)
130{
131}
132
133int nvgpu_clk_arb_get_current_pstate(struct gk20a *g)
134{
135 return -ENOSYS;
136}
137
138void nvgpu_clk_arb_pstate_change_lock(struct gk20a *g, bool lock)
139{
140}
141
142void nvgpu_clk_arb_send_thermal_alarm(struct gk20a *g)
143{
144}
145
146void nvgpu_clk_arb_schedule_alarm(struct gk20a *g, u32 alarm)
147{
148}
diff --git a/drivers/gpu/nvgpu/common/posix/cond.c b/drivers/gpu/nvgpu/common/posix/cond.c
new file mode 100644
index 00000000..ca8a2c4a
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/cond.c
@@ -0,0 +1,55 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/cond.h>
24
25#include <nvgpu/posix/cond.h>
26
27int nvgpu_cond_init(struct nvgpu_cond *cond)
28{
29 return -ENOSYS;
30}
31
32int nvgpu_cond_signal(struct nvgpu_cond *cond)
33{
34 return -ENOSYS;
35}
36
37int nvgpu_cond_signal_interruptible(struct nvgpu_cond *cond)
38{
39 return -ENOSYS;
40}
41
42int nvgpu_cond_broadcast(struct nvgpu_cond *cond)
43{
44 return -ENOSYS;
45}
46
47int nvgpu_cond_broadcast_interruptible(struct nvgpu_cond *cond)
48{
49 return -ENOSYS;
50}
51
52void nvgpu_cond_destroy(struct nvgpu_cond *cond)
53{
54
55}
diff --git a/drivers/gpu/nvgpu/common/posix/dma.c b/drivers/gpu/nvgpu/common/posix/dma.c
new file mode 100644
index 00000000..23f59501
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/dma.c
@@ -0,0 +1,220 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <stdlib.h>
24
25#include <nvgpu/mm.h>
26#include <nvgpu/vm.h>
27#include <nvgpu/bug.h>
28#include <nvgpu/dma.h>
29#include <nvgpu/gmmu.h>
30#include <nvgpu/nvgpu_mem.h>
31#include <nvgpu/enabled.h>
32
33/*
34 * In userspace vidmem vs sysmem is just a difference in what is placed in the
35 * aperture field.
36 */
37static int __nvgpu_do_dma_alloc(struct gk20a *g, unsigned long flags,
38 size_t size, struct nvgpu_mem *mem,
39 enum nvgpu_aperture ap)
40{
41 void *memory = malloc(mem->aligned_size);
42
43 if (memory == NULL)
44 return -ENOMEM;
45
46 mem->cpu_va = memory;
47 mem->aperture = ap;
48 mem->size = size;
49 mem->aligned_size = PAGE_ALIGN(size);
50 mem->gpu_va = 0ULL;
51 mem->skip_wmb = true;
52 mem->vidmem_alloc = NULL;
53 mem->allocator = NULL;
54
55 return 0;
56}
57
58bool nvgpu_iommuable(struct gk20a *g)
59{
60 return false;
61}
62
63int nvgpu_dma_alloc(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
64{
65 return nvgpu_dma_alloc_flags(g, 0, size, mem);
66}
67
68int nvgpu_dma_alloc_flags(struct gk20a *g, unsigned long flags, size_t size,
69 struct nvgpu_mem *mem)
70{
71 if (!nvgpu_is_enabled(g, NVGPU_MM_UNIFIED_MEMORY)) {
72 /*
73 * First try vidmem. Obviously in userspace there's no such
74 * thing as vidmem per se but we will mark the aperture as
75 * vidmem.
76 */
77 int err = nvgpu_dma_alloc_flags_vid(g, 0, size, mem);
78
79 if (!err)
80 return 0;
81 /*
82 * Fall back to sysmem (which may then also fail) in case
83 * vidmem is exhausted.
84 */
85 }
86
87 return nvgpu_dma_alloc_flags_sys(g, flags, size, mem);
88
89}
90
91int nvgpu_dma_alloc_sys(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
92{
93 return nvgpu_dma_alloc_flags_sys(g, 0, size, mem);
94}
95
96int nvgpu_dma_alloc_flags_sys(struct gk20a *g, unsigned long flags,
97 size_t size, struct nvgpu_mem *mem)
98{
99 return __nvgpu_do_dma_alloc(g, flags, size, mem, APERTURE_SYSMEM);
100}
101
102int nvgpu_dma_alloc_vid(struct gk20a *g, size_t size, struct nvgpu_mem *mem)
103{
104 return nvgpu_dma_alloc_flags_vid(g, 0, size, mem);
105}
106
107int nvgpu_dma_alloc_flags_vid(struct gk20a *g, unsigned long flags,
108 size_t size, struct nvgpu_mem *mem)
109{
110 return __nvgpu_do_dma_alloc(g, flags, size, mem, APERTURE_VIDMEM);
111}
112
113int nvgpu_dma_alloc_flags_vid_at(struct gk20a *g, unsigned long flags,
114 size_t size, struct nvgpu_mem *mem, u64 at)
115{
116 BUG();
117
118 return 0;
119}
120
121void nvgpu_dma_free(struct gk20a *g, struct nvgpu_mem *mem)
122{
123 if (!(mem->mem_flags & NVGPU_MEM_FLAG_SHADOW_COPY))
124 free(mem->cpu_va);
125
126 memset(mem, 0, sizeof(*mem));
127}
128
129int nvgpu_dma_alloc_map(struct vm_gk20a *vm, size_t size,
130 struct nvgpu_mem *mem)
131{
132 return nvgpu_dma_alloc_map_flags(vm, 0, size, mem);
133}
134
135int nvgpu_dma_alloc_map_flags(struct vm_gk20a *vm, unsigned long flags,
136 size_t size, struct nvgpu_mem *mem)
137{
138 if (!nvgpu_is_enabled(gk20a_from_vm(vm), NVGPU_MM_UNIFIED_MEMORY)) {
139 int err = nvgpu_dma_alloc_map_flags_vid(vm,
140 flags | NVGPU_DMA_NO_KERNEL_MAPPING,
141 size, mem);
142
143 if (!err)
144 return 0;
145 /*
146 * Fall back to sysmem (which may then also fail) in case
147 * vidmem is exhausted.
148 */
149 }
150
151 return nvgpu_dma_alloc_map_flags_sys(vm, flags, size, mem);
152}
153
154int nvgpu_dma_alloc_map_sys(struct vm_gk20a *vm, size_t size,
155 struct nvgpu_mem *mem)
156{
157 return nvgpu_dma_alloc_map_flags_sys(vm, 0, size, mem);
158}
159
160int nvgpu_dma_alloc_map_flags_sys(struct vm_gk20a *vm, unsigned long flags,
161 size_t size, struct nvgpu_mem *mem)
162{
163 int err = nvgpu_dma_alloc_flags_sys(vm->mm->g, flags, size, mem);
164
165 if (err)
166 return err;
167
168 mem->gpu_va = nvgpu_gmmu_map(vm, mem, size, 0,
169 gk20a_mem_flag_none, false,
170 mem->aperture);
171 if (!mem->gpu_va) {
172 err = -ENOMEM;
173 goto fail_free;
174 }
175
176 return 0;
177
178fail_free:
179 nvgpu_dma_free(vm->mm->g, mem);
180 return err;
181}
182
183int nvgpu_dma_alloc_map_vid(struct vm_gk20a *vm, size_t size,
184 struct nvgpu_mem *mem)
185{
186 return nvgpu_dma_alloc_map_flags_vid(vm,
187 NVGPU_DMA_NO_KERNEL_MAPPING, size, mem);
188}
189
190int nvgpu_dma_alloc_map_flags_vid(struct vm_gk20a *vm, unsigned long flags,
191 size_t size, struct nvgpu_mem *mem)
192{
193 int err = nvgpu_dma_alloc_flags_vid(vm->mm->g, flags, size, mem);
194
195 if (err)
196 return err;
197
198 mem->gpu_va = nvgpu_gmmu_map(vm, mem, size, 0,
199 gk20a_mem_flag_none, false,
200 mem->aperture);
201 if (!mem->gpu_va) {
202 err = -ENOMEM;
203 goto fail_free;
204 }
205
206 return 0;
207
208fail_free:
209 nvgpu_dma_free(vm->mm->g, mem);
210 return err;
211}
212
213void nvgpu_dma_unmap_free(struct vm_gk20a *vm, struct nvgpu_mem *mem)
214{
215 if (mem->gpu_va)
216 nvgpu_gmmu_unmap(vm, mem, mem->gpu_va);
217 mem->gpu_va = 0;
218
219 nvgpu_dma_free(vm->mm->g, mem);
220}
diff --git a/drivers/gpu/nvgpu/common/posix/error_notifier.c b/drivers/gpu/nvgpu/common/posix/error_notifier.c
new file mode 100644
index 00000000..50b4f258
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/error_notifier.c
@@ -0,0 +1,40 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/error_notifier.h>
24
25void nvgpu_set_error_notifier_locked(struct channel_gk20a *ch, u32 error)
26{
27}
28
29void nvgpu_set_error_notifier(struct channel_gk20a *ch, u32 error)
30{
31}
32
33void nvgpu_set_error_notifier_if_empty(struct channel_gk20a *ch, u32 error)
34{
35}
36
37bool nvgpu_is_error_notifier_set(struct channel_gk20a *ch, u32 error_notifier)
38{
39 return false;
40}
diff --git a/drivers/gpu/nvgpu/common/posix/firmware.c b/drivers/gpu/nvgpu/common/posix/firmware.c
new file mode 100644
index 00000000..aedfef9f
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/firmware.c
@@ -0,0 +1,35 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/firmware.h>
24
25struct nvgpu_firmware *nvgpu_request_firmware(struct gk20a *g,
26 const char *fw_name,
27 int flags)
28{
29 return NULL;
30}
31
32void nvgpu_release_firmware(struct gk20a *g, struct nvgpu_firmware *fw)
33{
34 /* Noop. */
35}
diff --git a/drivers/gpu/nvgpu/common/posix/fuse.c b/drivers/gpu/nvgpu/common/posix/fuse.c
new file mode 100644
index 00000000..09ec36dc
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/fuse.c
@@ -0,0 +1,54 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/fuse.h>
24
25int nvgpu_tegra_get_gpu_speedo_id(struct gk20a *g)
26{
27 return 0;
28}
29
30void nvgpu_tegra_fuse_write_bypass(struct gk20a *g, u32 val)
31{
32}
33
34void nvgpu_tegra_fuse_write_access_sw(struct gk20a *g, u32 val)
35{
36}
37
38void nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(struct gk20a *g, u32 val)
39{
40}
41
42void nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable(struct gk20a *g, u32 val)
43{
44}
45
46int nvgpu_tegra_fuse_read_gcplex_config_fuse(struct gk20a *g, u32 *val)
47{
48 return -ENODEV;
49}
50
51int nvgpu_tegra_fuse_read_reserved_calib(struct gk20a *g, u32 *val)
52{
53 return -ENODEV;
54}
diff --git a/drivers/gpu/nvgpu/common/posix/io.c b/drivers/gpu/nvgpu/common/posix/io.c
new file mode 100644
index 00000000..ce018940
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/io.c
@@ -0,0 +1,82 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/io.h>
24#include <nvgpu/io_usermode.h>
25#include <nvgpu/bug.h>
26
27/*
28 * For now none of these make sense to execute in userspace. Eventually we
29 * may want to use these to verify certain register read/write sequences
30 * but for now, just hang.
31 */
32
33void nvgpu_writel(struct gk20a *g, u32 r, u32 v)
34{
35 BUG();
36}
37
38u32 nvgpu_readl(struct gk20a *g, u32 r)
39{
40 BUG();
41
42 return 0;
43}
44
45u32 __nvgpu_readl(struct gk20a *g, u32 r)
46{
47 BUG();
48
49 return 0;
50}
51
52void nvgpu_writel_check(struct gk20a *g, u32 r, u32 v)
53{
54 BUG();
55}
56
57void nvgpu_bar1_writel(struct gk20a *g, u32 b, u32 v)
58{
59 BUG();
60}
61
62u32 nvgpu_bar1_readl(struct gk20a *g, u32 b)
63{
64 BUG();
65
66 return 0;
67}
68
69bool nvgpu_io_exists(struct gk20a *g)
70{
71 return false;
72}
73
74bool nvgpu_io_valid_reg(struct gk20a *g, u32 r)
75{
76 return false;
77}
78
79void nvgpu_usermode_writel(struct gk20a *g, u32 r, u32 v)
80{
81 BUG();
82}
diff --git a/drivers/gpu/nvgpu/common/posix/kmem.c b/drivers/gpu/nvgpu/common/posix/kmem.c
new file mode 100644
index 00000000..3c0b9b66
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/kmem.c
@@ -0,0 +1,134 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <stdlib.h>
24
25#include <nvgpu/bug.h>
26#include <nvgpu/kmem.h>
27#include <nvgpu/types.h>
28
29#include <nvgpu/posix/kmem.h>
30
31struct nvgpu_kmem_cache {
32 size_t alloc_size;
33};
34
35/*
36 * kmem cache emulation: basically just do a regular malloc(). This is slower
37 * but should not affect a user of kmem cache in the slightest bit.
38 */
39struct nvgpu_kmem_cache *nvgpu_kmem_cache_create(struct gk20a *g, size_t size)
40{
41 struct nvgpu_kmem_cache *cache =
42 malloc(sizeof(struct nvgpu_kmem_cache));
43
44 if (cache != NULL)
45 return NULL;
46
47 cache->alloc_size = size;
48
49 return cache;
50}
51
52void nvgpu_kmem_cache_destroy(struct nvgpu_kmem_cache *cache)
53{
54 free(cache);
55}
56
57void *nvgpu_kmem_cache_alloc(struct nvgpu_kmem_cache *cache)
58{
59 return malloc(cache->alloc_size);
60}
61
62void nvgpu_kmem_cache_free(struct nvgpu_kmem_cache *cache, void *ptr)
63{
64 free(ptr);
65}
66
67void *__nvgpu_kmalloc(struct gk20a *g, size_t size, unsigned long ip)
68{
69 return malloc(size);
70}
71
72void *__nvgpu_kzalloc(struct gk20a *g, size_t size, unsigned long ip)
73{
74 return calloc(1, size);
75}
76
77void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, unsigned long ip)
78{
79 /*
80 * calloc() implicitly zeros mem. So calloc a single member size bytes
81 * long.
82 */
83 return calloc(n, size);
84}
85
86void __nvgpu_kfree(struct gk20a *g, void *addr)
87{
88 free(addr);
89}
90
91/*
92 * The concept of vmalloc() does not exist in userspace.
93 */
94void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, unsigned long ip)
95{
96 return __nvgpu_kmalloc(g, size, ip);
97}
98
99void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, unsigned long ip)
100{
101 return __nvgpu_kzalloc(g, size, ip);
102}
103
104void __nvgpu_vfree(struct gk20a *g, void *addr)
105{
106 __nvgpu_kfree(g, addr);
107}
108
109void *__nvgpu_big_alloc(struct gk20a *g, size_t size, bool clear)
110{
111 /*
112 * Since in userspace vmalloc() == kmalloc() == malloc() we can just
113 * reuse k[zm]alloc() for this.
114 */
115 return clear ?
116 __nvgpu_kzalloc(g, size, _THIS_IP_) :
117 __nvgpu_kmalloc(g, size, _THIS_IP_);
118}
119
120void nvgpu_big_free(struct gk20a *g, void *p)
121{
122 __nvgpu_kfree(g, p);
123}
124
125int nvgpu_kmem_init(struct gk20a *g)
126{
127 /* Nothing to init at the moment. */
128 return 0;
129}
130
131void nvgpu_kmem_fini(struct gk20a *g, int flags)
132{
133
134}
diff --git a/drivers/gpu/nvgpu/common/posix/lock.c b/drivers/gpu/nvgpu/common/posix/lock.c
new file mode 100644
index 00000000..bca0f04c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/lock.c
@@ -0,0 +1,79 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/lock.h>
24#include <nvgpu/posix/lock.h>
25
26int nvgpu_mutex_init(struct nvgpu_mutex *mutex)
27{
28 return pthread_mutex_init(&mutex->lock.mutex, NULL);
29}
30
31void nvgpu_mutex_acquire(struct nvgpu_mutex *mutex)
32{
33 __nvgpu_posix_lock_acquire(&mutex->lock);
34}
35
36void nvgpu_mutex_release(struct nvgpu_mutex *mutex)
37{
38 __nvgpu_posix_lock_release(&mutex->lock);
39}
40
41int nvgpu_mutex_tryacquire(struct nvgpu_mutex *mutex)
42{
43 return __nvgpu_posix_lock_try_acquire(&mutex->lock);
44}
45
46void nvgpu_mutex_destroy(struct nvgpu_mutex *mutex)
47{
48 pthread_mutex_destroy(&mutex->lock.mutex);
49}
50
51void nvgpu_spinlock_init(struct nvgpu_spinlock *spinlock)
52{
53 pthread_mutex_init(&spinlock->lock.mutex, NULL);
54}
55
56void nvgpu_spinlock_acquire(struct nvgpu_spinlock *spinlock)
57{
58 __nvgpu_posix_lock_acquire(&spinlock->lock);
59}
60
61void nvgpu_spinlock_release(struct nvgpu_spinlock *spinlock)
62{
63 __nvgpu_posix_lock_release(&spinlock->lock);
64}
65
66void nvgpu_raw_spinlock_init(struct nvgpu_raw_spinlock *spinlock)
67{
68 pthread_mutex_init(&spinlock->lock.mutex, NULL);
69}
70
71void nvgpu_raw_spinlock_acquire(struct nvgpu_raw_spinlock *spinlock)
72{
73 __nvgpu_posix_lock_acquire(&spinlock->lock);
74}
75
76void nvgpu_raw_spinlock_release(struct nvgpu_raw_spinlock *spinlock)
77{
78 __nvgpu_posix_lock_release(&spinlock->lock);
79}
diff --git a/drivers/gpu/nvgpu/common/posix/log.c b/drivers/gpu/nvgpu/common/posix/log.c
new file mode 100644
index 00000000..6bfb673c
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/log.c
@@ -0,0 +1,95 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/log.h>
24#include <nvgpu/types.h>
25
26#include "gk20a/gk20a.h"
27
28/*
29 * Define a length for log buffers. This is the buffer that the 'fmt, ...' part
30 * of __nvgpu_do_log_print() prints into.
31 */
32#define LOG_BUFFER_LENGTH 160
33
34/*
35 * Keep this roughly the same as the kernel log format.
36 */
37#define LOG_FMT "nvgpu: %s %33s:%-4d [%-4s] %s\n"
38
39u64 nvgpu_dbg_mask = NVGPU_DEFAULT_DBG_MASK;
40
41static const char *log_types[] = {
42 "ERR",
43 "WRN",
44 "DBG",
45 "INFO",
46};
47
48static inline const char *nvgpu_log_name(struct gk20a *g)
49{
50 return "gpu.USS";
51}
52
53static void __nvgpu_really_print_log(const char *gpu_name,
54 const char *func_name, int line,
55 enum nvgpu_log_type type, const char *log)
56{
57 const char *name = gpu_name ? gpu_name : "";
58 const char *log_type = log_types[type];
59
60 printf(LOG_FMT, name, func_name, line, log_type, log);
61}
62
63__attribute__((format (printf, 5, 6)))
64void __nvgpu_log_msg(struct gk20a *g, const char *func_name, int line,
65 enum nvgpu_log_type type, const char *fmt, ...)
66{
67 char log[LOG_BUFFER_LENGTH];
68 va_list args;
69
70 va_start(args, fmt);
71 vsnprintf(log, LOG_BUFFER_LENGTH, fmt, args);
72 va_end(args);
73
74 __nvgpu_really_print_log(nvgpu_log_name(g),
75 func_name, line, type, log);
76}
77
78__attribute__((format (printf, 5, 6)))
79void __nvgpu_log_dbg(struct gk20a *g, u64 log_mask,
80 const char *func_name, int line,
81 const char *fmt, ...)
82{
83 char log[LOG_BUFFER_LENGTH];
84 va_list args;
85
86 if ((log_mask & g->log_mask) == 0)
87 return;
88
89 va_start(args, fmt);
90 vsnprintf(log, LOG_BUFFER_LENGTH, fmt, args);
91 va_end(args);
92
93 __nvgpu_really_print_log(nvgpu_log_name(g),
94 func_name, line, NVGPU_DEBUG, log);
95}
diff --git a/drivers/gpu/nvgpu/common/posix/nvgpu.c b/drivers/gpu/nvgpu/common/posix/nvgpu.c
new file mode 100644
index 00000000..6f2a5fe9
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/nvgpu.c
@@ -0,0 +1,137 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <unistd.h>
24#include <stdlib.h>
25#include <pthread.h>
26
27#include <nvgpu/bug.h>
28#include <nvgpu/types.h>
29#include <nvgpu/atomic.h>
30#include <nvgpu/nvgpu_common.h>
31#include <nvgpu/os_sched.h>
32
33#include <nvgpu/posix/probe.h>
34
35#include "os_posix.h"
36
37#include "gk20a/gk20a.h"
38
39void nvgpu_wait_for_deferred_interrupts(struct gk20a *g)
40{
41 /*
42 * No interrupts in userspace so nothing to wait for.
43 */
44}
45
46int nvgpu_current_pid(struct gk20a *g)
47{
48 /*
49 * In the kernel this gets us the PID of the calling process for IOCTLs.
50 * But since we are in userspace this doesn't quite mean the same thing.
51 * This simply returns the PID of the currently running process.
52 */
53 return (int)getpid();
54}
55
56int nvgpu_current_tid(struct gk20a *g)
57{
58 /*
59 * In POSIX thread ID is not the same as a process ID. In Linux threads
60 * and processes are represented by the same thing, but userspace can't
61 * really rely on that.
62 *
63 * We can, however, get a pthread_t for a given thread. But this
64 * pthread_t need not have any relation to the underlying system's
65 * representation of "threads".
66 */
67 return (int)pthread_self();
68}
69
70/*
71 * Somewhat meaningless in userspace...
72 */
73void nvgpu_kernel_restart(void *cmd)
74{
75 BUG();
76}
77
78/*
79 * We have no runtime PM stuff in userspace so these are really just noops.
80 */
81void gk20a_busy_noresume(struct gk20a *g)
82{
83}
84
85void gk20a_idle_nosuspend(struct gk20a *g)
86{
87}
88
89int gk20a_busy(struct gk20a *g)
90{
91 nvgpu_atomic_inc(&g->usage_count);
92
93 return 0;
94}
95
96void gk20a_idle(struct gk20a *g)
97{
98 nvgpu_atomic_dec(&g->usage_count);
99}
100
101/*
102 * This function aims to initialize enough stuff to make unit testing worth
103 * while. There are several interfaces and APIs that rely on the struct gk20a's
104 * state in order to function: logging, for example, but there are many other
105 * things, too.
106 *
107 * Initialize as much of that as possible here. This is meant to be equivalent
108 * to the kernel space driver's probe function.
109 */
110struct gk20a *nvgpu_posix_probe(void)
111{
112 struct gk20a *g;
113 struct nvgpu_os_posix *p;
114 int err;
115
116 p = malloc(sizeof(*p));
117 if (p == NULL)
118 return NULL;
119
120 g = &p->g;
121
122 err = nvgpu_kmem_init(g);
123 if (err != 0)
124 goto fail;
125
126 return g;
127
128fail:
129 free(p);
130
131 return NULL;
132}
133
134void nvgpu_posix_cleanup(struct gk20a *g)
135{
136 nvgpu_kmem_fini(g, 0);
137}
diff --git a/drivers/gpu/nvgpu/common/posix/nvlink.c b/drivers/gpu/nvgpu/common/posix/nvlink.c
new file mode 100644
index 00000000..c830d6ed
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/nvlink.c
@@ -0,0 +1,33 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/nvlink.h>
24
25int nvgpu_nvlink_train(struct gk20a *g, u32 link_id, bool from_off)
26{
27 return -ENOSYS;
28}
29
30int nvgpu_nvlink_enumerate(struct gk20a *g)
31{
32 return -ENOSYS;
33}
diff --git a/drivers/gpu/nvgpu/common/posix/os_posix.h b/drivers/gpu/nvgpu/common/posix/os_posix.h
new file mode 100644
index 00000000..955186ef
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/os_posix.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_OS_POSIX_H__
24#define __NVGPU_OS_POSIX_H__
25
26#include "gk20a/gk20a.h"
27
28struct nvgpu_os_posix {
29 struct gk20a g;
30};
31
32#endif
diff --git a/drivers/gpu/nvgpu/common/posix/posix-comptags.c b/drivers/gpu/nvgpu/common/posix/posix-comptags.c
new file mode 100644
index 00000000..a00246dd
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/posix-comptags.c
@@ -0,0 +1,49 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bug.h>
24#include <nvgpu/comptags.h>
25
26#include <nvgpu/posix/vm.h>
27
28void gk20a_get_comptags(struct nvgpu_os_buffer *buf,
29 struct gk20a_comptags *comptags)
30{
31}
32
33int gk20a_alloc_or_get_comptags(struct gk20a *g,
34 struct nvgpu_os_buffer *buf,
35 struct gk20a_comptag_allocator *allocator,
36 struct gk20a_comptags *comptags)
37{
38 return -ENODEV;
39}
40
41bool gk20a_comptags_start_clear(struct nvgpu_os_buffer *buf)
42{
43 return false;
44}
45
46void gk20a_comptags_finish_clear(struct nvgpu_os_buffer *buf,
47 bool clear_successful)
48{
49}
diff --git a/drivers/gpu/nvgpu/common/posix/posix-nvgpu_mem.c b/drivers/gpu/nvgpu/common/posix/posix-nvgpu_mem.c
new file mode 100644
index 00000000..f8feb6a2
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/posix-nvgpu_mem.c
@@ -0,0 +1,209 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bug.h>
24#include <nvgpu/dma.h>
25#include <nvgpu/gmmu.h>
26#include <nvgpu/kmem.h>
27#include <nvgpu/nvgpu_mem.h>
28
29/*
30 * DMA memory buffers - obviously we don't really have DMA in userspace but we
31 * can emulate a lot of the DMA mem functionality for unit testing purposes.
32 */
33
34int nvgpu_mem_begin(struct gk20a *g, struct nvgpu_mem *mem)
35{
36 return 0;
37}
38
39void nvgpu_mem_end(struct gk20a *g, struct nvgpu_mem *mem)
40{
41 return;
42}
43
44u32 nvgpu_mem_rd32(struct gk20a *g, struct nvgpu_mem *mem, u32 w)
45{
46 u32 *mem_ptr = (u32 *)mem->cpu_va;
47
48 return mem_ptr[w];
49}
50
51u32 nvgpu_mem_rd(struct gk20a *g, struct nvgpu_mem *mem, u32 offset)
52{
53 if (offset & 0x3)
54 BUG();
55
56 return nvgpu_mem_rd32(g, mem, offset >> 2);
57}
58
59void nvgpu_mem_rd_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
60 void *dest, u32 size)
61{
62 if (offset & 0x3 || size & 0x3)
63 BUG();
64
65 memcpy(dest, ((char *)mem->cpu_va) + offset, size);
66}
67
68void nvgpu_mem_wr32(struct gk20a *g, struct nvgpu_mem *mem, u32 w, u32 data)
69{
70 u32 *mem_ptr = (u32 *)mem->cpu_va;
71
72 mem_ptr[w] = data;
73}
74
75void nvgpu_mem_wr(struct gk20a *g, struct nvgpu_mem *mem, u32 offset, u32 data)
76{
77 if (offset & 0x3)
78 BUG();
79
80 nvgpu_mem_wr32(g, mem, offset >> 2, data);
81}
82
83void nvgpu_mem_wr_n(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
84 void *src, u32 size)
85{
86 if (offset & 0x3 || size & 0x3)
87 BUG();
88
89 memcpy(((char *)mem->cpu_va) + offset, src, size);
90}
91
92void nvgpu_memset(struct gk20a *g, struct nvgpu_mem *mem, u32 offset,
93 u32 c, u32 size)
94{
95 memset(((char *)mem->cpu_va) + offset, c, size);
96}
97
98/*
99 * These functions are somewhat meaningless.
100 */
101u64 nvgpu_mem_get_addr(struct gk20a *g, struct nvgpu_mem *mem)
102{
103 return (u64)(uintptr_t)mem->cpu_va;
104}
105
106u64 nvgpu_mem_get_phys_addr(struct gk20a *g, struct nvgpu_mem *mem)
107{
108 return (u64)(uintptr_t)mem->cpu_va;
109}
110
111static struct nvgpu_sgl *nvgpu_mem_sgl_next(struct nvgpu_sgl *sgl)
112{
113 return NULL;
114}
115
116static u64 nvgpu_mem_sgl_phys(struct gk20a *g, struct nvgpu_sgl *sgl)
117{
118 struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
119
120 return (u64)(uintptr_t)mem->cpu_va;
121}
122
123static u64 nvgpu_mem_sgl_dma(struct nvgpu_sgl *sgl)
124{
125 struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
126
127 return (u64)(uintptr_t)mem->cpu_va;
128}
129
130static u64 nvgpu_mem_sgl_length(struct nvgpu_sgl *sgl)
131{
132 struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
133
134 return (u64)mem->aligned_size;
135}
136
137static u64 nvgpu_mem_sgl_gpu_addr(struct gk20a *g, struct nvgpu_sgl *sgl,
138 struct nvgpu_gmmu_attrs *attrs)
139{
140 struct nvgpu_mem *mem = (struct nvgpu_mem *)sgl;
141
142 return mem->gpu_va;
143}
144
145static bool nvgpu_mem_sgt_iommuable(struct gk20a *g, struct nvgpu_sgt *sgt)
146{
147 return nvgpu_iommuable(g);
148}
149
150static void nvgpu_mem_sgt_free(struct gk20a *g, struct nvgpu_sgt *sgt)
151{
152 nvgpu_kfree(g, sgt);
153}
154
155static struct nvgpu_sgt_ops nvgpu_sgt_posix_ops = {
156 .sgl_next = nvgpu_mem_sgl_next,
157 .sgl_phys = nvgpu_mem_sgl_phys,
158 .sgl_dma = nvgpu_mem_sgl_dma,
159 .sgl_length = nvgpu_mem_sgl_length,
160 .sgl_gpu_addr = nvgpu_mem_sgl_gpu_addr,
161 .sgt_iommuable = nvgpu_mem_sgt_iommuable,
162 .sgt_free = nvgpu_mem_sgt_free,
163};
164
165struct nvgpu_sgt *nvgpu_sgt_create_from_mem(struct gk20a *g,
166 struct nvgpu_mem *mem)
167{
168 struct nvgpu_sgt *sgt = nvgpu_kzalloc(g, sizeof(*sgt));
169
170 if (sgt == NULL)
171 return NULL;
172
173 /*
174 * The userspace implementation is simple: a single 'entry' (which we
175 * only need the mem struct to describe). Maybe this could be expanded
176 * to be more interesting some day.
177 */
178 sgt->sgl = (struct nvgpu_sgl *)mem;
179 sgt->ops = &nvgpu_sgt_posix_ops;
180
181 return sgt;
182}
183
184int nvgpu_mem_create_from_mem(struct gk20a *g,
185 struct nvgpu_mem *dest, struct nvgpu_mem *src,
186 int start_page, int nr_pages)
187{
188 u64 start = start_page * PAGE_SIZE;
189 u64 size = nr_pages * PAGE_SIZE;
190
191 if (src->aperture != APERTURE_SYSMEM)
192 return -EINVAL;
193
194 /* Some silly things a caller might do... */
195 if (size > src->size)
196 return -EINVAL;
197 if ((start + size) > src->size)
198 return -EINVAL;
199
200 memset(dest, 0, sizeof(*dest));
201
202 dest->cpu_va = ((char *)src->cpu_va) + start;
203 dest->mem_flags = src->mem_flags | NVGPU_MEM_FLAG_SHADOW_COPY;
204 dest->aperture = src->aperture;
205 dest->skip_wmb = src->skip_wmb;
206 dest->size = size;
207
208 return 0;
209}
diff --git a/drivers/gpu/nvgpu/common/posix/posix-vm.c b/drivers/gpu/nvgpu/common/posix/posix-vm.c
new file mode 100644
index 00000000..588b956d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/posix-vm.c
@@ -0,0 +1,52 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <stdlib.h>
24
25#include <nvgpu/vm.h>
26#include <nvgpu/bug.h>
27
28#include <nvgpu/posix/vm.h>
29
30u64 nvgpu_os_buf_get_size(struct nvgpu_os_buffer *os_buf)
31{
32 return os_buf->size;
33}
34
35struct nvgpu_mapped_buf *nvgpu_vm_find_mapping(struct vm_gk20a *vm,
36 struct nvgpu_os_buffer *os_buf,
37 u64 map_addr,
38 u32 flags,
39 int kind)
40{
41 BUG();
42
43 /*
44 * No map caching for now.
45 */
46 return NULL;
47}
48
49void nvgpu_vm_unmap_system(struct nvgpu_mapped_buf *mapped_buffer)
50{
51 free(mapped_buffer->os_priv.buf);
52}
diff --git a/drivers/gpu/nvgpu/common/posix/rwsem.c b/drivers/gpu/nvgpu/common/posix/rwsem.c
new file mode 100644
index 00000000..7a696b75
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/rwsem.c
@@ -0,0 +1,117 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bug.h>
24#include <nvgpu/rwsem.h>
25#include <nvgpu/timers.h>
26
27#include <nvgpu/posix/rwsem.h>
28
29void nvgpu_rwsem_init(struct nvgpu_rwsem *rwsem)
30{
31 memset(rwsem, 0, sizeof(*rwsem));
32
33 nvgpu_spinlock_init(&rwsem->lock);
34}
35
36/*
37 * Acquire.
38 */
39void nvgpu_rwsem_down_read(struct nvgpu_rwsem *rwsem)
40{
41 while (true) {
42 nvgpu_spinlock_acquire(&rwsem->lock);
43
44 /*
45 * If there's a writer try again.
46 */
47 if (rwsem->writers < 0) {
48 nvgpu_spinlock_release(&rwsem->lock);
49 nvgpu_msleep(10);
50 continue;
51 }
52
53 /*
54 * Otherwise decrement the read counter and return.
55 */
56 rwsem->readers -= 1;
57 nvgpu_spinlock_release(&rwsem->lock);
58 return;
59 }
60}
61
62/*
63 * Release.
64 */
65void nvgpu_rwsem_up_read(struct nvgpu_rwsem *rwsem)
66{
67 nvgpu_spinlock_acquire(&rwsem->lock);
68 rwsem->readers += 1;
69
70 /*
71 * Can't be any writers if there was a reader. Also can't be
72 * a positive number of readers. The increments are always
73 * downward so if we have a positive number then there is a
74 * balancing bug.
75 */
76 BUG_ON(rwsem->writers < 0);
77 BUG_ON(rwsem->readers > 0);
78
79 nvgpu_spinlock_release(&rwsem->lock);
80}
81
82void nvgpu_rwsem_down_write(struct nvgpu_rwsem *rwsem)
83{
84 while (true) {
85 nvgpu_spinlock_acquire(&rwsem->lock);
86
87 /*
88 * If there's a reader or a writer try again. Note: in this very
89 * simple implementation it's possible for readers to
90 * indefinitely starve writers.
91 */
92 if (rwsem->writers < 0 || rwsem->readers < 0) {
93 nvgpu_spinlock_release(&rwsem->lock);
94 nvgpu_msleep(10);
95 continue;
96 }
97
98 rwsem->writers -= 1;
99 nvgpu_spinlock_release(&rwsem->lock);
100 return;
101 }
102}
103
104void nvgpu_rwsem_up_write(struct nvgpu_rwsem *rwsem)
105{
106 nvgpu_spinlock_acquire(&rwsem->lock);
107 rwsem->writers += 1;
108
109 /*
110 * Writers can't be positive: that would be an unbalanced free. Readers
111 * must be zero - otherwise this writer should never have had access!
112 */
113 BUG_ON(rwsem->writers > 0);
114 BUG_ON(rwsem->readers != 0);
115
116 nvgpu_spinlock_release(&rwsem->lock);
117}
diff --git a/drivers/gpu/nvgpu/common/posix/soc.c b/drivers/gpu/nvgpu/common/posix/soc.c
new file mode 100644
index 00000000..0e5c7141
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/soc.c
@@ -0,0 +1,48 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/soc.h>
24
25bool nvgpu_platform_is_silicon(struct gk20a *g)
26{
27 return false;
28}
29
30bool nvgpu_platform_is_simulation(struct gk20a *g)
31{
32 return false;
33}
34
35bool nvgpu_platform_is_fpga(struct gk20a *g)
36{
37 return false;
38}
39
40bool nvgpu_is_hypervisor_mode(struct gk20a *g)
41{
42 return false;
43}
44
45bool nvgpu_is_bpmp_running(struct gk20a *g)
46{
47 return false;
48}
diff --git a/drivers/gpu/nvgpu/common/posix/stubs.c b/drivers/gpu/nvgpu/common/posix/stubs.c
new file mode 100644
index 00000000..d6270692
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/stubs.c
@@ -0,0 +1,32 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23/**
24 * Here lie OS stubs that do not have an implementation yet nor has any plans
25 * for an implementation.
26 */
27
28#include "gk20a/dbg_gpu_gk20a.h"
29
30void nvgpu_dbg_session_post_event(struct dbg_session_gk20a *dbg_s)
31{
32}
diff --git a/drivers/gpu/nvgpu/common/posix/thread.c b/drivers/gpu/nvgpu/common/posix/thread.c
new file mode 100644
index 00000000..d9476523
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/thread.c
@@ -0,0 +1,96 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <nvgpu/bug.h>
24#include <nvgpu/thread.h>
25
26#include <nvgpu/posix/thread.h>
27
28/**
29 * Use pthreads to mostly emulate the Linux kernel APIs. There are some things
30 * that are quite different - especially the stop/should_stop notions. In user
31 * space threads can send signals to one another but of course within the kernel
32 * that is not as simple.
33 *
34 * This could use some nice debugging some day as well.
35 */
36
37/*
38 * nvgpu thread functions return int. POSIX threads return void *. This little
39 * wrapper takes the int returning nvgpu thread and instead passes that int back
40 * through the void * pointer.
41 */
42static void *__nvgpu_posix_thread_wrapper(void *data)
43{
44 struct nvgpu_posix_thread_data *nvgpu = data;
45
46 return ERR_PTR(nvgpu->fn(nvgpu->data));
47}
48
49int nvgpu_thread_create(struct nvgpu_thread *thread,
50 void *data,
51 int (*threadfn)(void *data), const char *name)
52{
53 int ret;
54
55 BUG_ON(thread->running);
56
57 memset(thread, 0, sizeof(*thread));
58
59 /*
60 * By subtracting 1 the above memset ensures that we have a zero
61 * terminated string.
62 */
63 strncpy(thread->tname, name, NVGPU_THREAD_POSIX_MAX_NAMELEN - 1);
64
65 thread->nvgpu.data = data;
66 thread->nvgpu.fn = threadfn;
67
68 ret = pthread_create(&thread->thread, NULL,
69 __nvgpu_posix_thread_wrapper,
70 &thread->nvgpu);
71 if (ret != 0)
72 return ret;
73
74#ifdef _GNU_SOURCE
75 pthread_setname_np(thread->thread, thread->tname);
76#endif
77
78 thread->running = true;
79
80 return 0;
81}
82
83void nvgpu_thread_stop(struct nvgpu_thread *thread)
84{
85 thread->should_stop = true;
86}
87
88bool nvgpu_thread_should_stop(struct nvgpu_thread *thread)
89{
90 return thread->should_stop;
91}
92
93bool nvgpu_thread_is_running(struct nvgpu_thread *thread)
94{
95 return thread->running;
96}
diff --git a/drivers/gpu/nvgpu/common/posix/timers.c b/drivers/gpu/nvgpu/common/posix/timers.c
new file mode 100644
index 00000000..c84b0de5
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/timers.c
@@ -0,0 +1,169 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include <sys/time.h>
24
25#include <nvgpu/bug.h>
26#include <nvgpu/log.h>
27#include <nvgpu/timers.h>
28
29static s64 now(void)
30{
31 return nvgpu_current_time_ms();
32}
33
34/*
35 * Returns true if a > b;
36 */
37static bool time_after(s64 a, s64 b)
38{
39 return a - b > 0;
40}
41
42int nvgpu_timeout_init(struct gk20a *g, struct nvgpu_timeout *timeout,
43 u32 duration, unsigned long flags)
44{
45 if (flags & ~NVGPU_TIMER_FLAG_MASK)
46 return -EINVAL;
47
48 memset(timeout, 0, sizeof(*timeout));
49
50 timeout->g = g;
51 timeout->flags = flags;
52
53 if (flags & NVGPU_TIMER_RETRY_TIMER)
54 timeout->retries.max = duration;
55 else
56 timeout->time = nvgpu_current_time_ms() + (s64)duration;
57
58 return 0;
59}
60
61static int __nvgpu_timeout_expired_msg_cpu(struct nvgpu_timeout *timeout,
62 void *caller,
63 const char *fmt, va_list args)
64{
65 struct gk20a *g = timeout->g;
66
67 if (time_after(now(), timeout->time)) {
68 if (!(timeout->flags & NVGPU_TIMER_SILENT_TIMEOUT)) {
69 char buf[128];
70
71 vsnprintf(buf, sizeof(buf), fmt, args);
72
73 nvgpu_err(g, "Timeout detected @ %p %s", caller, buf);
74 }
75
76 return -ETIMEDOUT;
77 }
78
79 return 0;
80}
81
82static int __nvgpu_timeout_expired_msg_retry(struct nvgpu_timeout *timeout,
83 void *caller,
84 const char *fmt, va_list args)
85{
86 struct gk20a *g = timeout->g;
87
88 if (timeout->retries.attempted >= timeout->retries.max) {
89 if (!(timeout->flags & NVGPU_TIMER_SILENT_TIMEOUT)) {
90 char buf[128];
91
92 vsnprintf(buf, sizeof(buf), fmt, args);
93
94 nvgpu_err(g, "No more retries @ %p %s", caller, buf);
95 }
96
97 return -ETIMEDOUT;
98 }
99
100 timeout->retries.attempted++;
101
102 return 0;
103}
104
105int __nvgpu_timeout_expired_msg(struct nvgpu_timeout *timeout,
106 void *caller, const char *fmt, ...)
107{
108 int ret;
109 va_list args;
110
111 va_start(args, fmt);
112 if (timeout->flags & NVGPU_TIMER_RETRY_TIMER)
113 ret = __nvgpu_timeout_expired_msg_retry(timeout, caller, fmt,
114 args);
115 else
116 ret = __nvgpu_timeout_expired_msg_cpu(timeout, caller, fmt,
117 args);
118 va_end(args);
119
120 return ret;
121}
122
123int nvgpu_timeout_peek_expired(struct nvgpu_timeout *timeout)
124{
125 if (timeout->flags & NVGPU_TIMER_RETRY_TIMER)
126 return timeout->retries.attempted >= timeout->retries.max;
127 else
128 return time_after(now(), timeout->time);
129}
130
131void nvgpu_udelay(unsigned int usecs)
132{
133 BUG();
134}
135
136void nvgpu_usleep_range(unsigned int min_us, unsigned int max_us)
137{
138 BUG();
139}
140
141void nvgpu_msleep(unsigned int msecs)
142{
143 BUG();
144}
145
146static inline s64 __nvgpu_current_time_us(void)
147{
148 struct timeval now;
149 s64 time_now;
150 int ret;
151
152 ret = gettimeofday(&now, NULL);
153 if (ret != 0)
154 BUG();
155
156 time_now = ((s64)now.tv_sec * (s64)1000000) + (s64)now.tv_usec;
157
158 return time_now;
159}
160
161s64 nvgpu_current_time_ms(void)
162{
163 return __nvgpu_current_time_us() / (s64)1000;
164}
165
166u64 nvgpu_hr_timestamp(void)
167{
168 return __nvgpu_current_time_us();
169}
diff --git a/drivers/gpu/nvgpu/common/posix/tsg.c b/drivers/gpu/nvgpu/common/posix/tsg.c
new file mode 100644
index 00000000..8736123d
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/posix/tsg.c
@@ -0,0 +1,28 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#include "gk20a/tsg_gk20a.h"
24
25void gk20a_tsg_event_id_post_event(struct tsg_gk20a *tsg,
26 int __event_id)
27{
28}
diff --git a/drivers/gpu/nvgpu/include/nvgpu/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/atomic.h
index 0f319f71..12d1c86e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/atomic.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/atomic.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <nvgpu/linux/atomic.h> 26#include <nvgpu/linux/atomic.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/atomic.h>
27#else 29#else
28#include <nvgpu_rmos/include/atomic.h> 30#include <nvgpu_rmos/include/atomic.h>
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/barrier.h b/drivers/gpu/nvgpu/include/nvgpu/barrier.h
index 03a14a99..49b10b86 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/barrier.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/barrier.h
@@ -30,6 +30,8 @@
30 30
31#ifdef __KERNEL__ 31#ifdef __KERNEL__
32#include <nvgpu/linux/barrier.h> 32#include <nvgpu/linux/barrier.h>
33#elif defined(__NVGPU_POSIX__)
34#include <nvgpu/posix/barrier.h>
33#else 35#else
34#include <nvgpu_rmos/include/barrier.h> 36#include <nvgpu_rmos/include/barrier.h>
35#endif 37#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
index d3bac60e..26b6e19d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bitops.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bitops.h
@@ -25,6 +25,8 @@
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/bitops.h> 26#include <linux/bitops.h>
27#include <linux/bitmap.h> 27#include <linux/bitmap.h>
28#elif defined(__NVGPU_POSIX__)
29#include <nvgpu/posix/bitops.h>
28#else 30#else
29#include <nvgpu_rmos/include/bitops.h> 31#include <nvgpu_rmos/include/bitops.h>
30#endif 32#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bsearch.h b/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
index b02cc85c..872701e6 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bsearch.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/bsearch.h> 26#include <linux/bsearch.h>
27#elif defined(__NVGPU_POSIX__)
28#include <stdlib.h>
27#endif 29#endif
28 30
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/bug.h b/drivers/gpu/nvgpu/include/nvgpu/bug.h
index ea62c6d8..671439a1 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/bug.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bug.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/bug.h> 26#include <linux/bug.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/bug.h>
27#else 29#else
28#include <nvgpu_rmos/include/bug.h> 30#include <nvgpu_rmos/include/bug.h>
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h b/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
index c6620663..4dd9e0d8 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/circ_buf.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/circ_buf.h> 26#include <linux/circ_buf.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/circ_buf.h>
27#endif 29#endif
28 30
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/cond.h b/drivers/gpu/nvgpu/include/nvgpu/cond.h
index b6f2598e..340fb460 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/cond.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/cond.h
@@ -25,6 +25,8 @@
25 25
26#ifdef __KERNEL__ 26#ifdef __KERNEL__
27#include <nvgpu/linux/cond.h> 27#include <nvgpu/linux/cond.h>
28#elif defined(__NVGPU_POSIX__)
29#include <nvgpu/posix/cond.h>
28#else 30#else
29#include <nvgpu_rmos/include/cond.h> 31#include <nvgpu_rmos/include/cond.h>
30#endif 32#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/kmem.h b/drivers/gpu/nvgpu/include/nvgpu/kmem.h
index fef837cf..91574ce0 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/kmem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/kmem.h
@@ -40,6 +40,8 @@ struct gk20a;
40 */ 40 */
41#ifdef __KERNEL__ 41#ifdef __KERNEL__
42#include <nvgpu/linux/kmem.h> 42#include <nvgpu/linux/kmem.h>
43#elif defined(__NVGPU_POSIX__)
44#include <nvgpu/posix/kmem.h>
43#else 45#else
44#include <nvgpu_rmos/include/kmem.h> 46#include <nvgpu_rmos/include/kmem.h>
45#endif 47#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/lock.h b/drivers/gpu/nvgpu/include/nvgpu/lock.h
index bccded57..7e4b2ac3 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/lock.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/lock.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a 4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"), 5 * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,8 @@
25 25
26#ifdef __KERNEL__ 26#ifdef __KERNEL__
27#include <nvgpu/linux/lock.h> 27#include <nvgpu/linux/lock.h>
28#elif defined(__NVGPU_POSIX__)
29#include <nvgpu/posix/lock.h>
28#else 30#else
29#include <nvgpu_rmos/include/lock.h> 31#include <nvgpu_rmos/include/lock.h>
30#endif 32#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log.h b/drivers/gpu/nvgpu/include/nvgpu/log.h
index 897dcfc6..87ab17ee 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/log.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/log.h
@@ -106,7 +106,7 @@ int nvgpu_log_mask_enabled(struct gk20a *g, u64 log_mask);
106 * Print a message if the log_mask matches the enabled debugging. 106 * Print a message if the log_mask matches the enabled debugging.
107 */ 107 */
108#define nvgpu_log(g, log_mask, fmt, arg...) \ 108#define nvgpu_log(g, log_mask, fmt, arg...) \
109 __nvgpu_log_dbg(g, log_mask, __func__, __LINE__, fmt, ##arg) 109 __nvgpu_log_dbg(g, (u32)log_mask, __func__, __LINE__, fmt, ##arg)
110 110
111/** 111/**
112 * nvgpu_err - Print an error 112 * nvgpu_err - Print an error
diff --git a/drivers/gpu/nvgpu/include/nvgpu/log2.h b/drivers/gpu/nvgpu/include/nvgpu/log2.h
index 827162f8..57b77217 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/log2.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/log2.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/log2.h> 26#include <linux/log2.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/log2.h>
27#endif 29#endif
28 30
29#endif /* __NVGPU_LOG2_H__ */ 31#endif /* __NVGPU_LOG2_H__ */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
index c5e3e752..93fce81e 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/nvgpu_mem.h
@@ -29,6 +29,8 @@
29 29
30#ifdef __KERNEL__ 30#ifdef __KERNEL__
31#include <nvgpu/linux/nvgpu_mem.h> 31#include <nvgpu/linux/nvgpu_mem.h>
32#elif defined(__NVGPU_POSIX__)
33#include <nvgpu/posix/nvgpu_mem.h>
32#else 34#else
33#include <nvgpu_rmos/include/nvgpu_mem.h> 35#include <nvgpu_rmos/include/nvgpu_mem.h>
34#endif 36#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h b/drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h
new file mode 100644
index 00000000..c9d92128
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/atomic.h
@@ -0,0 +1,191 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_ATOMIC_H__
24#define __NVGPU_POSIX_ATOMIC_H__
25
26#include <nvgpu/types.h>
27
28/*
29 * Note: this code uses the GCC builtins to implement atomics.
30 */
31
32#define __atomic_cmpxchg(p, v, c) __sync_val_compare_and_swap(p, v, c)
33#define __atomic_and(p, v) __sync_fetch_and_and(p, v)
34#define __atomic_or(p, v) __sync_fetch_and_or(p, v)
35
36#define cmpxchg __atomic_cmpxchg
37
38/*
39 * Place holders until real atomics can be implemented... Yay for GCC builtins!
40 * We can use those eventually to define all the Linux atomic ops.
41 *
42 * TODO: make these _actually_ atomic!
43 */
44typedef struct __nvgpu_posix_atomic {
45 int v;
46} nvgpu_atomic_t;
47
48typedef struct __nvgpu_posix_atomic64 {
49 long v;
50} nvgpu_atomic64_t;
51
52#define __nvgpu_atomic_init(i) { i }
53#define __nvgpu_atomic64_init(i) { i }
54
55static inline void __nvgpu_atomic_set(nvgpu_atomic_t *v, int i)
56{
57 v->v = i;
58}
59
60static inline int __nvgpu_atomic_read(nvgpu_atomic_t *v)
61{
62 return v->v;
63}
64
65static inline void __nvgpu_atomic_inc(nvgpu_atomic_t *v)
66{
67 v->v++;
68}
69
70static inline int __nvgpu_atomic_inc_return(nvgpu_atomic_t *v)
71{
72 v->v++;
73 return v->v;
74}
75
76static inline void __nvgpu_atomic_dec(nvgpu_atomic_t *v)
77{
78 v->v--;
79}
80
81static inline int __nvgpu_atomic_dec_return(nvgpu_atomic_t *v)
82{
83 v->v--;
84 return v->v;
85}
86
87static inline int __nvgpu_atomic_cmpxchg(nvgpu_atomic_t *v, int old, int new)
88{
89 if (v->v == old)
90 v->v = new;
91
92 return v->v;
93}
94
95static inline int __nvgpu_atomic_xchg(nvgpu_atomic_t *v, int new)
96{
97 v->v = new;
98 return new;
99}
100
101static inline bool __nvgpu_atomic_inc_and_test(nvgpu_atomic_t *v)
102{
103 v->v++;
104 return v->v ? true : false;
105}
106
107static inline bool __nvgpu_atomic_dec_and_test(nvgpu_atomic_t *v)
108{
109 v->v--;
110 return v->v ? true : false;
111}
112
113static inline bool __nvgpu_atomic_sub_and_test(int i, nvgpu_atomic_t *v)
114{
115 v->v -= i;
116 return v->v ? true : false;
117}
118
119static inline int __nvgpu_atomic_add_return(int i, nvgpu_atomic_t *v)
120{
121 v->v += i;
122 return v->v;
123}
124
125static inline int __nvgpu_atomic_add_unless(nvgpu_atomic_t *v, int a, int u)
126{
127 if (v->v != u)
128 v->v += a;
129
130 return v->v;
131}
132
133static inline void __nvgpu_atomic64_set(nvgpu_atomic64_t *v, long i)
134{
135 v->v = i;
136}
137
138static inline long __nvgpu_atomic64_read(nvgpu_atomic64_t *v)
139{
140 return v->v;
141}
142
143static inline void __nvgpu_atomic64_add(long x, nvgpu_atomic64_t *v)
144{
145 v->v += x;
146}
147
148static inline void __nvgpu_atomic64_inc(nvgpu_atomic64_t *v)
149{
150 v->v++;
151}
152
153static inline long __nvgpu_atomic64_inc_return(nvgpu_atomic64_t *v)
154{
155 v->v++;
156 return v->v;
157}
158
159static inline void __nvgpu_atomic64_dec(nvgpu_atomic64_t *v)
160{
161 v->v--;
162}
163
164static inline long __nvgpu_atomic64_dec_return(nvgpu_atomic64_t *v)
165{
166 v->v--;
167 return v->v;
168}
169
170static inline long __nvgpu_atomic64_cmpxchg(nvgpu_atomic64_t *v,
171 long old, long new)
172{
173
174 if (v->v == old)
175 v->v = new;
176
177 return v->v;
178}
179
180static inline void __nvgpu_atomic64_sub(long x, nvgpu_atomic64_t *v)
181{
182 v->v -= x;
183}
184
185static inline long __nvgpu_atomic64_sub_return(long x, nvgpu_atomic64_t *v)
186{
187 v->v -= x;
188 return v->v;
189}
190
191#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/barrier.h b/drivers/gpu/nvgpu/include/nvgpu/posix/barrier.h
new file mode 100644
index 00000000..edc7b129
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/barrier.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_BARRIER_H__
24#define __NVGPU_POSIX_BARRIER_H__
25
26#define ACCESS_ONCE(x) (*(volatile __typeof__(x) *)&x)
27
28/*
29 * TODO: implement all these!
30 */
31#define __nvgpu_mb()
32#define __nvgpu_rmb()
33#define __nvgpu_wmb()
34
35#define __nvgpu_smp_mb()
36#define __nvgpu_smp_rmb()
37#define __nvgpu_smp_wmb()
38
39#define __nvgpu_read_barrier_depends()
40#define __nvgpu_smp_read_barrier_depends()
41
42#define __NV_ACCESS_ONCE(x) ACCESS_ONCE(x)
43
44#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
new file mode 100644
index 00000000..bfc6fef1
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/bitops.h
@@ -0,0 +1,92 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_BITOPS_H__
24#define __NVGPU_POSIX_BITOPS_H__
25
26#include <nvgpu/types.h>
27
28/*
29 * Assume an 8 bit byte, of course.
30 */
31#define BITS_PER_BYTE 8UL
32#define BITS_PER_LONG (__SIZEOF_LONG__ * BITS_PER_BYTE)
33#define BITS_TO_LONGS(bits) \
34 (bits + (BITS_PER_LONG - 1) / BITS_PER_LONG)
35
36#define BIT(i) (1UL << (i))
37
38#define GENMASK(h, l) \
39 (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h))))
40
41#define DECLARE_BITMAP(bmap, bits) \
42 unsigned long bmap[BITS_TO_LONGS(bits)]
43
44#define for_each_set_bit(bit, addr, size) \
45 for ((bit) = find_first_bit((addr), (size)); \
46 (bit) < (size); \
47 (bit) = find_next_bit((addr), (size), (bit) + 1))
48
49#define ffs(word) __ffs(word)
50#define ffz(word) __ffs(~(word))
51#define fls(word) __fls(word)
52
53/*
54 * Clashes with symbols in libc it seems.
55 */
56#define __ffs(word) __nvgpu_posix_ffs(word)
57#define __fls(word) __nvgpu_posix_fls(word)
58
59unsigned long __nvgpu_posix_ffs(unsigned long word);
60unsigned long __nvgpu_posix_fls(unsigned long word);
61
62unsigned long find_first_bit(const unsigned long *addr, unsigned long size);
63unsigned long find_next_bit(const unsigned long *addr, unsigned long size,
64 unsigned long offset);
65unsigned long find_first_zero_bit(const unsigned long *addr,
66 unsigned long size);
67
68bool test_bit(int nr, const volatile unsigned long *addr);
69bool test_and_set_bit(int nr, volatile unsigned long *addr);
70bool test_and_clear_bit(int nr, volatile unsigned long *addr);
71
72/*
73 * These two are atomic.
74 */
75void set_bit(int nr, volatile unsigned long *addr);
76void clear_bit(int nr, volatile unsigned long *addr);
77
78void bitmap_set(unsigned long *map, unsigned int start, int len);
79void bitmap_clear(unsigned long *map, unsigned int start, int len);
80unsigned long bitmap_find_next_zero_area_off(unsigned long *map,
81 unsigned long size,
82 unsigned long start,
83 unsigned int nr,
84 unsigned long align_mask,
85 unsigned long align_offset);
86unsigned long bitmap_find_next_zero_area(unsigned long *map,
87 unsigned long size,
88 unsigned long start,
89 unsigned int nr,
90 unsigned long align_mask);
91
92#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/bug.h b/drivers/gpu/nvgpu/include/nvgpu/posix/bug.h
new file mode 100644
index 00000000..04389a90
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/bug.h
@@ -0,0 +1,56 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_BUG_H__
24#define __NVGPU_POSIX_BUG_H__
25
26#include <nvgpu/types.h>
27
28/*
29 * TODO: make these actually useful!
30 */
31
32#define BUG() __bug("")
33#define BUG_ON(cond) \
34 do { \
35 if (cond) \
36 BUG(); \
37 } while (0)
38
39#define WARN(cond, msg, arg...) __warn(cond, msg, ##arg)
40#define WARN_ON(cond) __warn(cond, "")
41
42#define WARN_ONCE(cond, msg, arg...) \
43 ({static int __warned__ = 0; \
44 if (!__warned__) { \
45 WARN(cond, msg, ##arg); \
46 __warned__ = 1; \
47 } \
48 cond; })
49
50
51void dump_stack(void);
52
53void __bug(const char *fmt, ...) __attribute__ ((noreturn));
54bool __warn(bool cond, const char *fmt, ...);
55
56#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/circ_buf.h b/drivers/gpu/nvgpu/include/nvgpu/posix/circ_buf.h
new file mode 100644
index 00000000..8d9b5ea0
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/circ_buf.h
@@ -0,0 +1,44 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_CIRC_BUF_H__
24#define __NVGPU_POSIX_CIRC_BUF_H__
25
26#include <nvgpu/bug.h>
27
28/* TODO: implement. */
29
30#define CIRC_CNT(head, tail, size) \
31 ({(void)head; \
32 (void)tail; \
33 (void)size; \
34 BUG(); \
35 1; })
36
37#define CIRC_SPACE(head, tail, size) \
38 ({(void)head; \
39 (void)tail; \
40 (void)size; \
41 BUG(); \
42 1; })
43
44#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/cond.h b/drivers/gpu/nvgpu/include/nvgpu/posix/cond.h
new file mode 100644
index 00000000..3528388b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/cond.h
@@ -0,0 +1,59 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_COND_H__
24#define __NVGPU_POSIX_COND_H__
25
26#include <nvgpu/bug.h>
27
28struct nvgpu_cond {
29 /* Place holder until this can be properly implemented. */
30};
31
32/**
33 * NVGPU_COND_WAIT - Wait for a condition to be true
34 *
35 * @c - The condition variable to sleep on
36 * @condition - The condition that needs to be true
37 * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait
38 *
39 * Wait for a condition to become true. Returns -ETIMEOUT if
40 * the wait timed out with condition false.
41 */
42#define NVGPU_COND_WAIT(c, condition, timeout_ms) \
43 ({BUG(); 1; })
44
45/**
46 * NVGPU_COND_WAIT_INTERRUPTIBLE - Wait for a condition to be true
47 *
48 * @c - The condition variable to sleep on
49 * @condition - The condition that needs to be true
50 * @timeout_ms - Timeout in milliseconds, or 0 for infinite wait
51 *
52 * Wait for a condition to become true. Returns -ETIMEOUT if
53 * the wait timed out with condition false or -ERESTARTSYS on
54 * signal.
55 */
56#define NVGPU_COND_WAIT_INTERRUPTIBLE(c, condition, timeout_ms) \
57 ({BUG(); 1; })
58
59#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/kmem.h b/drivers/gpu/nvgpu/include/nvgpu/posix/kmem.h
new file mode 100644
index 00000000..483ac3b3
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/kmem.h
@@ -0,0 +1,36 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_KMEM_H__
24#define __NVGPU_POSIX_KMEM_H__
25
26#include <nvgpu/types.h>
27
28void *__nvgpu_kmalloc(struct gk20a *g, size_t size, unsigned long ip);
29void *__nvgpu_kzalloc(struct gk20a *g, size_t size, unsigned long ip);
30void *__nvgpu_kcalloc(struct gk20a *g, size_t n, size_t size, unsigned long ip);
31void *__nvgpu_vmalloc(struct gk20a *g, unsigned long size, unsigned long ip);
32void *__nvgpu_vzalloc(struct gk20a *g, unsigned long size, unsigned long ip);
33void __nvgpu_kfree(struct gk20a *g, void *addr);
34void __nvgpu_vfree(struct gk20a *g, void *addr);
35
36#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/lock.h b/drivers/gpu/nvgpu/include/nvgpu/posix/lock.h
new file mode 100644
index 00000000..82eddd02
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/lock.h
@@ -0,0 +1,69 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_LOCK_H__
24#define __NVGPU_POSIX_LOCK_H__
25
26#include <stdlib.h>
27
28#include <pthread.h>
29
30/*
31 * All locks for posix nvgpu are just pthread locks. There's not a lot of reason
32 * to have real spinlocks in userspace since we aren't using real HW or running
33 * perf critical code where a sleep could be devestating.
34 *
35 * This could be revisited later, though.
36 */
37struct __nvgpu_posix_lock {
38 pthread_mutex_t mutex;
39};
40
41static inline void __nvgpu_posix_lock_acquire(struct __nvgpu_posix_lock *lock)
42{
43 pthread_mutex_lock(&lock->mutex);
44}
45
46static inline int __nvgpu_posix_lock_try_acquire(
47 struct __nvgpu_posix_lock *lock)
48{
49 return pthread_mutex_trylock(&lock->mutex);
50}
51
52static inline void __nvgpu_posix_lock_release(struct __nvgpu_posix_lock *lock)
53{
54 pthread_mutex_unlock(&lock->mutex);
55}
56
57struct nvgpu_mutex {
58 struct __nvgpu_posix_lock lock;
59};
60
61struct nvgpu_spinlock {
62 struct __nvgpu_posix_lock lock;
63};
64
65struct nvgpu_raw_spinlock {
66 struct __nvgpu_posix_lock lock;
67};
68
69#endif /* NVGPU_LOCK_LINUX_H */
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/log2.h b/drivers/gpu/nvgpu/include/nvgpu/posix/log2.h
new file mode 100644
index 00000000..ca95c10a
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/log2.h
@@ -0,0 +1,37 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_LOG2_H__
24#define __NVGPU_POSIX_LOG2_H__
25
26#define ilog2(x) (fls(x) - 1)
27
28#define roundup_pow_of_two(x) (1UL << fls((x) - 1))
29#define rounddown_pow_of_two(x) (1UL << (fls(x) - 1))
30
31#define is_power_of_2(x) \
32 ({ \
33 typeof(x) __x__ = (x); \
34 (__x__ != 0 && ((__x__ & (__x__ - 1)) == 0)); \
35 })
36
37#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/nvgpu_mem.h b/drivers/gpu/nvgpu/include/nvgpu/posix/nvgpu_mem.h
new file mode 100644
index 00000000..30cdf60f
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/nvgpu_mem.h
@@ -0,0 +1,32 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_NVGPU_MEM_H__
24#define __NVGPU_POSIX_NVGPU_MEM_H__
25
26struct nvgpu_mem_priv {
27 /*
28 * Eventually this will require an implementation using nvmap.
29 */
30};
31
32#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h b/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
new file mode 100644
index 00000000..a9763aa9
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/probe.h
@@ -0,0 +1,31 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_PROBE_H__
24#define __NVGPU_POSIX_PROBE_H__
25
26struct gk20a;
27
28struct gk20a *nvgpu_posix_probe(void);
29void nvgpu_posix_cleanup(struct gk20a *g);
30
31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/rwsem.h b/drivers/gpu/nvgpu/include/nvgpu/posix/rwsem.h
new file mode 100644
index 00000000..65aa931b
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/rwsem.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_RWSEM_H__
24#define __NVGPU_POSIX_RWSEM_H__
25
26#include <nvgpu/lock.h>
27
28struct nvgpu_rwsem {
29 struct nvgpu_spinlock lock;
30
31 int readers;
32 int writers;
33};
34
35#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/sizes.h b/drivers/gpu/nvgpu/include/nvgpu/posix/sizes.h
new file mode 100644
index 00000000..3fda7574
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/sizes.h
@@ -0,0 +1,38 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_SIZES_H__
24#define __NVGPU_POSIX_SIZES_H__
25
26#define SZ_1K (1UL << 10)
27#define SZ_4K (SZ_1K << 2)
28#define SZ_64K (SZ_1K << 6)
29#define SZ_128K (SZ_1K << 7)
30
31#define SZ_1M (1UL << 20)
32#define SZ_16M (SZ_1M << 4)
33#define SZ_256M (SZ_1M << 8)
34
35#define SZ_1G (1UL << 30)
36#define SZ_4G (SZ_1G << 2)
37
38#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/sort.h b/drivers/gpu/nvgpu/include/nvgpu/posix/sort.h
new file mode 100644
index 00000000..6a6920eb
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/sort.h
@@ -0,0 +1,35 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_SORT_H__
24#define __NVGPU_POSIX_SORT_H__
25
26#include <nvgpu/bug.h>
27
28static void sort(void *base, size_t num, size_t size,
29 int (*cmp)(const void *, const void *),
30 void (*swap)(void *, void *, int))
31{
32 __bug("sort() not implemented yet!");
33}
34
35#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/thread.h b/drivers/gpu/nvgpu/include/nvgpu/posix/thread.h
new file mode 100644
index 00000000..a312cc13
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/thread.h
@@ -0,0 +1,51 @@
1/*
2 * Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_THREAD_H__
24#define __NVGPU_POSIX_THREAD_H__
25
26#include <pthread.h>
27
28#include <nvgpu/types.h>
29
30/*
31 * Handles passing an nvgpu thread function into a posix thread.
32 */
33struct nvgpu_posix_thread_data {
34 int (*fn)(void *data);
35 void *data;
36};
37
38/*
39 * For some reason POSIX only allows 16 bytes of name length.
40 */
41#define NVGPU_THREAD_POSIX_MAX_NAMELEN 16
42
43struct nvgpu_thread {
44 bool running;
45 bool should_stop;
46 pthread_t thread;
47 struct nvgpu_posix_thread_data nvgpu;
48 char tname[16];
49};
50
51#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/types.h b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
new file mode 100644
index 00000000..3dfcec6c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/types.h
@@ -0,0 +1,219 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_TYPES_H__
24#define __NVGPU_POSIX_TYPES_H__
25
26#include <stdbool.h>
27#include <stdint.h>
28#include <stddef.h>
29#include <errno.h>
30#include <limits.h>
31#include <string.h>
32#include <strings.h>
33#include <stdio.h>
34#include <stdarg.h>
35
36/*
37 * For endianness functions.
38 */
39#include <netinet/in.h>
40
41typedef unsigned char __u8;
42typedef unsigned short __u16;
43typedef unsigned int __u32;
44typedef unsigned long long __u64;
45
46typedef __u8 u8;
47typedef __u16 u16;
48typedef __u32 u32;
49typedef __u64 u64;
50
51typedef char s8;
52typedef short s16;
53typedef int s32;
54typedef long long s64;
55
56#define min_t(type, a, b) \
57 ({ \
58 type __a = (a); \
59 type __b = (b); \
60 __a < __b ? __a : __b; \
61 })
62
63#define min(a, b) \
64 ({ \
65 (a) < (b) ? a : b; \
66 })
67#define min3(a, b, c) min(min(a, b), c)
68
69#define max(a, b) \
70 ({ \
71 (a) > (b) ? a : b; \
72 })
73
74#define PAGE_SIZE 4096
75
76#define ARRAY_SIZE(array) \
77 (sizeof(array) / sizeof((array)[0]))
78
79#define MAX_SCHEDULE_TIMEOUT LONG_MAX
80
81#define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
82
83/*
84 * Only used in clk_gm20b.c which we will never unit test. Don't use!
85 */
86#define DIV_ROUND_CLOSEST(x, divisor) ({BUG(); 0; })
87
88/*
89 * Joys of userspace: usually division just works since the compiler can link
90 * against external division functions implicitly.
91 */
92#define do_div(a, b) ((a) /= (b))
93#define div64_u64(a, b) ((a) / (b))
94
95#define __round_mask(x, y) ((__typeof__(x))((y) - 1))
96#define round_up(x, y) ((((x) - 1) | __round_mask(x, y)) + 1)
97#define roundup(x, y) round_up(x, y)
98#define round_down(x, y) ((x) & ~__round_mask(x, y))
99
100#define ALIGN_MASK(x, mask) (((x) + (mask)) & ~(mask))
101#define ALIGN(x, a) ALIGN_MASK(x, (typeof(x))(a) - 1)
102#define PAGE_ALIGN(x) ALIGN(x, PAGE_SIZE)
103
104/*
105 * Caps return at the size of the buffer not what would have been written if buf
106 * were arbitrarily sized.
107 */
108static inline int scnprintf(char *buf, size_t size, const char *format, ...)
109{
110 size_t ret;
111 va_list args;
112
113 va_start(args, format);
114 ret = vsnprintf(buf, size, format, args);
115 va_end(args);
116
117 return ret <= size ? ret : size;
118}
119
120static inline u32 be32_to_cpu(u32 x)
121{
122 /*
123 * Conveniently big-endian happens to be network byte order as well so
124 * we can use ntohl() for this.
125 */
126 return ntohl(x);
127}
128
129/*
130 * Hamming weights.
131 */
132static inline unsigned long __hweight8(uint8_t x)
133{
134 return (unsigned long)(!!(x & (1 << 0)) +
135 !!(x & (1 << 1)) +
136 !!(x & (1 << 2)) +
137 !!(x & (1 << 3)) +
138 !!(x & (1 << 4)) +
139 !!(x & (1 << 5)) +
140 !!(x & (1 << 6)) +
141 !!(x & (1 << 7)));
142}
143
144static inline unsigned long __hweight16(uint16_t x)
145{
146 return __hweight8((uint8_t)x) +
147 __hweight8((uint8_t)((x & 0xff00) >> 8));
148}
149
150static inline unsigned long __hweight32(uint32_t x)
151{
152 return __hweight16((uint16_t)x) +
153 __hweight16((uint16_t)((x & 0xffff0000) >> 16));
154}
155
156static inline unsigned long __hweight64(uint64_t x)
157{
158 return __hweight32((uint32_t)x) +
159 __hweight32((uint32_t)((x & 0xffffffff00000000) >> 32));
160}
161
162#define hweight32 __hweight32
163#define hweight_long __hweight64
164
165/*
166 * Better suited under a compiler.h type header file, but for now these can live
167 * here.
168 */
169#define __must_check
170#define __maybe_unused __attribute__((unused))
171#define __iomem
172#define unlikely
173#define likely
174
175#define __stringify(x) #x
176
177/*
178 * Prevent compiler optimizations from mangling writes. But likely most uses of
179 * this in nvgpu are incorrect (i.e unnecessary).
180 */
181#define WRITE_ONCE(p, v) \
182 ({ \
183 volatile typeof(p) *__p__ = &(p); \
184 *__p__ = v; \
185 })
186
187#define container_of(ptr, type, member) ({ \
188 const typeof( ((type *)0)->member ) *__mptr = (ptr); \
189 (type *)( (char *)__mptr - offsetof(type,member) );})
190
191#define __packed __attribute__((packed))
192
193#define IS_ENABLED(config) 0
194
195#define MAX_ERRNO 4095
196
197#define IS_ERR_VALUE(x) ((x) >= (unsigned long)-MAX_ERRNO)
198
199static inline void *ERR_PTR(long error)
200{
201 return (void *) error;
202}
203
204static inline long PTR_ERR(void *error)
205{
206 return (long)(uintptr_t)error;
207}
208
209static inline bool IS_ERR(const void *ptr)
210{
211 return IS_ERR_VALUE((unsigned long)ptr);
212}
213
214static inline bool IS_ERR_OR_NULL(const void *ptr)
215{
216 return (ptr == NULL) || IS_ERR_VALUE((unsigned long)ptr);
217}
218
219#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/posix/vm.h b/drivers/gpu/nvgpu/include/nvgpu/posix/vm.h
new file mode 100644
index 00000000..ae997d3c
--- /dev/null
+++ b/drivers/gpu/nvgpu/include/nvgpu/posix/vm.h
@@ -0,0 +1,41 @@
1/*
2 * Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
19 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
20 * DEALINGS IN THE SOFTWARE.
21 */
22
23#ifndef __NVGPU_POSIX_VM_H__
24#define __NVGPU_POSIX_VM_H__
25
26#include <nvgpu/types.h>
27
28struct nvgpu_os_buffer {
29 /*
30 * We just use malloc() buffers in userspace.
31 */
32 void *buf;
33 size_t size;
34};
35
36struct nvgpu_mapped_buf_priv {
37 void *buf;
38 size_t size;
39};
40
41#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/rwsem.h b/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
index 0366ceff..4facf138 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/rwsem.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <nvgpu/linux/rwsem.h> 26#include <nvgpu/linux/rwsem.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/rwsem.h>
27#else 29#else
28#include <nvgpu_rmos/include/rwsem.h> 30#include <nvgpu_rmos/include/rwsem.h>
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/sizes.h b/drivers/gpu/nvgpu/include/nvgpu/sizes.h
index bb6f9c3d..588e772d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/sizes.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/sizes.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/sizes.h> 26#include <linux/sizes.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/sizes.h>
27#else 29#else
28#include <nvgpu_rmos/include/sizes.h> 30#include <nvgpu_rmos/include/sizes.h>
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/sort.h b/drivers/gpu/nvgpu/include/nvgpu/sort.h
index 0bef3593..20d86680 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/sort.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/sort.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/sort.h> 26#include <linux/sort.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/sort.h>
27#else 29#else
28#include <nvgpu_rmos/include/sort.h> 30#include <nvgpu_rmos/include/sort.h>
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/thread.h b/drivers/gpu/nvgpu/include/nvgpu/thread.h
index 79df9cda..316ca146 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/thread.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/thread.h
@@ -25,10 +25,14 @@
25 25
26#ifdef __KERNEL__ 26#ifdef __KERNEL__
27#include <nvgpu/linux/thread.h> 27#include <nvgpu/linux/thread.h>
28#elif defined(__NVGPU_POSIX__)
29#include <nvgpu/posix/thread.h>
28#else 30#else
29#include <nvgpu_rmos/include/thread.h> 31#include <nvgpu_rmos/include/thread.h>
30#endif 32#endif
31 33
34#include <nvgpu/types.h>
35
32/** 36/**
33 * nvgpu_thread_create - Create and run a new thread. 37 * nvgpu_thread_create - Create and run a new thread.
34 * 38 *
diff --git a/drivers/gpu/nvgpu/include/nvgpu/types.h b/drivers/gpu/nvgpu/include/nvgpu/types.h
index 8425c25d..1e243e53 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/types.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/types.h
@@ -24,6 +24,8 @@
24 24
25#ifdef __KERNEL__ 25#ifdef __KERNEL__
26#include <linux/types.h> 26#include <linux/types.h>
27#elif defined(__NVGPU_POSIX__)
28#include <nvgpu/posix/types.h>
27#else 29#else
28#include <nvgpu_rmos/include/types.h> 30#include <nvgpu_rmos/include/types.h>
29#endif 31#endif
diff --git a/drivers/gpu/nvgpu/include/nvgpu/vm.h b/drivers/gpu/nvgpu/include/nvgpu/vm.h
index a5a358ea..30a2d71d 100644
--- a/drivers/gpu/nvgpu/include/nvgpu/vm.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/vm.h
@@ -43,6 +43,8 @@ struct nvgpu_os_buffer;
43 43
44#ifdef __KERNEL__ 44#ifdef __KERNEL__
45#include <nvgpu/linux/vm.h> 45#include <nvgpu/linux/vm.h>
46#elif defined(__NVGPU_POSIX__)
47#include <nvgpu/posix/vm.h>
46#else 48#else
47/* QNX include goes here. */ 49/* QNX include goes here. */
48#include <nvgpu_rmos/include/vm.h> 50#include <nvgpu_rmos/include/vm.h>
diff --git a/drivers/gpu/nvgpu/libnvgpu-drv.export b/drivers/gpu/nvgpu/libnvgpu-drv.export
new file mode 100644
index 00000000..14900acc
--- /dev/null
+++ b/drivers/gpu/nvgpu/libnvgpu-drv.export
@@ -0,0 +1,1581 @@
1acr_ucode_patch_sig
2bitmap_clear
3bitmap_find_next_zero_area
4bitmap_find_next_zero_area_off
5bitmap_set
6bl_bootstrap_sec2
7boardobj_construct_super
8boardobj_destruct_super
9boardobjgrpconstruct_e255
10boardobjgrpconstruct_e32
11boardobjgrp_construct_super
12boardobjgrp_destruct_impl
13boardobjgrp_destruct_super
14boardobjgrpe32hdrset
15boardobjgrpmask_and
16boardobjgrpmask_bitclr
17boardobjgrpmask_bitget
18boardobjgrpmask_bitidxhighest
19boardobjgrpmask_bitidxlowest
20boardobjgrpmask_bitinv
21boardobjgrpmask_bitset
22boardobjgrpmask_bitsetcount
23boardobjgrpmask_clr
24boardobjgrpmask_copy
25boardobjgrpmask_export
26boardobjgrpmask_import
27boardobjgrpmask_init
28boardobjgrpmask_inv
29boardobjgrpmask_issubset
30boardobjgrpmask_iszero
31boardobjgrpmask_or
32boardobjgrpmask_set
33boardobjgrpmask_sizeeq
34boardobjgrpmask_xor
35boardobjgrp_pmucmd_construct_impl
36boardobjgrp_pmucmd_construct_impl_v1
37boardobjgrp_pmucmd_destroy_impl
38boardobjgrp_pmucmd_pmuinithandle_impl
39boardobjgrp_pmudatainit_legacy
40boardobjgrp_pmudatainit_super
41boardobjgrp_pmugetstatus_impl
42boardobjgrp_pmugetstatus_impl_v1
43boardobjgrp_pmuhdrdatainit_e255
44boardobjgrp_pmuhdrdatainit_e32
45boardobjgrp_pmuhdrdatainit_super
46boardobjgrp_pmuinithandle_impl
47boardobjgrp_pmuset_impl
48boardobjgrp_pmuset_impl_v1
49boardobj_implements_super
50boardobj_pmudatainit_super
51__bug
52channel_gk20a_alloc_job
53channel_gk20a_commit_va
54channel_gk20a_free_job
55channel_gk20a_is_prealloc_enabled
56channel_gk20a_joblist_is_empty
57channel_gk20a_joblist_lock
58channel_gk20a_joblist_unlock
59channel_gk20a_update_runlist
60channel_gm20b_bind
61channel_gp10b_commit_userd
62channel_gp10b_setup_ramfc
63channel_gv11b_setup_ramfc
64channel_gv11b_unbind
65clear_bit
66clear_halt_interrupt_status
67clk_domain_clk_prog_link
68clk_domain_get_f_or_v
69clk_domain_get_f_points
70clk_domain_pmu_setup
71clk_domain_print_vf_table
72clk_domain_sw_setup
73clk_fll_pmu_setup
74clk_fll_sw_setup
75clk_freq_controller_pmu_setup
76clk_freq_controller_sw_setup
77clk_get_fll_clks
78clk_pmu_freq_controller_load
79clk_pmu_vin_load
80clk_prog_pmu_setup
81clk_prog_sw_setup
82clk_set_fll_clks
83clk_vf_point_cache
84clk_vf_point_pmu_setup
85clk_vf_point_sw_setup
86clk_vin_pmu_setup
87clk_vin_sw_setup
88construct_clk_vf_point
89dbg_set_powergate
90dump_stack
91exec_regops_gk20a
92fb_gk20a_reset
93fb_gm20b_init_fs_state
94fecs_ucode_details
95find_first_bit
96find_first_zero_bit
97find_next_bit
98_fini
99free_acr_resources
100free_priv_cmdbuf
101get_ecc_override_val
102__get_pte_size
103__get_pte_size_fixed_map
104gk20a_alloc_fence
105gk20a_alloc_fence_pool
106gk20a_alloc_inst_block
107gk20a_alloc_obj_ctx
108gk20a_alloc_or_get_comptags
109gk20a_as_alloc_share
110gk20a_as_release_share
111gk20a_bus_bar1_bind
112gk20a_bus_init_hw
113gk20a_bus_isr
114gk20a_busy
115gk20a_busy_noresume
116gk20a_can_busy
117gk20a_ce2_isr
118gk20a_ce2_nonstall_isr
119gk20a_ce_create_context
120gk20a_ce_delete_context
121gk20a_ce_delete_context_priv
122gk20a_ce_destroy
123gk20a_ce_prepare_submit
124gk20a_ce_suspend
125gk20a_channel_abort
126gk20a_channel_abort_clean_up
127gk20a_channel_add_job
128gk20a_channel_alloc_gpfifo
129gk20a_channel_alloc_priv_cmdbuf
130gk20a_channel_clean_up_jobs
131gk20a_channel_close
132gk20a_channel_deterministic_idle
133gk20a_channel_deterministic_unidle
134gk20a_channel_free_usermode_buffers
135_gk20a_channel_get
136gk20a_channel_get_timescale_from_timeslice
137__gk20a_channel_kill
138_gk20a_channel_put
139gk20a_channel_resume
140gk20a_channel_semaphore_wakeup
141gk20a_channel_suspend
142gk20a_channel_sync_create
143gk20a_channel_sync_destroy
144gk20a_channel_sync_needs_sync_framework
145gk20a_channel_timeout_restart_all_channels
146gk20a_channel_update
147gk20a_channel_update_and_check_timeout
148gk20a_comptag_allocator_destroy
149gk20a_comptag_allocator_init
150gk20a_comptaglines_alloc
151gk20a_comptaglines_free
152gk20a_comptags_finish_clear
153gk20a_comptags_start_clear
154gk20a_dbg_gpu_broadcast_stop_trigger
155gk20a_dbg_gpu_clear_broadcast_stop_trigger
156gk20a_dbg_gpu_post_events
157gk20a_debug_dump_all_channel_status_ramfc
158gk20a_decode_ccsr_chan_status
159gk20a_decode_pbdma_chan_eng_ctx_status
160gk20a_deinit_pstate_support
161gk20a_detect_chip
162gk20a_disable_channel
163gk20a_disable_channel_tsg
164gk20a_disable_tsg
165gk20a_dump_channel_status_ramfc
166gk20a_dump_eng_status
167gk20a_dump_pbdma_status
168gk20a_elcg_init_idle_filters
169gk20a_enable_channel_tsg
170gk20a_enable_gr_hw
171gk20a_enable_priv_ring
172gk20a_enable_tsg
173gk20a_falcon_dump_stats
174gk20a_falcon_hal_sw_init
175gk20a_falcon_ops
176gk20a_fb_init_hw
177gk20a_fb_tlb_invalidate
178gk20a_fecs_dump_falcon_stats
179gk20a_fence_from_semaphore
180gk20a_fence_from_syncpt
181gk20a_fence_get
182gk20a_fence_install_fd
183gk20a_fence_is_expired
184gk20a_fence_put
185gk20a_fence_wait
186gk20a_fifo_abort_tsg
187gk20a_fifo_act_eng_interrupt_mask
188gk20a_fifo_alloc_inst
189gk20a_fifo_channel_from_chid
190gk20a_fifo_channel_status_is_ctx_reload
191gk20a_fifo_channel_status_is_next
192gk20a_fifo_channel_unbind
193gk20a_fifo_check_ch_ctxsw_timeout
194gk20a_fifo_check_tsg_ctxsw_timeout
195gk20a_fifo_default_timeslice_us
196gk20a_fifo_deferred_reset
197gk20a_fifo_delete_runlist
198gk20a_fifo_disable_all_engine_activity
199gk20a_fifo_disable_channel
200gk20a_fifo_disable_engine_activity
201gk20a_fifo_disable_tsg_sched
202gk20a_fifo_enable_all_engine_activity
203gk20a_fifo_enable_channel
204gk20a_fifo_enable_engine_activity
205gk20a_fifo_enable_tsg_sched
206gk20a_fifo_engine_enum_from_type
207gk20a_fifo_engine_interrupt_mask
208gk20a_fifo_error_ch
209gk20a_fifo_error_tsg
210gk20a_fifo_force_reset_ch
211gk20a_fifo_free_inst
212gk20a_fifo_get_all_ce_engine_reset_mask
213gk20a_fifo_get_engine_ids
214gk20a_fifo_get_engine_info
215gk20a_fifo_get_failing_engine_data
216gk20a_fifo_get_fast_ce_runlist_id
217gk20a_fifo_get_gr_engine_id
218gk20a_fifo_get_gr_runlist_id
219gk20a_fifo_get_mmu_fault_info
220gk20a_fifo_get_pbdma_signature
221gk20a_fifo_handle_pbdma_intr
222gk20a_fifo_handle_pbdma_intr_0
223gk20a_fifo_handle_pbdma_intr_1
224gk20a_fifo_handle_runlist_event
225gk20a_fifo_handle_sched_error
226gk20a_fifo_init_engine_info
227gk20a_fifo_interleave_level_name
228gk20a_fifo_intr_0_error_mask
229gk20a_fifo_is_engine_busy
230gk20a_fifo_is_preempt_pending
231gk20a_fifo_isr
232gk20a_fifo_issue_preempt
233gk20a_fifo_is_valid_engine_id
234gk20a_fifo_is_valid_runlist_id
235gk20a_fifo_mmu_fault_pending
236gk20a_fifo_nonstall_isr
237gk20a_fifo_pbdma_acquire_val
238gk20a_fifo_preempt
239gk20a_fifo_preempt_channel
240gk20a_fifo_preempt_tsg
241gk20a_fifo_recover
242gk20a_fifo_recover_ch
243gk20a_fifo_recover_tsg
244gk20a_fifo_reschedule_runlist
245gk20a_fifo_reset_engine
246gk20a_fifo_reset_pbdma_method
247gk20a_fifo_runlist_wait_pending
248gk20a_fifo_set_ctx_mmu_error_ch
249gk20a_fifo_set_ctx_mmu_error_tsg
250gk20a_fifo_set_runlist_interleave
251gk20a_fifo_set_runlist_state
252gk20a_fifo_setup_ramfc
253gk20a_fifo_setup_ramfc_for_privileged_channel
254gk20a_fifo_setup_userd
255gk20a_fifo_should_defer_engine_reset
256gk20a_fifo_suspend
257gk20a_fifo_teardown_ch_tsg
258gk20a_fifo_tsg_set_timeslice
259gk20a_fifo_tsg_unbind_channel
260gk20a_fifo_tsg_unbind_channel_verify_status
261gk20a_fifo_update_runlist
262gk20a_fifo_update_runlist_ids
263gk20a_fifo_userd_gp_get
264gk20a_fifo_userd_gp_put
265gk20a_fifo_userd_pb_get
266gk20a_fifo_wait_engine_idle
267gk20a_finalize_poweron
268gk20a_free_fence_pool
269gk20a_free_priv_cmdbuf
270gk20a_get
271gk20a_get_ch_runlist_entry
272gk20a_get_comptags
273gk20a_get_pde_pgsz
274gk20a_get_pte_pgsz
275gk20a_get_tsg_runlist_entry
276gk20a_gr_enable_exceptions
277gk20a_gr_enable_gpc_exceptions
278gk20a_gr_get_esr_sm_sel
279gk20a_gr_get_ovr_perf_regs
280gk20a_gr_get_sm_hww_global_esr
281gk20a_gr_get_sm_hww_warp_esr
282gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask
283gk20a_gr_gpc_offset
284gk20a_gr_handle_fecs_error
285gk20a_gr_handle_notify_pending
286gk20a_gr_handle_semaphore_pending
287gk20a_gr_init_ctxsw_hdr_data
288gk20a_gr_init_ovr_sm_dsm_perf
289gk20a_gr_isr
290gk20a_gr_lock_down_sm
291gk20a_gr_nonstall_isr
292gk20a_gr_reset
293gk20a_gr_resume_all_sms
294gk20a_gr_resume_single_sm
295gk20a_gr_set_shader_exceptions
296gk20a_gr_sm_debugger_attached
297gk20a_gr_suspend
298gk20a_gr_suspend_all_sms
299gk20a_gr_suspend_single_sm
300gk20a_gr_tpc_offset
301gk20a_gr_wait_for_sm_lock_down
302gk20a_gr_wait_initialized
303_gk20a_gr_zbc_set_table
304gk20a_gr_zbc_set_table
305gk20a_idle
306gk20a_idle_nosuspend
307gk20a_init_ce_support
308gk20a_init_channel_support
309gk20a_init_fence
310gk20a_init_fifo_reset_enable_hw
311gk20a_init_fifo_setup_hw
312gk20a_init_fifo_setup_sw
313gk20a_init_fifo_setup_sw_common
314gk20a_init_fifo_support
315gk20a_init_gpu_characteristics
316gk20a_init_gr
317gk20a_init_gr_support
318gk20a_init_inst_block
319gk20a_init_mm_setup_hw
320gk20a_init_pmu_setup_hw1
321gk20a_init_pstate_pmu_support
322gk20a_init_pstate_support
323gk20a_init_sw_bundle
324gk20a_init_therm_support
325gk20a_init_tsg_support
326gk20a_is_channel_ctx_resident
327gk20a_is_channel_marked_as_tsg
328gk20a_is_fault_engine_subid_gpc
329gk20a_is_pmu_supported
330gk20a_locked_gmmu_map
331gk20a_locked_gmmu_unmap
332gk20a_mc_boot_0
333gk20a_mc_disable
334gk20a_mc_enable
335gk20a_mc_reset
336gk20a_mm_cbc_clean
337gk20a_mm_fb_flush
338gk20a_mm_get_iommu_bit
339gk20a_mm_get_mmu_levels
340gk20a_mm_init_pdb
341gk20a_mm_l2_flush
342gk20a_mm_l2_invalidate
343gk20a_open_new_channel
344gk20a_perfbuf_disable_locked
345gk20a_perfbuf_enable_locked
346gk20a_pmu_dump_elpg_stats
347gk20a_pmu_dump_falcon_stats
348gk20a_pmu_elpg_statistics
349gk20a_pmu_engine_reset
350gk20a_pmu_get_irqdest
351gk20a_pmu_init_perfmon_counter
352gk20a_pmu_is_engine_in_reset
353gk20a_pmu_is_interrupted
354gk20a_pmu_isr
355gk20a_pmu_msgq_tail
356gk20a_pmu_mutex_acquire
357gk20a_pmu_mutex_release
358gk20a_pmu_pg_engines_list
359gk20a_pmu_pg_feature_list
360gk20a_pmu_pg_idle_counter_config
361gk20a_pmu_queue_head
362gk20a_pmu_queue_tail
363gk20a_pmu_read_idle_counter
364gk20a_pmu_reset_idle_counter
365gk20a_pmu_save_zbc
366gk20a_pramin_enter
367gk20a_pramin_exit
368gk20a_prepare_poweroff
369gk20a_priv_ring_isr
370gk20a_put
371gk20a_read_ptimer
372gk20a_refch_from_inst_ptr
373gk20a_runlist_construct_locked
374gk20a_tsg_bind_channel
375gk20a_tsg_event_id_post_event
376gk20a_tsg_get_timeslice
377gk20a_tsg_open
378gk20a_tsg_release
379gk20a_tsg_set_runlist_interleave
380gk20a_tsg_set_timeslice
381gk20a_tsg_unbind_channel
382__gk20a_vm_bind_channel
383gk20a_vm_bind_channel
384gk20a_vm_release_share
385gk20a_wait_channel_idle
386gk20a_wait_for_idle
387gk20a_wait_until_counter_is_N
388__gk20a_warn_on_no_regs
389gk20a_write_dmatrfbase
390gm20a_gr_disable_rd_coalesce
391gm20b_alloc_blob_space
392gm20b_apply_smpc_war
393gm20b_blcg_bus_load_gating_prod
394gm20b_blcg_ctxsw_firmware_load_gating_prod
395gm20b_blcg_fb_load_gating_prod
396gm20b_blcg_fifo_load_gating_prod
397gm20b_blcg_gr_load_gating_prod
398gm20b_blcg_ltc_load_gating_prod
399gm20b_blcg_pmu_load_gating_prod
400gm20b_blcg_pwr_csb_load_gating_prod
401gm20b_blcg_xbar_load_gating_prod
402gm20b_bootstrap_hs_flcn
403gm20b_bus_bar1_bind
404gm20b_clk_get_gpcclk_clock_counter
405gm20b_clk_get_pll_debug_data
406gm20b_clk_get_voltage
407gm20b_clk_is_prepared
408gm20b_clk_pll_reg_write
409gm20b_clk_prepare
410gm20b_clk_unprepare
411gm20b_determine_L2_size_bytes
412gm20b_device_info_data_parse
413gm20b_fb_compressible_page_size
414gm20b_fb_compression_align_mask
415gm20b_fb_compression_page_size
416gm20b_fb_debug_mode_enabled
417gm20b_fb_dump_vpr_wpr_info
418gm20b_fb_read_wpr_info
419gm20b_fb_set_debug_mode
420gm20b_fb_set_mmu_page_size
421gm20b_fb_set_use_full_comp_tag_line
422gm20b_fb_vpr_info_fetch
423gm20b_fifo_get_num_fifos
424gm20b_fifo_init_pbdma_intr_descs
425gm20b_fifo_trigger_mmu_fault
426gm20b_fifo_tsg_verify_status_ctx_reload
427gm20b_flcn_populate_bl_dmem_desc
428gm20b_flush_ltc
429gm20b_fuse_check_priv_security
430gm20b_get_context_whitelist_ranges
431gm20b_get_context_whitelist_ranges_count
432gm20b_get_global_whitelist_ranges
433gm20b_get_global_whitelist_ranges_count
434gm20b_get_gpc_pll_parms
435gm20b_get_kind_invalid
436gm20b_get_kind_pitch
437gm20b_get_litter_value
438gm20b_get_qctl_whitelist
439gm20b_get_qctl_whitelist_count
440gm20b_get_qctl_whitelist_ranges
441gm20b_get_qctl_whitelist_ranges_count
442gm20b_get_runcontrol_whitelist
443gm20b_get_runcontrol_whitelist_count
444gm20b_get_runcontrol_whitelist_ranges
445gm20b_get_runcontrol_whitelist_ranges_count
446gm20b_gpcclk_set_rate
447gm20b_gpu_phys_addr
448gm20b_gr_clear_sm_error_state
449gm20b_gr_clear_sm_hww
450gm20b_gr_record_sm_error_state
451gm20b_gr_update_sm_error_state
452gm20b_init_clk_setup_sw
453gm20b_init_clk_support
454gm20b_init_hal
455gm20b_init_nspmu_setup_hw1
456gm20b_init_pmu_setup_hw1
457gm20b_init_therm_setup_hw
458gm20b_is_lazy_bootstrap
459gm20b_is_pmu_supported
460gm20b_is_priv_load
461gm20b_load_falcon_ucode
462gm20b_ltc_cbc_ctrl
463gm20b_ltc_cbc_fix_config
464gm20b_ltc_init_cbc
465gm20b_ltc_init_comptags
466gm20b_ltc_init_fs_state
467gm20b_ltc_isr
468gm20b_ltc_set_enabled
469gm20b_ltc_set_zbc_color_entry
470gm20b_ltc_set_zbc_depth_entry
471gm20b_mm_get_big_page_sizes
472gm20b_mm_get_default_big_page_size
473gm20b_mm_is_bar1_supported
474gm20b_mm_set_big_page_size
475gm20b_mm_support_sparse
476gm20b_pmu_init_acr
477gm20b_pmu_load_lsf
478gm20b_pmu_populate_loader_cfg
479gm20b_pmu_setup_elpg
480gm20b_recalc_rate
481gm20b_round_rate
482gm20b_setup_apertures
483gm20b_slcg_bus_load_gating_prod
484gm20b_slcg_ce2_load_gating_prod
485gm20b_slcg_chiplet_load_gating_prod
486gm20b_slcg_ctxsw_firmware_load_gating_prod
487gm20b_slcg_fb_load_gating_prod
488gm20b_slcg_fifo_load_gating_prod
489gm20b_slcg_perf_load_gating_prod
490gm20b_slcg_pmu_load_gating_prod
491gm20b_slcg_priring_load_gating_prod
492gm20b_slcg_pwr_csb_load_gating_prod
493gm20b_slcg_therm_load_gating_prod
494gm20b_slcg_xbar_load_gating_prod
495gm20b_suspend_clk_support
496gm20b_update_lspmu_cmdline_args
497gm20b_wpr_info
498gm20b_write_dmatrfbase
499gp106_alloc_blob_space
500gp106_apply_smpc_war
501gp106_bios_init
502gp106_bios_preos_wait_for_halt
503gp106_blcg_bus_load_gating_prod
504gp106_blcg_ce_load_gating_prod
505gp106_blcg_fb_load_gating_prod
506gp106_blcg_fifo_load_gating_prod
507gp106_blcg_gr_load_gating_prod
508gp106_blcg_ltc_load_gating_prod
509gp106_blcg_pmu_load_gating_prod
510gp106_blcg_xbar_load_gating_prod
511gp106_bootstrap_hs_flcn
512gp106_clk_measure_freq
513gp106_configure_therm_alert
514gp106_crystal_clk_hz
515gp106_elcg_init_idle_filters
516gp106_falcon_hal_sw_init
517gp106_fb_reset
518gp106_fifo_get_num_fifos
519gp106_flcn_populate_bl_dmem_desc
520gp106_fuse_check_priv_security
521gp106_get_arbiter_clk_default
522gp106_get_arbiter_clk_domains
523gp106_get_arbiter_clk_range
524gp106_get_context_whitelist_ranges
525gp106_get_context_whitelist_ranges_count
526gp106_get_global_whitelist_ranges
527gp106_get_global_whitelist_ranges_count
528gp106_get_internal_sensor_curr_temp
529gp106_get_internal_sensor_limits
530gp106_get_qctl_whitelist
531gp106_get_qctl_whitelist_count
532gp106_get_qctl_whitelist_ranges
533gp106_get_qctl_whitelist_ranges_count
534gp106_get_runcontrol_whitelist
535gp106_get_runcontrol_whitelist_count
536gp106_get_runcontrol_whitelist_ranges
537gp106_get_runcontrol_whitelist_ranges_count
538gp106_init_clk_support
539gp106_init_hal
540gp106_is_lazy_bootstrap
541gp106_is_pmu_supported
542gp106_is_priv_load
543gp106_load_falcon_ucode
544gp106_mclk_change
545gp106_mclk_deinit
546gp106_mclk_init
547gp106_mm_get_vidmem_size
548gp106_pg_param_init
549gp106_pmu_elpg_statistics
550gp106_pmu_engine_reset
551gp106_pmu_is_engine_in_reset
552gp106_pmu_is_lpwr_feature_supported
553gp106_pmu_pg_engines_list
554gp106_pmu_pg_feature_list
555gp106_pmu_populate_loader_cfg
556gp106_prepare_ucode_blob
557gp106_sec2_reset
558gp106_slcg_bus_load_gating_prod
559gp106_slcg_ce2_load_gating_prod
560gp106_slcg_chiplet_load_gating_prod
561gp106_slcg_ctxsw_firmware_load_gating_prod
562gp106_slcg_fb_load_gating_prod
563gp106_slcg_fifo_load_gating_prod
564gp106_slcg_perf_load_gating_prod
565gp106_slcg_pmu_load_gating_prod
566gp106_slcg_priring_load_gating_prod
567gp106_slcg_therm_load_gating_prod
568gp106_slcg_xbar_load_gating_prod
569gp106_suspend_clk_support
570gp106_wpr_info
571gp10b_apply_smpc_war
572gp10b_blcg_bus_load_gating_prod
573gp10b_blcg_ce_load_gating_prod
574gp10b_blcg_ctxsw_firmware_load_gating_prod
575gp10b_blcg_fb_load_gating_prod
576gp10b_blcg_fifo_load_gating_prod
577gp10b_blcg_gr_load_gating_prod
578gp10b_blcg_ltc_load_gating_prod
579gp10b_blcg_pmu_load_gating_prod
580gp10b_blcg_pwr_csb_load_gating_prod
581gp10b_blcg_xbar_load_gating_prod
582gp10b_ce_isr
583gp10b_ce_nonstall_isr
584gp10b_determine_L2_size_bytes
585gp10b_device_info_data_parse
586gp10b_elcg_init_idle_filters
587gp10b_fb_compressible_page_size
588gp10b_fb_compression_page_size
589gp10b_fifo_engine_enum_from_type
590gp10b_fifo_get_mmu_fault_info
591gp10b_fifo_get_pbdma_signature
592gp10b_fifo_init_pbdma_intr_descs
593gp10b_fifo_resetup_ramfc
594gp10b_fuse_check_priv_security
595gp10b_get_context_whitelist_ranges
596gp10b_get_context_whitelist_ranges_count
597gp10b_get_global_whitelist_ranges
598gp10b_get_global_whitelist_ranges_count
599gp10b_get_litter_value
600gp10b_get_qctl_whitelist
601gp10b_get_qctl_whitelist_count
602gp10b_get_qctl_whitelist_ranges
603gp10b_get_qctl_whitelist_ranges_count
604gp10b_get_runcontrol_whitelist
605gp10b_get_runcontrol_whitelist_count
606gp10b_get_runcontrol_whitelist_ranges
607gp10b_get_runcontrol_whitelist_ranges_count
608gp10b_gr_get_sm_hww_warp_esr
609gp10b_init_bar2_mm_hw_setup
610gp10b_init_bar2_vm
611gp10b_init_gpu_characteristics
612gp10b_init_hal
613gp10b_init_mm_setup_hw
614gp10b_init_pmu_setup_hw1
615gp10b_init_therm_setup_hw
616gp10b_is_lazy_bootstrap
617gp10b_is_pmu_supported
618gp10b_is_priv_load
619gp10b_load_falcon_ucode
620gp10b_ltc_cbc_ctrl
621gp10b_ltc_init_comptags
622gp10b_ltc_init_fs_state
623gp10b_ltc_isr
624gp10b_ltc_set_enabled
625gp10b_mm_get_default_big_page_size
626gp10b_mm_get_iommu_bit
627gp10b_mm_get_mmu_levels
628gp10b_mm_init_pdb
629gp10b_pg_gr_init
630gp10b_pmu_elpg_statistics
631gp10b_pmu_setup_elpg
632gp10b_priv_ring_decode_error_code
633gp10b_priv_ring_isr
634gp10b_remove_bar2_vm
635gp10b_replayable_pagefault_buffer_clear_overflow
636gp10b_replayable_pagefault_buffer_deinit
637gp10b_replayable_pagefault_buffer_get_index
638gp10b_replayable_pagefault_buffer_info
639gp10b_replayable_pagefault_buffer_init
640gp10b_replayable_pagefault_buffer_is_empty
641gp10b_replayable_pagefault_buffer_is_full
642gp10b_replayable_pagefault_buffer_is_overflow
643gp10b_replayable_pagefault_buffer_put_index
644gp10b_slcg_bus_load_gating_prod
645gp10b_slcg_ce2_load_gating_prod
646gp10b_slcg_chiplet_load_gating_prod
647gp10b_slcg_ctxsw_firmware_load_gating_prod
648gp10b_slcg_fb_load_gating_prod
649gp10b_slcg_fifo_load_gating_prod
650gp10b_slcg_perf_load_gating_prod
651gp10b_slcg_pmu_load_gating_prod
652gp10b_slcg_priring_load_gating_prod
653gp10b_slcg_pwr_csb_load_gating_prod
654gp10b_slcg_therm_load_gating_prod
655gp10b_slcg_xbar_load_gating_prod
656gp10b_write_dmatrfbase
657gpccs_ucode_details
658gpu_init_hal
659gr_gk20a_add_ctxsw_reg_perf_pma
660gr_gk20a_add_ctxsw_reg_pm_fbpa
661gr_gk20a_add_zbc
662gr_gk20a_add_zbc_color
663gr_gk20a_add_zbc_depth
664gr_gk20a_alloc_gr_ctx
665gr_gk20a_bind_ctxsw_zcull
666gr_gk20a_blcg_gr_load_gating_prod
667gr_gk20a_clear_sm_errors
668gr_gk20a_commit_global_ctx_buffers
669gr_gk20a_commit_global_pagepool
670gr_gk20a_commit_global_timeslice
671gr_gk20a_commit_inst
672gr_gk20a_create_priv_addr_table
673gr_gk20a_ctx_patch_write
674gr_gk20a_ctx_patch_write_begin
675gr_gk20a_ctx_patch_write_end
676gr_gk20a_ctx_wait_ucode
677gr_gk20a_decode_priv_addr
678gr_gk20a_disable_ctxsw
679gr_gk20a_enable_ctxsw
680gr_gk20a_enable_hww_exceptions
681__gr_gk20a_exec_ctx_ops
682gr_gk20a_exec_ctx_ops
683gr_gk20a_fecs_ctx_bind_channel
684gr_gk20a_fecs_ctx_image_save
685gr_gk20a_fecs_get_reglist_img_size
686gr_gk20a_fecs_host_int_enable
687gr_gk20a_fecs_set_reglist_bind_inst
688gr_gk20a_fecs_set_reglist_virtual_addr
689gr_gk20a_free_gr_ctx
690gr_gk20a_free_tsg_gr_ctx
691gr_gk20a_get_ctx_buffer_offsets
692gr_gk20a_get_ctx_id
693gr_gk20a_get_ctxsw_zcull_size
694gr_gk20a_get_patch_slots
695gr_gk20a_get_pm_ctx_buffer_offsets
696gr_gk20a_get_tpc_count
697gr_gk20a_get_zcull_info
698gr_gk20a_halt_pipe
699gr_gk20a_handle_sm_exception
700gr_gk20a_handle_tex_exception
701gr_gk20a_init_blcg_mode
702gr_gk20a_init_cg_mode
703gr_gk20a_init_ctx_state
704gr_gk20a_init_ctxsw_ucode
705gr_gk20a_init_ctx_vars
706gr_gk20a_init_ctx_vars_sim
707gr_gk20a_init_elcg_mode
708gr_gk20a_init_fs_state
709gr_gk20a_init_sm_id_table
710gr_gk20a_inval_icache
711gr_gk20a_load_ctxsw_ucode
712gr_gk20a_load_ctxsw_ucode_boot
713gr_gk20a_load_ctxsw_ucode_header
714gr_gk20a_load_falcon_bind_instblk
715gr_gk20a_load_golden_ctx_image
716gr_gk20a_load_zbc_default_table
717gr_gk20a_pg_gr_load_gating_prod
718gr_gk20a_pmu_save_zbc
719gr_gk20a_program_zcull_mapping
720gr_gk20a_query_zbc
721gr_gk20a_resume_context
722gr_gk20a_resume_contexts
723gr_gk20a_resume_from_pause
724gr_gk20a_set_sm_debug_mode
725gr_gk20a_setup_rop_mapping
726gr_gk20a_slcg_gr_load_gating_prod
727gr_gk20a_slcg_perf_load_gating_prod
728gr_gk20a_slcg_therm_load_gating_prod
729gr_gk20a_split_ppc_broadcast_addr
730gr_gk20a_submit_fecs_method_op
731gr_gk20a_submit_fecs_sideband_method_op
732gr_gk20a_suspend_context
733gr_gk20a_suspend_contexts
734gr_gk20a_tpc_enabled_exceptions
735gr_gk20a_trigger_suspend
736gr_gk20a_update_hwpm_ctxsw_mode
737gr_gk20a_update_smpc_ctxsw_mode
738gr_gk20a_wait_fe_idle
739gr_gk20a_wait_for_pause
740gr_gk20a_wait_idle
741gr_gk20a_write_pm_ptr
742gr_gk20a_write_zcull_ptr
743gr_gm20b_alloc_gr_ctx
744gr_gm20b_bpt_reg_info
745gr_gm20b_bundle_cb_defaults
746gr_gm20b_calc_global_ctx_buffer_size
747gr_gm20b_cb_size_default
748gr_gm20b_commit_global_attrib_cb
749gr_gm20b_commit_global_bundle_cb
750gr_gm20b_commit_global_cb_manager
751gr_gm20b_commit_global_pagepool
752gr_gm20b_detect_sm_arch
753gr_gm20b_dump_gr_status_regs
754gr_gm20b_enable_cde_in_fecs
755gr_gm20b_get_access_map
756gr_gm20b_get_fbp_en_mask
757gr_gm20b_get_gpc_tpc_mask
758gr_gm20b_get_max_fbps_count
759gr_gm20b_get_max_ltc_per_fbp
760gr_gm20b_get_max_lts_per_ltc
761gr_gm20b_get_netlist_name
762gr_gm20b_get_pmm_per_chiplet_offset
763gr_gm20b_get_preemption_mode_flags
764gr_gm20b_get_sm_dsm_perf_ctrl_regs
765gr_gm20b_get_sm_dsm_perf_regs
766gr_gm20b_get_tpc_num
767gr_gm20b_handle_sw_method
768gr_gm20b_init_cyclestats
769gr_gm20b_init_fs_state
770gr_gm20b_init_gpc_mmu
771gr_gm20b_init_sm_dsm_reg_info
772gr_gm20b_is_firmware_defined
773gr_gm20b_is_ltcn_ltss_addr
774gr_gm20b_is_ltcs_ltss_addr
775gr_gm20b_is_tpc_addr
776gr_gm20b_is_valid_class
777gr_gm20b_is_valid_compute_class
778gr_gm20b_is_valid_gfx_class
779gr_gm20b_load_ctxsw_ucode
780gr_gm20b_load_ctxsw_ucode_segments
781gr_gm20b_load_smid_config
782gr_gm20b_load_tpc_mask
783gr_gm20b_pagepool_default_size
784gr_gm20b_pg_gr_load_gating_prod
785gr_gm20b_program_sm_id_numbering
786gr_gm20b_rop_l2_en_mask
787gr_gm20b_set_alpha_circular_buffer_size
788gr_gm20b_set_circular_buffer_size
789gr_gm20b_set_gpc_tpc_mask
790gr_gm20b_set_hww_esr_report_mask
791gr_gm20b_set_rd_coalesce
792gr_gm20b_slcg_gr_load_gating_prod
793gr_gm20b_split_ltc_broadcast_addr
794gr_gm20b_split_lts_broadcast_addr
795gr_gm20b_update_ctxsw_preemption_mode
796gr_gm20b_update_pc_sampling
797gr_gp106_cb_size_default
798gr_gp106_get_netlist_name
799gr_gp106_handle_sw_method
800gr_gp106_is_firmware_defined
801gr_gp106_is_valid_class
802gr_gp106_pagepool_default_size
803gr_gp106_pg_gr_load_gating_prod
804gr_gp106_set_ctxsw_preemption_mode
805gr_gp106_slcg_gr_load_gating_prod
806gr_gp10b_add_zbc_color
807gr_gp10b_add_zbc_depth
808gr_gp10b_alloc_buffer
809gr_gp10b_alloc_gr_ctx
810gr_gp10b_calc_global_ctx_buffer_size
811gr_gp10b_cb_size_default
812gr_gp10b_commit_global_attrib_cb
813gr_gp10b_commit_global_bundle_cb
814gr_gp10b_commit_global_cb_manager
815gr_gp10b_commit_global_pagepool
816gr_gp10b_dump_ctxsw_stats
817gr_gp10b_dump_gr_status_regs
818gr_gp10b_get_access_map
819gr_gp10b_get_gpcs_swdx_dss_zbc_c_format_reg
820gr_gp10b_get_gpcs_swdx_dss_zbc_z_format_reg
821gr_gp10b_get_max_gfxp_wfi_timeout_count
822gr_gp10b_get_netlist_name
823gr_gp10b_get_preemption_mode_flags
824gr_gp10b_handle_fecs_error
825gr_gp10b_handle_sm_exception
826gr_gp10b_handle_sw_method
827gr_gp10b_handle_tex_exception
828gr_gp10b_init_ctx_state
829gr_gp10b_init_ctxsw_hdr_data
830gr_gp10b_init_czf_bypass
831gr_gp10b_init_fs_state
832gr_gp10b_init_gfxp_wfi_timeout_count
833gr_gp10b_init_preemption_state
834gr_gp10b_is_firmware_defined
835gr_gp10b_is_valid_class
836gr_gp10b_is_valid_compute_class
837gr_gp10b_is_valid_gfx_class
838gr_gp10b_load_smid_config
839gr_gp10b_pagepool_default_size
840gr_gp10b_pg_gr_load_gating_prod
841gr_gp10b_pre_process_sm_exception
842gr_gp10b_set_alpha_circular_buffer_size
843gr_gp10b_set_bes_crop_debug3
844gr_gp10b_set_bes_crop_debug4
845gr_gp10b_set_boosted_ctx
846gr_gp10b_set_cilp_preempt_pending
847gr_gp10b_set_circular_buffer_size
848gr_gp10b_set_ctxsw_preemption_mode
849gr_gp10b_set_czf_bypass
850gr_gp10b_set_gpc_tpc_mask
851gr_gp10b_set_preemption_buffer_va
852gr_gp10b_set_preemption_mode
853gr_gp10b_slcg_gr_load_gating_prod
854gr_gp10b_suspend_context
855gr_gp10b_suspend_contexts
856gr_gp10b_update_boosted_ctx
857gr_gp10b_update_ctxsw_preemption_mode
858gr_gp10b_wait_empty
859gr_gv100_add_ctxsw_reg_perf_pma
860gr_gv100_add_ctxsw_reg_pm_fbpa
861gr_gv100_bundle_cb_defaults
862gr_gv100_cb_size_default
863gr_gv100_get_netlist_name
864gr_gv100_get_patch_slots
865gr_gv100_init_sm_id_table
866gr_gv100_is_firmware_defined
867gr_gv100_set_gpc_tpc_mask
868gr_gv11b_add_zbc_stencil
869gr_gv11b_add_zbc_type_s
870gr_gv11b_alloc_buffer
871gr_gv11b_bundle_cb_defaults
872gr_gv11b_calc_global_ctx_buffer_size
873gr_gv11b_cb_size_default
874gr_gv11b_commit_global_attrib_cb
875gr_gv11b_commit_global_timeslice
876gr_gv11b_commit_inst
877gr_gv11b_create_priv_addr_table
878gr_gv11b_decode_priv_addr
879gr_gv11b_detect_sm_arch
880gr_gv11b_dump_gr_status_regs
881gr_gv11b_ecc_init_scrub_reg
882gr_gv11b_enable_exceptions
883gr_gv11b_enable_gpc_exceptions
884gr_gv11b_enable_hww_exceptions
885gr_gv11b_fecs_host_int_enable
886gr_gv11b_get_access_map
887gr_gv11b_get_gpcs_swdx_dss_zbc_c_format_reg
888gr_gv11b_get_gpcs_swdx_dss_zbc_z_format_reg
889gr_gv11b_get_max_gfxp_wfi_timeout_count
890gr_gv11b_get_netlist_name
891gr_gv11b_get_pmm_per_chiplet_offset
892gr_gv11b_handle_fecs_error
893gr_gv11b_handle_gcc_exception
894gr_gv11b_handle_gpc_gpccs_exception
895gr_gv11b_handle_gpc_gpcmmu_exception
896gr_gv11b_handle_ssync_hww
897gr_gv11b_handle_sw_method
898gr_gv11b_handle_tex_exception
899gr_gv11b_handle_tpc_mpc_exception
900gr_gv11b_handle_tpc_sm_ecc_exception
901gr_gv11b_init_elcg_mode
902gr_gv11b_init_fs_state
903gr_gv11b_init_gfxp_wfi_timeout_count
904gr_gv11b_init_gpc_mmu
905gr_gv11b_init_preemption_state
906gr_gv11b_init_sw_veid_bundle
907gr_gv11b_is_firmware_defined
908gr_gv11b_is_valid_class
909gr_gv11b_is_valid_compute_class
910gr_gv11b_is_valid_gfx_class
911gr_gv11b_load_smid_config
912gr_gv11b_load_stencil_default_tbl
913gr_gv11b_load_stencil_tbl
914gr_gv11b_load_tpc_mask
915gr_gv11b_pagepool_default_size
916gr_gv11b_pg_gr_load_gating_prod
917gr_gv11b_pre_process_sm_exception
918gr_gv11b_program_sm_id_numbering
919gr_gv11b_program_zcull_mapping
920gr_gv11b_set_alpha_circular_buffer_size
921gr_gv11b_set_circular_buffer_size
922gr_gv11b_set_ctxsw_preemption_mode
923gr_gv11b_set_gpc_tpc_mask
924gr_gv11b_set_preemption_buffer_va
925gr_gv11b_setup_rop_mapping
926gr_gv11b_slcg_gr_load_gating_prod
927gr_gv11b_update_ctxsw_preemption_mode
928gr_gv11b_wait_empty
929gr_gv11b_write_pm_ptr
930gr_gv11b_write_zcull_ptr
931gr_gv11b_zbc_s_query_table
932gv100_apply_ctxsw_timeout_intr
933gv100_apply_smpc_war
934gv100_bios_preos_reload_check
935gv100_bios_preos_wait_for_halt
936gv100_falcon_hal_sw_init
937gv100_fb_enable_nvlink
938gv100_fb_init_nvlink
939gv100_fb_memory_unlock
940gv100_fb_reset
941gv100_fifo_get_num_fifos
942gv100_fifo_get_preempt_timeout
943gv100_get_context_whitelist_ranges
944gv100_get_context_whitelist_ranges_count
945gv100_get_global_whitelist_ranges
946gv100_get_global_whitelist_ranges_count
947gv100_get_qctl_whitelist
948gv100_get_qctl_whitelist_count
949gv100_get_qctl_whitelist_ranges
950gv100_get_qctl_whitelist_ranges_count
951gv100_get_runcontrol_whitelist
952gv100_get_runcontrol_whitelist_count
953gv100_get_runcontrol_whitelist_ranges
954gv100_get_runcontrol_whitelist_ranges_count
955gv100_init_gpu_characteristics
956gv100_init_hal
957gv100_load_falcon_ucode
958gv100_mc_is_intr_nvlink_pending
959gv100_mc_is_stall_and_eng_intr_pending
960gv100_mm_get_flush_retries
961gv100_mm_get_vidmem_size
962gv100_nvlink_discover_ioctrl
963gv100_nvlink_discover_link
964gv100_nvlink_early_init
965gv100_nvlink_init
966gv100_nvlink_interface_init
967gv100_nvlink_isr
968gv100_nvlink_link_early_init
969gv100_nvlink_link_get_mode
970gv100_nvlink_link_get_rx_sublink_state
971gv100_nvlink_link_get_state
972gv100_nvlink_link_get_sublink_mode
973gv100_nvlink_link_get_tx_sublink_state
974gv100_nvlink_link_set_mode
975gv100_nvlink_link_set_sublink_mode
976gv100_nvlink_reg_init
977gv100_nvlink_shutdown
978gv100_pmu_init_acr
979gv11b_alloc_blob_space
980gv11b_alloc_subctx_header
981gv11b_apply_smpc_war
982gv11b_blcg_bus_load_gating_prod
983gv11b_blcg_ce_load_gating_prod
984gv11b_blcg_ctxsw_firmware_load_gating_prod
985gv11b_blcg_fb_load_gating_prod
986gv11b_blcg_fifo_load_gating_prod
987gv11b_blcg_gr_load_gating_prod
988gv11b_blcg_ltc_load_gating_prod
989gv11b_blcg_pmu_load_gating_prod
990gv11b_blcg_pwr_csb_load_gating_prod
991gv11b_blcg_xbar_load_gating_prod
992gv11b_bootstrap_hs_flcn
993gv11b_ce_get_num_lce
994gv11b_ce_get_num_pce
995gv11b_ce_isr
996gv11b_ce_mthd_buffer_fault_in_bar2_fault
997gv11b_detect_ecc_enabled_units
998gv11b_dump_channel_status_ramfc
999gv11b_dump_eng_status
1000gv11b_elcg_init_idle_filters
1001gv11b_fb_disable_hub_intr
1002gv11b_fb_enable_hub_intr
1003gv11b_fb_fault_buf_configure_hw
1004gv11b_fb_fault_buf_set_state_hw
1005gv11b_fb_hub_isr
1006gv11b_fb_init_cbc
1007gv11b_fb_init_fs_state
1008gv11b_fb_is_fault_buf_enabled
1009gv11b_fb_mmu_fault_pending
1010gv11b_fb_reset
1011gv11b_fifo_deinit_eng_method_buffers
1012gv11b_fifo_enable_tsg
1013gv11b_fifo_get_num_fifos
1014gv11b_fifo_get_preempt_timeout
1015gv11b_fifo_handle_ctxsw_timeout
1016gv11b_fifo_handle_pbdma_intr_0
1017gv11b_fifo_handle_pbdma_intr_1
1018gv11b_fifo_handle_sched_error
1019gv11b_fifo_init_eng_method_buffers
1020gv11b_fifo_init_pbdma_intr_descs
1021gv11b_fifo_intr_0_error_mask
1022gv11b_fifo_is_preempt_pending
1023gv11b_fifo_preempt_channel
1024gv11b_fifo_preempt_ch_tsg
1025gv11b_fifo_preempt_tsg
1026gv11b_fifo_reset_pbdma_and_eng_faulted
1027gv11b_fifo_teardown_ch_tsg
1028gv11b_fifo_tsg_verify_status_faulted
1029gv11b_free_subctx_header
1030gv11b_get_ch_runlist_entry
1031gv11b_get_context_whitelist_ranges
1032gv11b_get_context_whitelist_ranges_count
1033gv11b_get_global_whitelist_ranges
1034gv11b_get_global_whitelist_ranges_count
1035gv11b_get_litter_value
1036gv11b_get_qctl_whitelist
1037gv11b_get_qctl_whitelist_count
1038gv11b_get_qctl_whitelist_ranges
1039gv11b_get_qctl_whitelist_ranges_count
1040gv11b_get_runcontrol_whitelist
1041gv11b_get_runcontrol_whitelist_count
1042gv11b_get_runcontrol_whitelist_ranges
1043gv11b_get_runcontrol_whitelist_ranges_count
1044gv11b_get_tsg_runlist_entry
1045gv11b_gpu_phys_addr
1046gv11b_gr_access_smpc_reg
1047gv11b_gr_bpt_reg_info
1048gv11b_gr_clear_sm_hww
1049gv11b_gr_decode_egpc_addr
1050gv11b_gr_egpc_etpc_priv_addr_table
1051gv11b_gr_get_egpc_base
1052gv11b_gr_get_egpc_etpc_num
1053gv11b_gr_get_esr_sm_sel
1054gv11b_gr_get_ovr_perf_regs
1055gv11b_gr_get_sm_dsm_perf_ctrl_regs
1056gv11b_gr_get_sm_dsm_perf_regs
1057gv11b_gr_get_sm_hww_global_esr
1058gv11b_gr_get_sm_hww_warp_esr
1059gv11b_gr_get_sm_no_lock_down_hww_global_esr_mask
1060gv11b_gr_init_ovr_sm_dsm_perf
1061gv11b_gr_init_sm_dsm_reg_info
1062gv11b_gr_lock_down_sm
1063gv11b_gr_pri_is_egpc_addr
1064gv11b_gr_pri_is_etpc_addr
1065gv11b_gr_record_sm_error_state
1066gv11b_gr_resume_all_sms
1067gv11b_gr_resume_from_pause
1068gv11b_gr_resume_single_sm
1069gv11b_gr_set_hww_esr_report_mask
1070gv11b_gr_set_sm_debug_mode
1071gv11b_gr_sm_debugger_attached
1072gv11b_gr_sm_offset
1073gv11b_gr_sm_trigger_suspend
1074gv11b_gr_suspend_all_sms
1075gv11b_gr_suspend_single_sm
1076gv11b_gr_update_sm_error_state
1077gv11b_gr_wait_for_sm_lock_down
1078gv11b_init_bar2_mm_hw_setup
1079gv11b_init_fifo_reset_enable_hw
1080gv11b_init_fifo_setup_hw
1081gv11b_init_gpu_characteristics
1082gv11b_init_hal
1083gv11b_init_inst_block
1084gv11b_init_mm_setup_hw
1085gv11b_init_pmu_setup_hw1
1086gv11b_init_subcontext_pdb
1087gv11b_init_therm_setup_hw
1088gv11b_is_fault_engine_subid_gpc
1089gv11b_is_lazy_bootstrap
1090gv11b_is_pmu_supported
1091gv11b_is_priv_load
1092gv11b_ltc_init_fs_state
1093gv11b_ltc_isr
1094gv11b_ltc_set_zbc_stencil_entry
1095gv11b_mc_is_intr_hub_pending
1096gv11b_mc_is_stall_and_eng_intr_pending
1097gv11b_mm_fault_info_mem_destroy
1098gv11b_mm_is_bar1_supported
1099gv11b_mm_l2_flush
1100gv11b_mm_mmu_fault_pending
1101gv11b_mm_remove_bar2_vm
1102gv11b_mmu_fault_id_to_eng_pbdma_id_and_veid
1103gv11b_perfbuf_disable_locked
1104gv11b_perfbuf_enable_locked
1105gv11b_pg_gr_init
1106gv11b_pg_set_subfeature_mask
1107gv11b_pmu_bootstrap
1108gv11b_pmu_get_irqdest
1109gv11b_pmu_handle_ext_irq
1110gv11b_pmu_setup_elpg
1111gv11b_setup_apertures
1112gv11b_slcg_bus_load_gating_prod
1113gv11b_slcg_ce2_load_gating_prod
1114gv11b_slcg_chiplet_load_gating_prod
1115gv11b_slcg_ctxsw_firmware_load_gating_prod
1116gv11b_slcg_fb_load_gating_prod
1117gv11b_slcg_fifo_load_gating_prod
1118gv11b_slcg_perf_load_gating_prod
1119gv11b_slcg_pmu_load_gating_prod
1120gv11b_slcg_priring_load_gating_prod
1121gv11b_slcg_pwr_csb_load_gating_prod
1122gv11b_slcg_therm_load_gating_prod
1123gv11b_slcg_xbar_load_gating_prod
1124gv11b_update_subctx_header
1125gv11b_userd_gp_get
1126gv11b_userd_gp_put
1127gv11b_userd_pb_get
1128_init
1129init_pmu_setup_hw1
1130init_rppg
1131init_sec2_setup_hw1
1132is_bar0_global_offset_whitelisted_gk20a
1133is_boardobjgrp_pmucmd_id_valid_v0
1134is_boardobjgrp_pmucmd_id_valid_v1
1135__locked_fifo_preempt
1136__locked_fifo_preempt_timeout_rc
1137lsf_gen_wpr_requirements
1138lsfm_add_ucode_img
1139lsfm_discover_ucode_images
1140lsfm_fill_flcn_bl_gen_desc
1141lsfm_fill_static_lsb_hdr_info
1142lsfm_free_nonpmu_ucode_img_res
1143lsfm_free_ucode_img_res
1144lsfm_init_wpr_contents
1145ltc_gk20a_slcg_ltc_load_gating_prod
1146ltc_gm20b_slcg_ltc_load_gating_prod
1147ltc_gp106_slcg_ltc_load_gating_prod
1148ltc_gp10b_slcg_ltc_load_gating_prod
1149ltc_gv11b_slcg_ltc_load_gating_prod
1150mc_gk20a_handle_intr_nonstall
1151mc_gk20a_intr_enable
1152mc_gk20a_intr_nonstall
1153mc_gk20a_intr_nonstall_pause
1154mc_gk20a_intr_nonstall_resume
1155mc_gk20a_intr_stall
1156mc_gk20a_intr_stall_pause
1157mc_gk20a_intr_stall_resume
1158mc_gk20a_intr_unit_config
1159mc_gk20a_is_intr1_pending
1160mc_gk20a_isr_stall
1161mc_gp10b_intr_enable
1162mc_gp10b_intr_nonstall
1163mc_gp10b_intr_nonstall_pause
1164mc_gp10b_intr_nonstall_resume
1165mc_gp10b_intr_stall
1166mc_gp10b_intr_stall_pause
1167mc_gp10b_intr_stall_resume
1168mc_gp10b_intr_unit_config
1169mc_gp10b_is_intr1_pending
1170mc_gp10b_isr_stall
1171mc_gv100_intr_enable
1172mc_gv11b_intr_enable
1173nvgpu_aelpg_init
1174nvgpu_aelpg_init_and_enable
1175nvgpu_alloc
1176nvgpu_alloc_base
1177__nvgpu_alloc_common_init
1178nvgpu_alloc_destroy
1179nvgpu_alloc_end
1180nvgpu_alloc_fixed
1181nvgpu_alloc_initialized
1182nvgpu_alloc_length
1183nvgpu_alloc_release_carveout
1184nvgpu_alloc_reserve_carveout
1185nvgpu_alloc_space
1186__nvgpu_aperture_mask
1187nvgpu_aperture_mask
1188nvgpu_bar1_readl
1189nvgpu_bar1_writel
1190__nvgpu_big_alloc
1191nvgpu_big_free
1192nvgpu_big_pages_possible
1193nvgpu_bios_execute_script
1194nvgpu_bios_get_nvlink_config_data
1195nvgpu_bios_get_perf_table_ptrs
1196nvgpu_bios_parse_rom
1197nvgpu_bios_read_s8
1198nvgpu_bios_read_u16
1199nvgpu_bios_read_u32
1200nvgpu_bios_read_u8
1201nvgpu_bitmap_allocator_init
1202__nvgpu_buddy_allocator_init
1203nvgpu_buddy_allocator_init
1204nvgpu_channel_worker_deinit
1205nvgpu_channel_worker_init
1206nvgpu_check_and_set_context_reservation
1207nvgpu_check_and_set_global_reservation
1208__nvgpu_check_gpu_state
1209nvgpu_clk_arb_cleanup_arbiter
1210nvgpu_clk_arb_commit_request_fd
1211nvgpu_clk_arb_get_arbiter_actual_mhz
1212nvgpu_clk_arb_get_arbiter_clk_domains
1213nvgpu_clk_arb_get_arbiter_clk_f_points
1214nvgpu_clk_arb_get_arbiter_clk_range
1215nvgpu_clk_arb_get_arbiter_effective_mhz
1216nvgpu_clk_arb_get_current_pstate
1217nvgpu_clk_arb_get_session_target_mhz
1218nvgpu_clk_arb_init_arbiter
1219nvgpu_clk_arb_init_session
1220nvgpu_clk_arb_install_event_fd
1221nvgpu_clk_arb_install_request_fd
1222nvgpu_clk_arb_install_session_fd
1223nvgpu_clk_arb_is_valid_domain
1224nvgpu_clk_arb_pstate_change_lock
1225nvgpu_clk_arb_release_session
1226nvgpu_clk_arb_schedule_alarm
1227nvgpu_clk_arb_schedule_vf_table_update
1228nvgpu_clk_arb_send_thermal_alarm
1229nvgpu_clk_arb_set_session_target_mhz
1230nvgpu_cond_broadcast
1231nvgpu_cond_broadcast_interruptible
1232nvgpu_cond_destroy
1233nvgpu_cond_init
1234nvgpu_cond_signal
1235nvgpu_cond_signal_interruptible
1236nvgpu_current_pid
1237nvgpu_current_tid
1238nvgpu_current_time_ms
1239nvgpu_dbg_gpu_get_session_channel
1240nvgpu_dma_alloc
1241nvgpu_dma_alloc_flags
1242nvgpu_dma_alloc_flags_sys
1243nvgpu_dma_alloc_flags_vid
1244nvgpu_dma_alloc_flags_vid_at
1245nvgpu_dma_alloc_map
1246nvgpu_dma_alloc_map_flags
1247nvgpu_dma_alloc_map_flags_sys
1248nvgpu_dma_alloc_map_flags_vid
1249nvgpu_dma_alloc_map_sys
1250nvgpu_dma_alloc_map_vid
1251nvgpu_dma_alloc_sys
1252nvgpu_dma_alloc_vid
1253nvgpu_dma_free
1254nvgpu_dma_unmap_free
1255nvgpu_find_hex_in_string
1256nvgpu_flcn_bootstrap
1257nvgpu_flcn_clear_halt_intr_status
1258nvgpu_flcn_copy_from_dmem
1259nvgpu_flcn_copy_from_imem
1260nvgpu_flcn_copy_to_dmem
1261nvgpu_flcn_copy_to_imem
1262nvgpu_flcn_dump_stats
1263nvgpu_flcn_get_cpu_halted_status
1264nvgpu_flcn_get_idle_status
1265nvgpu_flcn_get_mem_scrubbing_status
1266nvgpu_flcn_mailbox_read
1267nvgpu_flcn_mailbox_write
1268nvgpu_flcn_mem_scrub_wait
1269nvgpu_flcn_print_dmem
1270nvgpu_flcn_print_imem
1271nvgpu_flcn_reset
1272nvgpu_flcn_set_irq
1273nvgpu_flcn_sw_init
1274nvgpu_flcn_wait_for_halt
1275nvgpu_flcn_wait_idle
1276nvgpu_free
1277nvgpu_free_enabled_flags
1278nvgpu_free_fixed
1279nvgpu_free_inst_block
1280nvgpu_get_gpfifo_entry_size
1281nvgpu_get_gp_free_count
1282__nvgpu_get_pte
1283nvgpu_get_timestamps_zipper
1284nvgpu_gmmu_init_page_table
1285nvgpu_gmmu_map
1286nvgpu_gmmu_map_fixed
1287nvgpu_gmmu_unmap
1288nvgpu_gp_free_count
1289nvgpu_hr_timestamp
1290nvgpu_init_enabled_flags
1291nvgpu_init_ltc_support
1292nvgpu_init_mm_ce_context
1293nvgpu_init_mm_support
1294nvgpu_init_pmu_fw_support
1295nvgpu_init_pmu_support
1296nvgpu_init_pramin
1297nvgpu_insert_mapped_buf
1298nvgpu_inst_block_addr
1299nvgpu_io_exists
1300nvgpu_iommuable
1301nvgpu_io_valid_reg
1302nvgpu_is_bpmp_running
1303nvgpu_is_enabled
1304nvgpu_is_error_notifier_set
1305nvgpu_is_hypervisor_mode
1306__nvgpu_kcalloc
1307nvgpu_kernel_restart
1308__nvgpu_kfree
1309nvgpu_kill_task_pg_init
1310__nvgpu_kmalloc
1311nvgpu_kmem_cache_alloc
1312nvgpu_kmem_cache_create
1313nvgpu_kmem_cache_destroy
1314nvgpu_kmem_cache_free
1315nvgpu_kmem_fini
1316nvgpu_kmem_init
1317__nvgpu_kzalloc
1318nvgpu_lockless_allocator_init
1319__nvgpu_log_dbg
1320__nvgpu_log_msg
1321nvgpu_lpwr_disable_pg
1322nvgpu_lpwr_enable_pg
1323nvgpu_lpwr_is_mscg_supported
1324nvgpu_lpwr_is_rppg_supported
1325nvgpu_lpwr_pg_setup
1326nvgpu_lpwr_post_init
1327nvgpu_ltc_alloc_cbc
1328nvgpu_ltc_sync_enabled
1329nvgpu_lwpr_mclk_change
1330nvgpu_mem_begin
1331nvgpu_mem_create_from_mem
1332nvgpu_mem_end
1333nvgpu_mem_get_addr
1334nvgpu_mem_get_phys_addr
1335nvgpu_mem_iommu_translate
1336nvgpu_mem_rd
1337nvgpu_mem_rd32
1338nvgpu_mem_rd_n
1339nvgpu_memset
1340nvgpu_mem_wr
1341nvgpu_mem_wr32
1342nvgpu_mem_wr_n
1343nvgpu_mm_get_available_big_page_sizes
1344nvgpu_mm_get_default_big_page_size
1345nvgpu_mm_suspend
1346nvgpu_msleep
1347nvgpu_mutex_acquire
1348nvgpu_mutex_destroy
1349nvgpu_mutex_init
1350nvgpu_mutex_release
1351nvgpu_mutex_tryacquire
1352nvgpu_nvlink_enumerate
1353nvgpu_nvlink_train
1354nvgpu_os_buf_get_size
1355nvgpu_page_allocator_init
1356__nvgpu_pd_alloc
1357__nvgpu_pd_cache_alloc_direct
1358nvgpu_pd_cache_fini
1359__nvgpu_pd_cache_free_direct
1360nvgpu_pd_cache_init
1361__nvgpu_pd_free
1362nvgpu_platform_is_fpga
1363nvgpu_platform_is_silicon
1364nvgpu_platform_is_simulation
1365nvgpu_pmu_ap_send_command
1366nvgpu_pmu_cmd_post
1367nvgpu_pmu_destroy
1368nvgpu_pmu_disable_elpg
1369nvgpu_pmu_dump_elpg_stats
1370nvgpu_pmu_dump_falcon_stats
1371nvgpu_pmu_enable_elpg
1372nvgpu_pmu_get_load_counters
1373nvgpu_pmu_get_pg_stats
1374nvgpu_pmu_handle_perfmon_event
1375nvgpu_pmu_handle_therm_event
1376nvgpu_pmu_init_bind_fecs
1377nvgpu_pmu_init_perfmon
1378nvgpu_pmu_init_perfmon_rpc
1379nvgpu_pmu_init_powergating
1380nvgpu_pmu_load_norm
1381nvgpu_pmu_load_update
1382nvgpu_pmu_mutex_acquire
1383nvgpu_pmu_mutex_release
1384nvgpu_pmu_perfmon_get_samples_rpc
1385nvgpu_pmu_perfmon_start_sampling
1386nvgpu_pmu_perfmon_start_sampling_rpc
1387nvgpu_pmu_perfmon_stop_sampling
1388nvgpu_pmu_perfmon_stop_sampling_rpc
1389nvgpu_pmu_pg_global_enable
1390nvgpu_pmu_prepare_ns_ucode_blob
1391nvgpu_pmu_process_init_msg
1392nvgpu_pmu_process_message
1393nvgpu_pmu_queue_init
1394nvgpu_pmu_queue_is_empty
1395nvgpu_pmu_reset
1396nvgpu_pmu_reset_load_counters
1397nvgpu_pmu_rpc_execute
1398nvgpu_pmu_seq_init
1399nvgpu_pmu_setup_hw_load_zbc
1400nvgpu_pmu_state_change
1401nvgpu_pmu_super_surface_alloc
1402nvgpu_pmu_surface_describe
1403nvgpu_pmu_surface_free
1404nvgpu_pmu_sysmem_surface_alloc
1405nvgpu_pmu_vidmem_surface_alloc
1406nvgpu_posix_cleanup
1407__nvgpu_posix_ffs
1408__nvgpu_posix_fls
1409nvgpu_posix_probe
1410nvgpu_pramin_access_batched
1411__nvgpu_pte_words
1412nvgpu_raw_spinlock_acquire
1413nvgpu_raw_spinlock_init
1414nvgpu_raw_spinlock_release
1415nvgpu_rbtree_enum_next
1416nvgpu_rbtree_enum_start
1417nvgpu_rbtree_insert
1418nvgpu_rbtree_less_than_search
1419nvgpu_rbtree_range_search
1420nvgpu_rbtree_search
1421nvgpu_rbtree_unlink
1422__nvgpu_readl
1423nvgpu_readl
1424nvgpu_release_firmware
1425nvgpu_release_profiler_reservation
1426nvgpu_remove_mapped_buf
1427nvgpu_request_firmware
1428nvgpu_rwsem_down_read
1429nvgpu_rwsem_down_write
1430nvgpu_rwsem_init
1431nvgpu_rwsem_up_read
1432nvgpu_rwsem_up_write
1433nvgpu_semaphore_alloc
1434nvgpu_semaphore_free_hw_sema
1435nvgpu_semaphore_get
1436nvgpu_semaphore_get_sea
1437nvgpu_semaphore_pool_alloc
1438nvgpu_semaphore_pool_get
1439__nvgpu_semaphore_pool_gpu_va
1440nvgpu_semaphore_pool_map
1441nvgpu_semaphore_pool_put
1442nvgpu_semaphore_pool_unmap
1443nvgpu_semaphore_put
1444nvgpu_semaphore_sea_create
1445nvgpu_semaphore_sea_destroy
1446__nvgpu_set_enabled
1447nvgpu_set_error_notifier
1448nvgpu_set_error_notifier_if_empty
1449nvgpu_set_error_notifier_locked
1450__nvgpu_set_pte
1451nvgpu_sgt_alignment
1452nvgpu_sgt_create_from_mem
1453nvgpu_sgt_free
1454nvgpu_sgt_get_dma
1455nvgpu_sgt_get_gpu_addr
1456nvgpu_sgt_get_length
1457nvgpu_sgt_get_next
1458nvgpu_sgt_get_phys
1459nvgpu_sgt_iommuable
1460nvgpu_spinlock_acquire
1461nvgpu_spinlock_init
1462nvgpu_spinlock_release
1463nvgpu_tegra_fuse_read_gcplex_config_fuse
1464nvgpu_tegra_fuse_read_reserved_calib
1465nvgpu_tegra_fuse_write_access_sw
1466nvgpu_tegra_fuse_write_bypass
1467nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable
1468nvgpu_tegra_fuse_write_opt_gpu_tpc1_disable
1469nvgpu_tegra_get_gpu_speedo_id
1470nvgpu_thread_create
1471nvgpu_thread_is_running
1472nvgpu_thread_should_stop
1473nvgpu_thread_stop
1474__nvgpu_timeout_expired_msg
1475nvgpu_timeout_init
1476nvgpu_timeout_peek_expired
1477nvgpu_udelay
1478nvgpu_usermode_writel
1479nvgpu_usleep_range
1480__nvgpu_vfree
1481__nvgpu_vmalloc
1482__nvgpu_vm_alloc_va
1483nvgpu_vm_area_alloc
1484nvgpu_vm_area_find
1485nvgpu_vm_area_free
1486nvgpu_vm_area_validate_buffer
1487__nvgpu_vm_find_mapped_buf
1488__nvgpu_vm_find_mapped_buf_less_than
1489__nvgpu_vm_find_mapped_buf_range
1490nvgpu_vm_find_mapping
1491__nvgpu_vm_free_va
1492nvgpu_vm_get
1493nvgpu_vm_get_buffers
1494__nvgpu_vm_init
1495nvgpu_vm_init
1496nvgpu_vm_map
1497nvgpu_vm_mapping_batch_finish
1498nvgpu_vm_mapping_batch_finish_locked
1499nvgpu_vm_mapping_batch_start
1500nvgpu_vm_pde_coverage_bit_count
1501nvgpu_vm_put
1502nvgpu_vm_put_buffers
1503nvgpu_vm_unmap
1504__nvgpu_vm_unmap_ref
1505nvgpu_vm_unmap_system
1506nvgpu_volt_rail_get_voltage_gp10x
1507nvgpu_volt_rail_get_voltage_gv10x
1508nvgpu_volt_send_load_cmd_to_pmu_gp10x
1509nvgpu_volt_send_load_cmd_to_pmu_gv10x
1510nvgpu_volt_set_voltage_gp10x
1511nvgpu_volt_set_voltage_gv10x
1512__nvgpu_vzalloc
1513nvgpu_wait_for_deferred_interrupts
1514nvgpu_writel
1515nvgpu_writel_check
1516perf_pmu_vfe_load
1517pmgr_device_sw_setup
1518pmgr_domain_pmu_setup
1519pmgr_domain_sw_setup
1520pmgr_monitor_sw_setup
1521pmgr_pmu_pwr_devices_query_blocking
1522pmgr_policy_sw_setup
1523pmgr_pwr_devices_get_current
1524pmgr_pwr_devices_get_power
1525pmgr_pwr_devices_get_voltage
1526pmgr_send_pmgr_tables_to_pmu
1527pmu_bootstrap
1528pmu_dump_security_fuses_gm20b
1529pmu_dump_security_fuses_gp10b
1530pmu_enable_irq
1531pmu_exec_gen_bl
1532pmu_handle_fecs_boot_acr_msg
1533pmu_ucode_details
1534pmu_wait_for_halt
1535pmu_wait_message_cond
1536prepare_ucode_blob
1537pstate_find
1538pstate_get_clk_set_info
1539reg_op_is_gr_ctx
1540reg_op_is_read
1541sec2_clear_halt_interrupt_status
1542sec2_wait_for_halt
1543set_bit
1544test_and_clear_bit
1545test_and_set_bit
1546test_bit
1547therm_channel_sw_setup
1548therm_configure_therm_alert
1549therm_device_sw_setup
1550therm_domain_pmu_setup
1551therm_domain_sw_setup
1552therm_send_pmgr_tables_to_pmu
1553tsg_gk20a_from_ch
1554vfe_equ_pmu_setup
1555vfe_equ_sw_setup
1556vfe_var_pmu_setup
1557vfe_var_sw_setup
1558vm_aspace_id
1559volt_dev_pmu_setup
1560volt_dev_sw_setup
1561volt_get_voltage
1562volt_policy_pmu_setup
1563volt_policy_sw_setup
1564volt_rail_pmu_setup
1565volt_rail_sw_setup
1566volt_rail_vbios_volt_domain_convert_to_internal
1567volt_rail_volt_dev_register
1568volt_rail_volt_domain_convert_to_idx
1569volt_set_noiseaware_vmin
1570volt_set_voltage
1571__warn
1572xve_available_speeds_gp106
1573xve_disable_aspm_gp106
1574xve_disable_shadow_rom_gp106
1575xve_enable_shadow_rom_gp106
1576xve_get_link_control_status
1577xve_get_speed_gp106
1578xve_reset_gpu_gp106
1579xve_set_speed_gp106
1580xve_xve_readl_gp106
1581xve_xve_writel_gp106
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-07 13:41:21 -0400