gpu: nvgpu: fix gpc_tpc_mask to use max_gpc_count

gpc_tpc_mask uses gpc/tpc IDs directly read from fuse, so it needs to
use max_gpc_count for any possible cases rather not gpc_count.

Bug 2302005

Change-Id: I903ee3e0c10c4b329dd0d76c40d3516dc36ed303
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1790464
Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 10 insertions, 7 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index e40f296e..4dfddf5d 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -3196,10 +3196,10 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
                                         sizeof(u32));
 
         if (gr->gpc_tpc_mask == NULL)
-                gr->gpc_tpc_mask = nvgpu_kzalloc(g, gr->gpc_count *
+                gr->gpc_tpc_mask = nvgpu_kzalloc(g, gr->max_gpc_count *
                                         sizeof(u32));
         else
-                memset(gr->gpc_tpc_mask, 0,  gr->gpc_count *
+                memset(gr->gpc_tpc_mask, 0,  gr->max_gpc_count *
                                         sizeof(u32));
 
         if (gr->gpc_zcb_count == NULL)
@@ -3228,6 +3228,13 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
             !gr->gpc_ppc_count || !gr->gpc_skip_mask)
                 goto clean_up;
 
+        for (gpc_index = 0; gpc_index < gr->max_gpc_count; gpc_index++) {
+                if (g->ops.gr.get_gpc_tpc_mask) {
+                        gr->gpc_tpc_mask[gpc_index] =
+                                g->ops.gr.get_gpc_tpc_mask(g, gpc_index);
+                }
+        }
+
         gr->ppc_count = 0;
         gr->tpc_count = 0;
         gr->zcb_count = 0;
@@ -3243,10 +3250,6 @@ static int gr_gk20a_init_gr_config(struct gk20a *g, struct gr_gk20a *gr)
                         gr_gpc0_fs_gpc_num_available_zculls_v(tmp);
                 gr->zcb_count += gr->gpc_zcb_count[gpc_index];
 
-                if (g->ops.gr.get_gpc_tpc_mask)
-                        gr->gpc_tpc_mask[gpc_index] =
-                                g->ops.gr.get_gpc_tpc_mask(g, gpc_index);
-
                 for (pes_index = 0; pes_index < gr->pe_count_per_gpc; pes_index++) {
                         if (!gr->pes_tpc_count[pes_index]) {
                                 gr->pes_tpc_count[pes_index] =
diff --git a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
index f7de17ad..e87d5822 100644
--- a/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
+++ b/drivers/gpu/nvgpu/os/linux/ioctl_ctrl.c
@@ -515,7 +515,7 @@ static int gk20a_ctrl_get_tpc_masks(struct gk20a *g,
 {
         struct gr_gk20a *gr = &g->gr;
         int err = 0;
-        const u32 gpc_tpc_mask_size = sizeof(u32) * gr->gpc_count;
+        const u32 gpc_tpc_mask_size = sizeof(u32) * gr->max_gpc_count;
 
         if (args->mask_buf_size > 0) {
                 size_t write_size = gpc_tpc_mask_size;