diff options
author | Konsta Holtta <kholtta@nvidia.com> | 2017-06-14 08:04:36 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-06-19 07:35:30 -0400 |
commit | 679ba3ca9b8adc6445be3a8d17d32a5863c14126 (patch) | |
tree | 835f1e98b32bf14d272120afc671c37533555163 /drivers/gpu | |
parent | b454c9c129d20ba94f2841c555310754cbd53d00 (diff) |
gpu: nvgpu: Use timeout retry API in xve
Get rid of manual timeout tracking with jiffies in xve_gp106.c by using
the timeout API instead.
Jira NVGPU-83
Change-Id: Ida45539e05ac4de2a9d747170627c7104f27a544
Signed-off-by: Konsta Holtta <kholtta@nvidia.com>
Reviewed-on: http://git-master/r/1502998
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gp106/xve_gp106.c | 75 |
1 files changed, 24 insertions, 51 deletions
diff --git a/drivers/gpu/nvgpu/gp106/xve_gp106.c b/drivers/gpu/nvgpu/gp106/xve_gp106.c index 4eb96614..bbf86e33 100644 --- a/drivers/gpu/nvgpu/gp106/xve_gp106.c +++ b/drivers/gpu/nvgpu/gp106/xve_gp106.c | |||
@@ -34,29 +34,6 @@ | |||
34 | 34 | ||
35 | #define NV_PCFG 0x88000 | 35 | #define NV_PCFG 0x88000 |
36 | 36 | ||
37 | /** | ||
38 | * Init a timer and place the timeout data in @timeout. | ||
39 | */ | ||
40 | static void init_timeout(u32 timeout_ms, u32 *timeout) | ||
41 | { | ||
42 | *timeout = jiffies + msecs_to_jiffies(timeout_ms); | ||
43 | } | ||
44 | |||
45 | /** | ||
46 | * Returns 1 if the current time is after @timeout i.e: the timer timed | ||
47 | * out. Returns 0 if the timer still has time left. | ||
48 | */ | ||
49 | static int check_timeout(u32 *timeout) | ||
50 | { | ||
51 | unsigned long now = jiffies; | ||
52 | unsigned long timeout_l = (unsigned long)*timeout; | ||
53 | |||
54 | if (time_after(now, timeout_l)) | ||
55 | return 1; | ||
56 | |||
57 | return 0; | ||
58 | } | ||
59 | |||
60 | static void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val) | 37 | static void xve_xve_writel_gp106(struct gk20a *g, u32 reg, u32 val) |
61 | { | 38 | { |
62 | gk20a_writel(g, NV_PCFG + reg, val); | 39 | gk20a_writel(g, NV_PCFG + reg, val); |
@@ -231,7 +208,7 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
231 | u32 dl_mgr, saved_dl_mgr; | 208 | u32 dl_mgr, saved_dl_mgr; |
232 | u32 pl_link_config; | 209 | u32 pl_link_config; |
233 | u32 link_control_status, link_speed_setting, link_width; | 210 | u32 link_control_status, link_speed_setting, link_width; |
234 | u32 timeout; | 211 | struct nvgpu_timeout timeout; |
235 | int attempts = 10, err_status = 0; | 212 | int attempts = 10, err_status = 0; |
236 | 213 | ||
237 | g->ops.xve.get_speed(g, ¤t_link_speed); | 214 | g->ops.xve.get_speed(g, ¤t_link_speed); |
@@ -258,26 +235,23 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
258 | gk20a_writel(g, xp_dl_mgr_r(0), dl_mgr); | 235 | gk20a_writel(g, xp_dl_mgr_r(0), dl_mgr); |
259 | xv_sc_dbg(DL_SAFE_MODE, " Done!"); | 236 | xv_sc_dbg(DL_SAFE_MODE, " Done!"); |
260 | 237 | ||
261 | init_timeout(GPU_XVE_TIMEOUT_MS, &timeout); | 238 | nvgpu_timeout_init(g, &timeout, GPU_XVE_TIMEOUT_MS, |
239 | NVGPU_TIMER_CPU_TIMER); | ||
262 | 240 | ||
263 | xv_sc_dbg(CHECK_LINK, "Checking for link idle..."); | 241 | xv_sc_dbg(CHECK_LINK, "Checking for link idle..."); |
264 | while (1) { | 242 | do { |
265 | pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0)); | 243 | pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0)); |
266 | if ((xp_pl_link_config_ltssm_status_f(pl_link_config) == | 244 | if ((xp_pl_link_config_ltssm_status_f(pl_link_config) == |
267 | xp_pl_link_config_ltssm_status_idle_v()) && | 245 | xp_pl_link_config_ltssm_status_idle_v()) && |
268 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == | 246 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == |
269 | xp_pl_link_config_ltssm_directive_normal_operations_v())) | 247 | xp_pl_link_config_ltssm_directive_normal_operations_v())) |
270 | break; | 248 | break; |
249 | } while (!nvgpu_timeout_expired(&timeout)); | ||
271 | 250 | ||
272 | if (check_timeout(&timeout)) { | 251 | if (nvgpu_timeout_peek_expired(&timeout)) { |
273 | err_status = -ETIMEDOUT; | 252 | err_status = -ETIMEDOUT; |
274 | break; | ||
275 | } | ||
276 | } | ||
277 | |||
278 | if (err_status == -ETIMEDOUT) | ||
279 | /* TODO: debug message. */ | ||
280 | goto done; | 253 | goto done; |
254 | } | ||
281 | 255 | ||
282 | xv_sc_dbg(CHECK_LINK, " Done"); | 256 | xv_sc_dbg(CHECK_LINK, " Done"); |
283 | 257 | ||
@@ -336,21 +310,19 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
336 | 310 | ||
337 | xv_sc_dbg(EXEC_CHANGE, "Running link speed change..."); | 311 | xv_sc_dbg(EXEC_CHANGE, "Running link speed change..."); |
338 | 312 | ||
339 | init_timeout(GPU_XVE_TIMEOUT_MS, &timeout); | 313 | nvgpu_timeout_init(g, &timeout, GPU_XVE_TIMEOUT_MS, |
340 | while (1) { | 314 | NVGPU_TIMER_CPU_TIMER); |
315 | do { | ||
341 | gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config); | 316 | gk20a_writel(g, xp_pl_link_config_r(0), pl_link_config); |
342 | if (pl_link_config == | 317 | if (pl_link_config == |
343 | gk20a_readl(g, xp_pl_link_config_r(0))) | 318 | gk20a_readl(g, xp_pl_link_config_r(0))) |
344 | break; | 319 | break; |
320 | } while (!nvgpu_timeout_expired(&timeout)); | ||
345 | 321 | ||
346 | if (check_timeout(&timeout)) { | 322 | if (nvgpu_timeout_peek_expired(&timeout)) { |
347 | err_status = -ETIMEDOUT; | 323 | err_status = -ETIMEDOUT; |
348 | break; | ||
349 | } | ||
350 | } | ||
351 | |||
352 | if (err_status == -ETIMEDOUT) | ||
353 | goto done; | 324 | goto done; |
325 | } | ||
354 | 326 | ||
355 | xv_sc_dbg(EXEC_CHANGE, " Wrote PL_LINK_CONFIG."); | 327 | xv_sc_dbg(EXEC_CHANGE, " Wrote PL_LINK_CONFIG."); |
356 | 328 | ||
@@ -370,8 +342,9 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
370 | * Read NV_XP_PL_LINK_CONFIG until the link has swapped to | 342 | * Read NV_XP_PL_LINK_CONFIG until the link has swapped to |
371 | * the target speed. | 343 | * the target speed. |
372 | */ | 344 | */ |
373 | init_timeout(GPU_XVE_TIMEOUT_MS, &timeout); | 345 | nvgpu_timeout_init(g, &timeout, GPU_XVE_TIMEOUT_MS, |
374 | while (1) { | 346 | NVGPU_TIMER_CPU_TIMER); |
347 | do { | ||
375 | pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0)); | 348 | pl_link_config = gk20a_readl(g, xp_pl_link_config_r(0)); |
376 | if (pl_link_config != 0xfffffff && | 349 | if (pl_link_config != 0xfffffff && |
377 | (xp_pl_link_config_ltssm_status_f(pl_link_config) == | 350 | (xp_pl_link_config_ltssm_status_f(pl_link_config) == |
@@ -379,13 +352,13 @@ static int __do_xve_set_speed_gp106(struct gk20a *g, u32 next_link_speed) | |||
379 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == | 352 | (xp_pl_link_config_ltssm_directive_f(pl_link_config) == |
380 | xp_pl_link_config_ltssm_directive_normal_operations_v())) | 353 | xp_pl_link_config_ltssm_directive_normal_operations_v())) |
381 | break; | 354 | break; |
355 | } while (!nvgpu_timeout_expired(&timeout)); | ||
382 | 356 | ||
383 | if (check_timeout(&timeout)) { | 357 | if (nvgpu_timeout_peek_expired(&timeout)) { |
384 | err_status = -ETIMEDOUT; | 358 | err_status = -ETIMEDOUT; |
385 | xv_sc_dbg(EXEC_CHANGE, " timeout; pl_link_config = 0x%x", | 359 | xv_sc_dbg(EXEC_CHANGE, " timeout; pl_link_config = 0x%x", |
386 | pl_link_config); | 360 | pl_link_config); |
387 | break; | 361 | break; |
388 | } | ||
389 | } | 362 | } |
390 | 363 | ||
391 | xv_sc_dbg(EXEC_CHANGE, " Change done... Checking status"); | 364 | xv_sc_dbg(EXEC_CHANGE, " Change done... Checking status"); |