diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-02-09 16:58:02 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-09 15:23:29 -0500 |
commit | 679086c42ea58ce3c355e1dd8c17f662f84a2faf (patch) | |
tree | cc8b1870260fc010352f96c12768715331a16ab4 /drivers/gpu | |
parent | 26cd7b3d822b0b759468300777ff6e43cb5f0f7e (diff) |
gpu: nvgpu: gv11b: support debug dump
Added dump for pbdma, engine status, channel status
and ramfc
JIRA GV11B-45
Change-Id: I25442932c61310005fea481455f68ba10c361381
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1302425
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | 93 |
1 files changed, 92 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c index 656c5421..e33b8ee2 100644 --- a/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/fifo_gv11b.c | |||
@@ -15,8 +15,9 @@ | |||
15 | #include <linux/delay.h> | 15 | #include <linux/delay.h> |
16 | #include <linux/types.h> | 16 | #include <linux/types.h> |
17 | 17 | ||
18 | #include "nvgpu/semaphore.h" | ||
19 | |||
18 | #include "gk20a/gk20a.h" | 20 | #include "gk20a/gk20a.h" |
19 | #include "gk20a/fifo_gk20a.h" | ||
20 | 21 | ||
21 | #include "gp10b/fifo_gp10b.h" | 22 | #include "gp10b/fifo_gp10b.h" |
22 | 23 | ||
@@ -223,6 +224,93 @@ static bool gv11b_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid) | |||
223 | return (engine_subid == gmmu_fault_client_type_gpc_v()); | 224 | return (engine_subid == gmmu_fault_client_type_gpc_v()); |
224 | } | 225 | } |
225 | 226 | ||
227 | static void gv11b_dump_channel_status_ramfc(struct gk20a *g, | ||
228 | struct gk20a_debug_output *o, | ||
229 | u32 hw_chid, | ||
230 | struct ch_state *ch_state) | ||
231 | { | ||
232 | u32 channel = gk20a_readl(g, ccsr_channel_r(hw_chid)); | ||
233 | u32 status = ccsr_channel_status_v(channel); | ||
234 | u32 *inst_mem; | ||
235 | struct channel_gk20a *c = g->fifo.channel + hw_chid; | ||
236 | struct nvgpu_semaphore_int *hw_sema = NULL; | ||
237 | |||
238 | if (c->hw_sema) | ||
239 | hw_sema = c->hw_sema; | ||
240 | |||
241 | if (!ch_state) | ||
242 | return; | ||
243 | |||
244 | inst_mem = &ch_state->inst_block[0]; | ||
245 | |||
246 | gk20a_debug_output(o, "%d-%s, pid %d, refs: %d: ", hw_chid, | ||
247 | dev_name(g->dev), | ||
248 | ch_state->pid, | ||
249 | ch_state->refs); | ||
250 | gk20a_debug_output(o, "channel status: %s in use %s %s\n", | ||
251 | ccsr_channel_enable_v(channel) ? "" : "not", | ||
252 | gk20a_decode_ccsr_chan_status(status), | ||
253 | ccsr_channel_busy_v(channel) ? "busy" : "not busy"); | ||
254 | gk20a_debug_output(o, "RAMFC : TOP: %016llx PUT: %016llx GET: %016llx " | ||
255 | "FETCH: %016llx\nHEADER: %08x COUNT: %08x\n" | ||
256 | "SEMAPHORE: addr hi: %08x addr lo: %08x\n" | ||
257 | "payload %08x execute %08x\n", | ||
258 | (u64)inst_mem[ram_fc_pb_top_level_get_w()] + | ||
259 | ((u64)inst_mem[ram_fc_pb_top_level_get_hi_w()] << 32ULL), | ||
260 | (u64)inst_mem[ram_fc_pb_put_w()] + | ||
261 | ((u64)inst_mem[ram_fc_pb_put_hi_w()] << 32ULL), | ||
262 | (u64)inst_mem[ram_fc_pb_get_w()] + | ||
263 | ((u64)inst_mem[ram_fc_pb_get_hi_w()] << 32ULL), | ||
264 | (u64)inst_mem[ram_fc_pb_fetch_w()] + | ||
265 | ((u64)inst_mem[ram_fc_pb_fetch_hi_w()] << 32ULL), | ||
266 | inst_mem[ram_fc_pb_header_w()], | ||
267 | inst_mem[ram_fc_pb_count_w()], | ||
268 | inst_mem[ram_fc_sem_addr_hi_w()], | ||
269 | inst_mem[ram_fc_sem_addr_lo_w()], | ||
270 | inst_mem[ram_fc_sem_payload_lo_w()], | ||
271 | inst_mem[ram_fc_sem_execute_w()]); | ||
272 | if (hw_sema) | ||
273 | gk20a_debug_output(o, "SEMA STATE: value: 0x%08x " | ||
274 | "next_val: 0x%08x addr: 0x%010llx\n", | ||
275 | readl(hw_sema->value), | ||
276 | atomic_read(&hw_sema->next_value), | ||
277 | nvgpu_hw_sema_addr(hw_sema)); | ||
278 | gk20a_debug_output(o, "\n"); | ||
279 | } | ||
280 | |||
281 | static void gv11b_dump_eng_status(struct gk20a *g, | ||
282 | struct gk20a_debug_output *o) | ||
283 | { | ||
284 | u32 i, host_num_engines; | ||
285 | |||
286 | host_num_engines = nvgpu_get_litter_value(g, GPU_LIT_HOST_NUM_ENGINES); | ||
287 | |||
288 | for (i = 0; i < host_num_engines; i++) { | ||
289 | u32 status = gk20a_readl(g, fifo_engine_status_r(i)); | ||
290 | u32 ctx_status = fifo_engine_status_ctx_status_v(status); | ||
291 | |||
292 | gk20a_debug_output(o, "%s eng %d: ", dev_name(g->dev), i); | ||
293 | gk20a_debug_output(o, | ||
294 | "id: %d (%s), next_id: %d (%s), ctx status: %s ", | ||
295 | fifo_engine_status_id_v(status), | ||
296 | fifo_engine_status_id_type_v(status) ? | ||
297 | "tsg" : "channel", | ||
298 | fifo_engine_status_next_id_v(status), | ||
299 | fifo_engine_status_next_id_type_v(status) ? | ||
300 | "tsg" : "channel", | ||
301 | gk20a_decode_pbdma_chan_eng_ctx_status(ctx_status)); | ||
302 | |||
303 | if (fifo_engine_status_eng_reload_v(status)) | ||
304 | gk20a_debug_output(o, "ctx_reload "); | ||
305 | if (fifo_engine_status_faulted_v(status)) | ||
306 | gk20a_debug_output(o, "faulted "); | ||
307 | if (fifo_engine_status_engine_v(status)) | ||
308 | gk20a_debug_output(o, "busy "); | ||
309 | gk20a_debug_output(o, "\n"); | ||
310 | } | ||
311 | gk20a_debug_output(o, "\n"); | ||
312 | } | ||
313 | |||
226 | void gv11b_init_fifo(struct gpu_ops *gops) | 314 | void gv11b_init_fifo(struct gpu_ops *gops) |
227 | { | 315 | { |
228 | gp10b_init_fifo(gops); | 316 | gp10b_init_fifo(gops); |
@@ -242,4 +330,7 @@ void gv11b_init_fifo(struct gpu_ops *gops) | |||
242 | gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; | 330 | gops->fifo.device_info_fault_id = top_device_info_data_fault_id_enum_v; |
243 | gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; | 331 | gops->fifo.is_fault_engine_subid_gpc = gv11b_is_fault_engine_subid_gpc; |
244 | gops->fifo.trigger_mmu_fault = NULL; | 332 | gops->fifo.trigger_mmu_fault = NULL; |
333 | gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; | ||
334 | gops->fifo.dump_eng_status = gv11b_dump_eng_status; | ||
335 | gops->fifo.dump_channel_status_ramfc = gv11b_dump_channel_status_ramfc; | ||
245 | } | 336 | } |