gpu: nvgpu: gv100: fix num_fbpas while adding ctxsw buffer entries

For LIST_nv_pm_fbpa_ctx_regs, we right now call
add_ctxsw_buffer_map_entries_subunits() to add registers corresponding
to all the FBPAs

But while configuring total number of registers, we do not consider
floorswept FBPAs and that causes misalignment in subsequent lists for GV100

Fix this by reading disabled/floorswept FBPAs from fuse and consider only those
FBPAs which are active for GV100

Add new HAL (*add_ctxsw_reg_pm_fbpa) to support this setting and define a
common HAL gr_gk20a_add_ctxsw_reg_pm_fbpa() for all chips except GV100

Define GV100 specific gr_gv100_add_ctxsw_reg_pm_fbpa() with above mentioned
implementation to consider floorsweeping

Bug 1998067

Change-Id: Id560551bb0b8142791c117b6d27864566c90b489
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1676654
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

12 files changed, 81 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index c1824b07..4ab1cd1b 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -450,6 +450,12 @@ struct gpu_ops {
                                         struct gr_gk20a_isr_data *isr_data);
                 int (*handle_semaphore_pending)(struct gk20a *g,
                                         struct gr_gk20a_isr_data *isr_data);
+                int (*add_ctxsw_reg_pm_fbpa)(struct gk20a *g,
+                                struct ctxsw_buf_offset_map_entry *map,
+                                struct aiv_list_gk20a *regs,
+                                u32 *count, u32 *offset,
+                                u32 max_cnt, u32 base,
+                                u32 num_fbpas, u32 stride, u32 mask);
         } gr;
         struct {
                 void (*init_hw)(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 94bfd224..bec33293 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -7495,6 +7495,17 @@ static int add_ctxsw_buffer_map_entries_subunits(
         return 0;
 }
 
+int gr_gk20a_add_ctxsw_reg_pm_fbpa(struct gk20a *g,
+                                struct ctxsw_buf_offset_map_entry *map,
+                                struct aiv_list_gk20a *regs,
+                                u32 *count, u32 *offset,
+                                u32 max_cnt, u32 base,
+                                u32 num_fbpas, u32 stride, u32 mask)
+{
+        return add_ctxsw_buffer_map_entries_subunits(map, regs, count, offset,
+                        max_cnt, base, num_fbpas, stride, mask);
+}
+
 static int add_ctxsw_buffer_map_entries_gpcs(struct gk20a *g,
                                         struct ctxsw_buf_offset_map_entry *map,
                                         u32 *count, u32 *offset, u32 max_cnt)
@@ -7683,7 +7694,7 @@ static int gr_gk20a_create_hwpm_ctxsw_buffer_offset_map(struct gk20a *g)
                 goto cleanup;
 
         /* Add entries from _LIST_nv_pm_fbpa_ctx_regs */
-        if (add_ctxsw_buffer_map_entries_subunits(map,
+        if (g->ops.gr.add_ctxsw_reg_pm_fbpa(g, map,
                                         &g->gr.ctx_vars.ctxsw_regs.pm_fbpa,
                                         &count, &offset,
                                         hwpm_ctxsw_reg_count_max, 0,
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
index 7f89037e..5ac363e1 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h
@@ -811,4 +811,10 @@ u32 gk20a_init_sw_bundle(struct gk20a *g);
 int gr_gk20a_fecs_ctx_image_save(struct channel_gk20a *c, u32 save_type);
 int gk20a_gr_handle_semaphore_pending(struct gk20a *g,
                                 struct gr_gk20a_isr_data *isr_data);
+int gr_gk20a_add_ctxsw_reg_pm_fbpa(struct gk20a *g,
+                                struct ctxsw_buf_offset_map_entry *map,
+                                struct aiv_list_gk20a *regs,
+                                u32 *count, u32 *offset,
+                                u32 max_cnt, u32 base,
+                                u32 num_fbpas, u32 stride, u32 mask);
 #endif /*__GR_GK20A_H__*/
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index dd0a50bc..9de5a4ca 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -314,6 +314,7 @@ static const struct gpu_ops gm20b_ops = {
                 .set_error_notifier = gk20a_gr_set_error_notifier,
                 .handle_notify_pending = gk20a_gr_handle_notify_pending,
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
+                .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
         },
         .fb = {
                 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index af6cf9ed..bab32a92 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -376,6 +376,7 @@ static const struct gpu_ops gp106_ops = {
                 .set_error_notifier = gk20a_gr_set_error_notifier,
                 .handle_notify_pending = gk20a_gr_handle_notify_pending,
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
+                .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
         },
         .fb = {
                 .reset = gp106_fb_reset,
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
index cce1ed4f..843b6ee7 100644
--- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c
@@ -344,6 +344,7 @@ static const struct gpu_ops gp10b_ops = {
                 .set_error_notifier = gk20a_gr_set_error_notifier,
                 .handle_notify_pending = gk20a_gr_handle_notify_pending,
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
+                .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
         },
         .fb = {
                 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.c b/drivers/gpu/nvgpu/gv100/gr_gv100.c
index bf143dbb..3aed7a19 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.c
@@ -34,6 +34,8 @@
 
 #include <nvgpu/hw/gv100/hw_gr_gv100.h>
 #include <nvgpu/hw/gv100/hw_proj_gv100.h>
+#include <nvgpu/hw/gv100/hw_fuse_gv100.h>
+
 
 /*
  *  Estimate performance if the given logical TPC in the given logical GPC were
@@ -329,3 +331,45 @@ u32 gr_gv100_get_patch_slots(struct gk20a *g)
 
         return size;
 }
+
+int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g,
+                                struct ctxsw_buf_offset_map_entry *map,
+                                struct aiv_list_gk20a *regs,
+                                u32 *count, u32 *offset,
+                                u32 max_cnt, u32 base,
+                                u32 num_fbpas, u32 stride, u32 mask)
+{
+        u32 fbpa_id;
+        u32 idx;
+        u32 cnt = *count;
+        u32 off = *offset;
+        u32 active_fbpa_mask;
+
+        if ((cnt + (regs->count * num_fbpas)) > max_cnt)
+                return -EINVAL;
+
+        /*
+         * Read active fbpa mask from fuse
+         * Note that 0:enable and 1:disable in value read from fuse so we've to
+         * flip the bits.
+         * Also set unused bits to zero
+         */
+        active_fbpa_mask = nvgpu_readl(g, fuse_status_opt_fbio_r());
+        active_fbpa_mask = ~active_fbpa_mask;
+        active_fbpa_mask = active_fbpa_mask & ((1 << num_fbpas) - 1);
+
+        for (idx = 0; idx < regs->count; idx++) {
+                for (fbpa_id = 0; fbpa_id < num_fbpas; fbpa_id++) {
+                        if (active_fbpa_mask & BIT(fbpa_id)) {
+                                map[cnt].addr = base +
+                                                (regs->l[idx].addr & mask) +
+                                                (fbpa_id * stride);
+                                map[cnt++].offset = off;
+                                off += 4;
+                        }
+                }
+        }
+        *count = cnt;
+        *offset = off;
+        return 0;
+}
diff --git a/drivers/gpu/nvgpu/gv100/gr_gv100.h b/drivers/gpu/nvgpu/gv100/gr_gv100.h
index 690bba57..e1174686 100644
--- a/drivers/gpu/nvgpu/gv100/gr_gv100.h
+++ b/drivers/gpu/nvgpu/gv100/gr_gv100.h
@@ -33,4 +33,10 @@ void gr_gv100_program_sm_id_numbering(struct gk20a *g,
                                         u32 gpc, u32 tpc, u32 smid);
 int gr_gv100_load_smid_config(struct gk20a *g);
 u32 gr_gv100_get_patch_slots(struct gk20a *g);
+int gr_gv100_add_ctxsw_reg_pm_fbpa(struct gk20a *g,
+                                struct ctxsw_buf_offset_map_entry *map,
+                                struct aiv_list_gk20a *regs,
+                                u32 *count, u32 *offset,
+                                u32 max_cnt, u32 base,
+                                u32 num_fbpas, u32 stride, u32 mask);
 #endif
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c
index 3dbd1e01..08fc7c34 100644
--- a/drivers/gpu/nvgpu/gv100/hal_gv100.c
+++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c
@@ -429,6 +429,7 @@ static const struct gpu_ops gv100_ops = {
                 .set_error_notifier = gk20a_gr_set_error_notifier,
                 .handle_notify_pending = gk20a_gr_handle_notify_pending,
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
+                .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa,
         },
         .fb = {
                 .reset = gv100_fb_reset,
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
index 1fe09827..1edf67d6 100644
--- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
+++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c
@@ -396,6 +396,7 @@ static const struct gpu_ops gv11b_ops = {
                 .set_error_notifier = gk20a_gr_set_error_notifier,
                 .handle_notify_pending = gk20a_gr_handle_notify_pending,
                 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
+                .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
         },
         .fb = {
                 .reset = gv11b_fb_reset,
diff --git a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
index 18eee404..5750fd78 100644
--- a/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
+++ b/drivers/gpu/nvgpu/vgpu/gp10b/vgpu_hal_gp10b.c
@@ -220,6 +220,7 @@ static const struct gpu_ops vgpu_gp10b_ops = {
                         gr_gp10b_init_gfxp_wfi_timeout_count,
                 .get_max_gfxp_wfi_timeout_count =
                         gr_gp10b_get_max_gfxp_wfi_timeout_count,
+                .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
         },
         .fb = {
                 .reset = fb_gk20a_reset,
diff --git a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
index 465b57a5..9588f4bd 100644
--- a/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
+++ b/drivers/gpu/nvgpu/vgpu/gv11b/vgpu_hal_gv11b.c
@@ -256,6 +256,7 @@ static const struct gpu_ops vgpu_gv11b_ops = {
                         gr_gv11b_init_gfxp_wfi_timeout_count,
                 .get_max_gfxp_wfi_timeout_count =
                         gr_gv11b_get_max_gfxp_wfi_timeout_count,
+                .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
         },
         .fb = {
                 .reset = gv11b_fb_reset,