diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-03-19 20:00:09 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-04-19 15:17:34 -0400 |
commit | 5ab3524f915a72021701975c026a1f38eea577e9 (patch) | |
tree | dc8badda976f761e511f23b499338fead46ea6a5 /drivers/gpu | |
parent | 89ffa669b69c7e0007f4a5dc92e9abc8c71ec3c4 (diff) |
Revert "gpu: nvgpu: add hal op for gr set error notifier"
This reverts commit d6c6c6c483478654b34685b9e13ed160bad49a1c.
RM server has moved to gops.fifo.set_error_notifier.
gops.gr.set_error_notifier is not needed anymore.
Jira VQRM-3058
Change-Id: I0fe7f914778ce66701a699aece2b36a5cd8079da
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1679708
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.c | 18 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gr_gk20a.h | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp106/hal_gp106.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gp10b/hal_gp10b.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv100/hal_gv100.c | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/hal_gv11b.c | 1 |
8 files changed, 9 insertions, 18 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index c55ba146..2e7bd4a5 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -446,8 +446,6 @@ struct gpu_ops { | |||
446 | struct nvgpu_gr_ctx *gr_ctx); | 446 | struct nvgpu_gr_ctx *gr_ctx); |
447 | void (*fecs_host_int_enable)(struct gk20a *g); | 447 | void (*fecs_host_int_enable)(struct gk20a *g); |
448 | int (*handle_ssync_hww)(struct gk20a *g); | 448 | int (*handle_ssync_hww)(struct gk20a *g); |
449 | void (*set_error_notifier)(struct gk20a *g, | ||
450 | struct gr_gk20a_isr_data *isr_data, u32 error_notifier); | ||
451 | int (*handle_notify_pending)(struct gk20a *g, | 449 | int (*handle_notify_pending)(struct gk20a *g, |
452 | struct gr_gk20a_isr_data *isr_data); | 450 | struct gr_gk20a_isr_data *isr_data); |
453 | int (*handle_semaphore_pending)(struct gk20a *g, | 451 | int (*handle_semaphore_pending)(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c index 121f264a..ed1f9af9 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c | |||
@@ -5136,7 +5136,7 @@ int gk20a_gr_reset(struct gk20a *g) | |||
5136 | return err; | 5136 | return err; |
5137 | } | 5137 | } |
5138 | 5138 | ||
5139 | void gk20a_gr_set_error_notifier(struct gk20a *g, | 5139 | static void gk20a_gr_set_error_notifier(struct gk20a *g, |
5140 | struct gr_gk20a_isr_data *isr_data, u32 error_notifier) | 5140 | struct gr_gk20a_isr_data *isr_data, u32 error_notifier) |
5141 | { | 5141 | { |
5142 | struct fifo_gk20a *f = &g->fifo; | 5142 | struct fifo_gk20a *f = &g->fifo; |
@@ -5169,7 +5169,7 @@ static int gk20a_gr_handle_semaphore_timeout_pending(struct gk20a *g, | |||
5169 | struct gr_gk20a_isr_data *isr_data) | 5169 | struct gr_gk20a_isr_data *isr_data) |
5170 | { | 5170 | { |
5171 | gk20a_dbg_fn(""); | 5171 | gk20a_dbg_fn(""); |
5172 | g->ops.gr.set_error_notifier(g, isr_data, | 5172 | gk20a_gr_set_error_notifier(g, isr_data, |
5173 | NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); | 5173 | NVGPU_ERR_NOTIFIER_GR_SEMAPHORE_TIMEOUT); |
5174 | nvgpu_err(g, | 5174 | nvgpu_err(g, |
5175 | "gr semaphore timeout"); | 5175 | "gr semaphore timeout"); |
@@ -5180,7 +5180,7 @@ static int gk20a_gr_intr_illegal_notify_pending(struct gk20a *g, | |||
5180 | struct gr_gk20a_isr_data *isr_data) | 5180 | struct gr_gk20a_isr_data *isr_data) |
5181 | { | 5181 | { |
5182 | gk20a_dbg_fn(""); | 5182 | gk20a_dbg_fn(""); |
5183 | g->ops.gr.set_error_notifier(g, isr_data, | 5183 | gk20a_gr_set_error_notifier(g, isr_data, |
5184 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); | 5184 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); |
5185 | /* This is an unrecoverable error, reset is needed */ | 5185 | /* This is an unrecoverable error, reset is needed */ |
5186 | nvgpu_err(g, | 5186 | nvgpu_err(g, |
@@ -5195,7 +5195,7 @@ static int gk20a_gr_handle_illegal_method(struct gk20a *g, | |||
5195 | isr_data->class_num, isr_data->offset, | 5195 | isr_data->class_num, isr_data->offset, |
5196 | isr_data->data_lo); | 5196 | isr_data->data_lo); |
5197 | if (ret) { | 5197 | if (ret) { |
5198 | g->ops.gr.set_error_notifier(g, isr_data, | 5198 | gk20a_gr_set_error_notifier(g, isr_data, |
5199 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); | 5199 | NVGPU_ERR_NOTIFIER_GR_ILLEGAL_NOTIFY); |
5200 | nvgpu_err(g, "invalid method class 0x%08x" | 5200 | nvgpu_err(g, "invalid method class 0x%08x" |
5201 | ", offset 0x%08x address 0x%08x", | 5201 | ", offset 0x%08x address 0x%08x", |
@@ -5208,7 +5208,7 @@ static int gk20a_gr_handle_illegal_class(struct gk20a *g, | |||
5208 | struct gr_gk20a_isr_data *isr_data) | 5208 | struct gr_gk20a_isr_data *isr_data) |
5209 | { | 5209 | { |
5210 | gk20a_dbg_fn(""); | 5210 | gk20a_dbg_fn(""); |
5211 | g->ops.gr.set_error_notifier(g, isr_data, | 5211 | gk20a_gr_set_error_notifier(g, isr_data, |
5212 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 5212 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
5213 | nvgpu_err(g, | 5213 | nvgpu_err(g, |
5214 | "invalid class 0x%08x, offset 0x%08x", | 5214 | "invalid class 0x%08x, offset 0x%08x", |
@@ -5226,7 +5226,7 @@ int gk20a_gr_handle_fecs_error(struct gk20a *g, struct channel_gk20a *ch, | |||
5226 | return 0; | 5226 | return 0; |
5227 | 5227 | ||
5228 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { | 5228 | if (gr_fecs_intr & gr_fecs_host_int_status_umimp_firmware_method_f(1)) { |
5229 | g->ops.gr.set_error_notifier(g, isr_data, | 5229 | gk20a_gr_set_error_notifier(g, isr_data, |
5230 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); | 5230 | NVGPU_ERR_NOTIFIER_FECS_ERR_UNIMP_FIRMWARE_METHOD); |
5231 | nvgpu_err(g, | 5231 | nvgpu_err(g, |
5232 | "firmware method error 0x%08x for offset 0x%04x", | 5232 | "firmware method error 0x%08x for offset 0x%04x", |
@@ -5252,7 +5252,7 @@ static int gk20a_gr_handle_class_error(struct gk20a *g, | |||
5252 | 5252 | ||
5253 | gr_class_error = | 5253 | gr_class_error = |
5254 | gr_class_error_code_v(gk20a_readl(g, gr_class_error_r())); | 5254 | gr_class_error_code_v(gk20a_readl(g, gr_class_error_r())); |
5255 | g->ops.gr.set_error_notifier(g, isr_data, | 5255 | gk20a_gr_set_error_notifier(g, isr_data, |
5256 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 5256 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
5257 | nvgpu_err(g, "class error 0x%08x, offset 0x%08x," | 5257 | nvgpu_err(g, "class error 0x%08x, offset 0x%08x," |
5258 | "sub channel 0x%08x mme generated %d," | 5258 | "sub channel 0x%08x mme generated %d," |
@@ -5281,7 +5281,7 @@ static int gk20a_gr_handle_firmware_method(struct gk20a *g, | |||
5281 | { | 5281 | { |
5282 | gk20a_dbg_fn(""); | 5282 | gk20a_dbg_fn(""); |
5283 | 5283 | ||
5284 | g->ops.gr.set_error_notifier(g, isr_data, | 5284 | gk20a_gr_set_error_notifier(g, isr_data, |
5285 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); | 5285 | NVGPU_ERR_NOTIFIER_GR_ERROR_SW_NOTIFY); |
5286 | nvgpu_err(g, | 5286 | nvgpu_err(g, |
5287 | "firmware method 0x%08x, offset 0x%08x for channel %u", | 5287 | "firmware method 0x%08x, offset 0x%08x for channel %u", |
@@ -6085,7 +6085,7 @@ int gk20a_gr_isr(struct gk20a *g) | |||
6085 | 6085 | ||
6086 | if (need_reset) { | 6086 | if (need_reset) { |
6087 | nvgpu_err(g, "set gr exception notifier"); | 6087 | nvgpu_err(g, "set gr exception notifier"); |
6088 | g->ops.gr.set_error_notifier(g, &isr_data, | 6088 | gk20a_gr_set_error_notifier(g, &isr_data, |
6089 | NVGPU_ERR_NOTIFIER_GR_EXCEPTION); | 6089 | NVGPU_ERR_NOTIFIER_GR_EXCEPTION); |
6090 | } | 6090 | } |
6091 | } | 6091 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h index 02f5e534..79afbf0c 100644 --- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.h | |||
@@ -799,8 +799,6 @@ void gk20a_gr_get_ovr_perf_regs(struct gk20a *g, u32 *num_ovr_perf_regs, | |||
799 | void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, | 799 | void gk20a_gr_init_ctxsw_hdr_data(struct gk20a *g, |
800 | struct nvgpu_mem *mem); | 800 | struct nvgpu_mem *mem); |
801 | u32 gr_gk20a_get_patch_slots(struct gk20a *g); | 801 | u32 gr_gk20a_get_patch_slots(struct gk20a *g); |
802 | void gk20a_gr_set_error_notifier(struct gk20a *g, | ||
803 | struct gr_gk20a_isr_data *isr_data, u32 error_notifier); | ||
804 | int gk20a_gr_handle_notify_pending(struct gk20a *g, | 802 | int gk20a_gr_handle_notify_pending(struct gk20a *g, |
805 | struct gr_gk20a_isr_data *isr_data); | 803 | struct gr_gk20a_isr_data *isr_data); |
806 | int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g, | 804 | int gr_gk20a_commit_global_ctx_buffers(struct gk20a *g, |
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index d6f64bb1..0e236d43 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -315,7 +315,6 @@ static const struct gpu_ops gm20b_ops = { | |||
315 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, | 315 | .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce, |
316 | .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, | 316 | .init_ctxsw_hdr_data = gk20a_gr_init_ctxsw_hdr_data, |
317 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, | 317 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, |
318 | .set_error_notifier = gk20a_gr_set_error_notifier, | ||
319 | .handle_notify_pending = gk20a_gr_handle_notify_pending, | 318 | .handle_notify_pending = gk20a_gr_handle_notify_pending, |
320 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 319 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
321 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 320 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c index eecb0f09..aedd6d14 100644 --- a/drivers/gpu/nvgpu/gp106/hal_gp106.c +++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c | |||
@@ -378,7 +378,6 @@ static const struct gpu_ops gp106_ops = { | |||
378 | .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode, | 378 | .set_ctxsw_preemption_mode = gr_gp106_set_ctxsw_preemption_mode, |
379 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, | 379 | .load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode, |
380 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, | 380 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, |
381 | .set_error_notifier = gk20a_gr_set_error_notifier, | ||
382 | .handle_notify_pending = gk20a_gr_handle_notify_pending, | 381 | .handle_notify_pending = gk20a_gr_handle_notify_pending, |
383 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 382 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
384 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 383 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
diff --git a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c index d70d6ac0..30e04717 100644 --- a/drivers/gpu/nvgpu/gp10b/hal_gp10b.c +++ b/drivers/gpu/nvgpu/gp10b/hal_gp10b.c | |||
@@ -346,7 +346,6 @@ static const struct gpu_ops gp10b_ops = { | |||
346 | gr_gp10b_get_max_gfxp_wfi_timeout_count, | 346 | gr_gp10b_get_max_gfxp_wfi_timeout_count, |
347 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, | 347 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, |
348 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, | 348 | .fecs_host_int_enable = gr_gk20a_fecs_host_int_enable, |
349 | .set_error_notifier = gk20a_gr_set_error_notifier, | ||
350 | .handle_notify_pending = gk20a_gr_handle_notify_pending, | 349 | .handle_notify_pending = gk20a_gr_handle_notify_pending, |
351 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 350 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
352 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 351 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |
diff --git a/drivers/gpu/nvgpu/gv100/hal_gv100.c b/drivers/gpu/nvgpu/gv100/hal_gv100.c index fc303e70..bf687dbf 100644 --- a/drivers/gpu/nvgpu/gv100/hal_gv100.c +++ b/drivers/gpu/nvgpu/gv100/hal_gv100.c | |||
@@ -425,7 +425,6 @@ static const struct gpu_ops gv100_ops = { | |||
425 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, | 425 | .decode_egpc_addr = gv11b_gr_decode_egpc_addr, |
426 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | 426 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, |
427 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, | 427 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, |
428 | .set_error_notifier = gk20a_gr_set_error_notifier, | ||
429 | .handle_notify_pending = gk20a_gr_handle_notify_pending, | 428 | .handle_notify_pending = gk20a_gr_handle_notify_pending, |
430 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 429 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
431 | .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa, | 430 | .add_ctxsw_reg_pm_fbpa = gr_gv100_add_ctxsw_reg_pm_fbpa, |
diff --git a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c index 49e83c4c..6aef49d7 100644 --- a/drivers/gpu/nvgpu/gv11b/hal_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/hal_gv11b.c | |||
@@ -398,7 +398,6 @@ static const struct gpu_ops gv11b_ops = { | |||
398 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, | 398 | .dump_ctxsw_stats = gr_gp10b_dump_ctxsw_stats, |
399 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, | 399 | .fecs_host_int_enable = gr_gv11b_fecs_host_int_enable, |
400 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, | 400 | .handle_ssync_hww = gr_gv11b_handle_ssync_hww, |
401 | .set_error_notifier = gk20a_gr_set_error_notifier, | ||
402 | .handle_notify_pending = gk20a_gr_handle_notify_pending, | 401 | .handle_notify_pending = gk20a_gr_handle_notify_pending, |
403 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, | 402 | .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, |
404 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, | 403 | .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, |