diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-12-08 04:20:38 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-12-10 23:41:31 -0500 |
commit | 5463b04f509c46131a729b62f0c0102fb7830b56 (patch) | |
tree | 7f9c176db262acfee4cc2ea0de8fd8f1e1d9b8d0 /drivers/gpu | |
parent | fa1b18c171aba0f8bb674ccc8c60ae81213a16f6 (diff) |
gpu: nvgpu: fix gpc_tpc_mask setting for gv11b
Pre-gv11b we only had 2 TPCs in a GPC. But on gv11b we have 4 TPCs in a GPC.
Hence update gr_gv11b_set_gpc_tpc_mask() as per new configuration and allow
setting bits based on number of TPCs
Bug 2031635
Change-Id: I44f5f6ce5f3e2501c229c9fcda36fb330ebf8bd0
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1614044
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gv11b/gr_gv11b.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c index 28812792..033d83d5 100644 --- a/drivers/gpu/nvgpu/gv11b/gr_gv11b.c +++ b/drivers/gpu/nvgpu/gv11b/gr_gv11b.c | |||
@@ -1683,15 +1683,29 @@ void gr_gv11b_commit_global_attrib_cb(struct gk20a *g, | |||
1683 | 1683 | ||
1684 | void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) | 1684 | void gr_gv11b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) |
1685 | { | 1685 | { |
1686 | u32 tpc_count_mask; | ||
1687 | u32 fuse_val; | ||
1688 | |||
1689 | if (!g->gr.gpc_tpc_mask[gpc_index]) | ||
1690 | return; | ||
1691 | |||
1692 | /* | ||
1693 | * For s/w value g->gr.gpc_tpc_mask[gpc_index], bit value 1 indicates | ||
1694 | * corresponding TPC is enabled. But for h/w fuse register, bit value 1 | ||
1695 | * indicates corresponding TPC is disabled. | ||
1696 | * So we need to flip the bits and ensure we don't write to bits greater | ||
1697 | * than TPC count | ||
1698 | */ | ||
1699 | tpc_count_mask = (1 << gr_gk20a_get_tpc_count(&g->gr, gpc_index)) - 1; | ||
1700 | |||
1701 | fuse_val = g->gr.gpc_tpc_mask[gpc_index]; | ||
1702 | fuse_val = ~fuse_val; | ||
1703 | fuse_val = fuse_val & tpc_count_mask; | ||
1704 | |||
1686 | nvgpu_tegra_fuse_write_bypass(g, 0x1); | 1705 | nvgpu_tegra_fuse_write_bypass(g, 0x1); |
1687 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); | 1706 | nvgpu_tegra_fuse_write_access_sw(g, 0x0); |
1688 | 1707 | ||
1689 | if (g->gr.gpc_tpc_mask[gpc_index] == 0x1) | 1708 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, fuse_val); |
1690 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x2); | ||
1691 | else if (g->gr.gpc_tpc_mask[gpc_index] == 0x2) | ||
1692 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x1); | ||
1693 | else | ||
1694 | nvgpu_tegra_fuse_write_opt_gpu_tpc0_disable(g, 0x0); | ||
1695 | } | 1709 | } |
1696 | 1710 | ||
1697 | void gr_gv11b_get_access_map(struct gk20a *g, | 1711 | void gr_gv11b_get_access_map(struct gk20a *g, |