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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-02-09 11:17:47 -0500
committermobile promotions <svcmobile_promotions@nvidia.com>2017-02-17 16:46:32 -0500
commit53465def649b813987ca0d4a7ced744305204b82 (patch)
treecdff16681cb0442de3b1a8bd151b2a38c0bc5311 /drivers/gpu
parent29a79e6b80c6a0da489d8b0a470c86e2fec9c355 (diff)
gpu: nvgpu: Generalize BIOS code
Most of BIOS parsing code is not specific to any particular GPU. Move most of the code to generic files, and leave only chip specific parts dealing with microcontroller boot into chip specific files. As most of the parsing is generic, they do not need to be called via HALs so remove the HALs and change the calls into direct function calls. All definitions meant to be used outside BIOS code itself are now in <nvgpu/bios.h> Change-Id: Id48e94c74511d6e95645e90e5bba5c12ef8da45d Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1302222 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu')
-rw-r--r--drivers/gpu/nvgpu/Makefile.nvgpu2
-rw-r--r--drivers/gpu/nvgpu/clk/clk_domain.c9
-rw-r--r--drivers/gpu/nvgpu/clk/clk_fll.c9
-rw-r--r--drivers/gpu/nvgpu/clk/clk_freq_controller.c19
-rw-r--r--drivers/gpu/nvgpu/clk/clk_mclk.c21
-rw-r--r--drivers/gpu/nvgpu/clk/clk_prog.c10
-rw-r--r--drivers/gpu/nvgpu/clk/clk_vf_point.c2
-rw-r--r--drivers/gpu/nvgpu/clk/clk_vin.c10
-rw-r--r--drivers/gpu/nvgpu/common/vbios/bios.c748
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.c4
-rw-r--r--drivers/gpu/nvgpu/gk20a/gk20a.h10
-rw-r--r--drivers/gpu/nvgpu/gm206/bios_gm206.c635
-rw-r--r--drivers/gpu/nvgpu/gm206/bios_gm206.h56
-rw-r--r--drivers/gpu/nvgpu/gm206/hal_gm206.c2
-rw-r--r--drivers/gpu/nvgpu/gp106/bios_gp106.c123
-rw-r--r--drivers/gpu/nvgpu/gp106/bios_gp106.h31
-rw-r--r--drivers/gpu/nvgpu/gp106/hal_gp106.c4
-rw-r--r--drivers/gpu/nvgpu/include/nvgpu/bios.h (renamed from drivers/gpu/nvgpu/include/bios.h)66
-rw-r--r--drivers/gpu/nvgpu/lpwr/lpwr.c36
-rw-r--r--drivers/gpu/nvgpu/lpwr/rppg.c2
-rw-r--r--drivers/gpu/nvgpu/perf/vfe_equ.c9
-rw-r--r--drivers/gpu/nvgpu/perf/vfe_var.c18
-rw-r--r--drivers/gpu/nvgpu/pmgr/pmgrpmu.c1
-rw-r--r--drivers/gpu/nvgpu/pmgr/pwrdev.c8
-rw-r--r--drivers/gpu/nvgpu/pmgr/pwrmonitor.c8
-rw-r--r--drivers/gpu/nvgpu/pmgr/pwrpolicy.c8
-rw-r--r--drivers/gpu/nvgpu/pstate/pstate.c11
-rw-r--r--drivers/gpu/nvgpu/therm/thrmchannel.c8
-rw-r--r--drivers/gpu/nvgpu/therm/thrmdev.c8
-rw-r--r--drivers/gpu/nvgpu/therm/thrmpmu.c1
-rw-r--r--drivers/gpu/nvgpu/volt/volt_dev.c15
-rw-r--r--drivers/gpu/nvgpu/volt/volt_pmu.c2
-rw-r--r--drivers/gpu/nvgpu/volt/volt_policy.c18
-rw-r--r--drivers/gpu/nvgpu/volt/volt_rail.c16
34 files changed, 911 insertions, 1019 deletions
diff --git a/drivers/gpu/nvgpu/Makefile.nvgpu b/drivers/gpu/nvgpu/Makefile.nvgpu
index 4daf5adb..2b8614c3 100644
--- a/drivers/gpu/nvgpu/Makefile.nvgpu
+++ b/drivers/gpu/nvgpu/Makefile.nvgpu
@@ -33,6 +33,7 @@ nvgpu-y := \
33 common/mm/lockless_allocator.o \ 33 common/mm/lockless_allocator.o \
34 common/nvgpu_common.o \ 34 common/nvgpu_common.o \
35 common/semaphore.o \ 35 common/semaphore.o \
36 common/vbios/bios.o \
36 gk20a/gk20a.o \ 37 gk20a/gk20a.o \
37 gk20a/sched_gk20a.o \ 38 gk20a/sched_gk20a.o \
38 gk20a/as_gk20a.o \ 39 gk20a/as_gk20a.o \
@@ -160,7 +161,6 @@ nvgpu-y += \
160 gp106/fifo_gp106.o \ 161 gp106/fifo_gp106.o \
161 gp106/ltc_gp106.o \ 162 gp106/ltc_gp106.o \
162 gp106/fb_gp106.o \ 163 gp106/fb_gp106.o \
163 gp106/bios_gp106.o \
164 gp106/regops_gp106.o \ 164 gp106/regops_gp106.o \
165 clk/clk_mclk.o \ 165 clk/clk_mclk.o \
166 pstate/pstate.o \ 166 pstate/pstate.o \
diff --git a/drivers/gpu/nvgpu/clk/clk_domain.c b/drivers/gpu/nvgpu/clk/clk_domain.c
index b53d3708..2a614f55 100644
--- a/drivers/gpu/nvgpu/clk/clk_domain.c
+++ b/drivers/gpu/nvgpu/clk/clk_domain.c
@@ -11,14 +11,14 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "clk.h" 17#include "clk.h"
16#include "clk_fll.h" 18#include "clk_fll.h"
17#include "clk_domain.h" 19#include "clk_domain.h"
18#include "include/bios.h"
19#include "boardobj/boardobjgrp.h" 20#include "boardobj/boardobjgrp.h"
20#include "boardobj/boardobjgrp_e32.h" 21#include "boardobj/boardobjgrp_e32.h"
21#include "gm206/bios_gm206.h"
22#include "ctrl/ctrlclk.h" 22#include "ctrl/ctrlclk.h"
23#include "ctrl/ctrlvolt.h" 23#include "ctrl/ctrlvolt.h"
24#include "gk20a/pmu_gk20a.h" 24#include "gk20a/pmu_gk20a.h"
@@ -261,10 +261,7 @@ static u32 devinit_get_clocks_table(struct gk20a *g,
261 261
262 gk20a_dbg_info(""); 262 gk20a_dbg_info("");
263 263
264 if (!g->ops.bios.get_perf_table_ptrs) 264 clocks_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
265 return -EINVAL;
266
267 clocks_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
268 g->bios.clock_token, CLOCKS_TABLE); 265 g->bios.clock_token, CLOCKS_TABLE);
269 if (clocks_table_ptr == NULL) { 266 if (clocks_table_ptr == NULL) {
270 status = -EINVAL; 267 status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/clk/clk_fll.c b/drivers/gpu/nvgpu/clk/clk_fll.c
index 91cd0e20..7694e720 100644
--- a/drivers/gpu/nvgpu/clk/clk_fll.c
+++ b/drivers/gpu/nvgpu/clk/clk_fll.c
@@ -11,13 +11,13 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "clk.h" 17#include "clk.h"
16#include "clk_fll.h" 18#include "clk_fll.h"
17#include "include/bios.h"
18#include "boardobj/boardobjgrp.h" 19#include "boardobj/boardobjgrp.h"
19#include "boardobj/boardobjgrp_e32.h" 20#include "boardobj/boardobjgrp_e32.h"
20#include "gm206/bios_gm206.h"
21#include "ctrl/ctrlclk.h" 21#include "ctrl/ctrlclk.h"
22#include "ctrl/ctrlvolt.h" 22#include "ctrl/ctrlvolt.h"
23#include "gk20a/pmu_gk20a.h" 23#include "gk20a/pmu_gk20a.h"
@@ -234,10 +234,7 @@ static u32 devinit_get_fll_device_table(struct gk20a *g,
234 234
235 gk20a_dbg_info(""); 235 gk20a_dbg_info("");
236 236
237 if (!g->ops.bios.get_perf_table_ptrs) 237 fll_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
238 return -EINVAL;
239
240 fll_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
241 g->bios.clock_token, FLL_TABLE); 238 g->bios.clock_token, FLL_TABLE);
242 if (fll_table_ptr == NULL) { 239 if (fll_table_ptr == NULL) {
243 status = -1; 240 status = -1;
diff --git a/drivers/gpu/nvgpu/clk/clk_freq_controller.c b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
index 6fa2db5a..4b47d978 100644
--- a/drivers/gpu/nvgpu/clk/clk_freq_controller.c
+++ b/drivers/gpu/nvgpu/clk/clk_freq_controller.c
@@ -11,15 +11,15 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "clk.h" 17#include "clk.h"
16#include "clk_fll.h" 18#include "clk_fll.h"
17#include "clk_domain.h" 19#include "clk_domain.h"
18#include "clk_freq_controller.h" 20#include "clk_freq_controller.h"
19#include "include/bios.h"
20#include "boardobj/boardobjgrp.h" 21#include "boardobj/boardobjgrp.h"
21#include "boardobj/boardobjgrp_e32.h" 22#include "boardobj/boardobjgrp_e32.h"
22#include "gm206/bios_gm206.h"
23#include "ctrl/ctrlclk.h" 23#include "ctrl/ctrlclk.h"
24#include "ctrl/ctrlvolt.h" 24#include "ctrl/ctrlvolt.h"
25#include "gk20a/pmu_gk20a.h" 25#include "gk20a/pmu_gk20a.h"
@@ -185,16 +185,11 @@ static u32 clk_get_freq_controller_table(struct gk20a *g,
185 }; 185 };
186 } freq_controller_data; 186 } freq_controller_data;
187 187
188 if (g->ops.bios.get_perf_table_ptrs) { 188 pfreq_controller_table_ptr =
189 pfreq_controller_table_ptr = 189 (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
190 (u8 *)g->ops.bios.get_perf_table_ptrs(g, 190 g->bios.clock_token,
191 g->bios.clock_token, 191 FREQUENCY_CONTROLLER_TABLE);
192 FREQUENCY_CONTROLLER_TABLE); 192 if (pfreq_controller_table_ptr == NULL) {
193 if (pfreq_controller_table_ptr == NULL) {
194 status = -EINVAL;
195 goto done;
196 }
197 } else {
198 status = -EINVAL; 193 status = -EINVAL;
199 goto done; 194 goto done;
200 } 195 }
diff --git a/drivers/gpu/nvgpu/clk/clk_mclk.c b/drivers/gpu/nvgpu/clk/clk_mclk.c
index 479fbb0e..815f55ba 100644
--- a/drivers/gpu/nvgpu/clk/clk_mclk.c
+++ b/drivers/gpu/nvgpu/clk/clk_mclk.c
@@ -13,12 +13,10 @@
13 13
14#include <linux/delay.h> 14#include <linux/delay.h>
15 15
16#include <nvgpu/bios.h>
17
16#include "gk20a/gk20a.h" 18#include "gk20a/gk20a.h"
17#include "gk20a/pmu_gk20a.h" 19#include "gk20a/pmu_gk20a.h"
18#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
19#include "gm206/bios_gm206.h"
20
21#include "include/bios.h"
22 20
23#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h> 21#include <nvgpu/hw/gk20a/hw_pwr_gk20a.h>
24#include <nvgpu/hw/gp106/hw_fb_gp106.h> 22#include <nvgpu/hw/gp106/hw_fb_gp106.h>
@@ -2022,12 +2020,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
2022 2020
2023 gk20a_dbg_info(""); 2021 gk20a_dbg_info("");
2024 2022
2025 if (!(g->ops.bios.get_perf_table_ptrs && 2023 mem_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
2026 g->ops.bios.execute_script)) {
2027 goto done;
2028 }
2029
2030 mem_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
2031 g->bios.perf_token, 2024 g->bios.perf_token,
2032 MEMORY_CLOCK_TABLE); 2025 MEMORY_CLOCK_TABLE);
2033 if (mem_table_ptr == NULL) { 2026 if (mem_table_ptr == NULL) {
@@ -2067,7 +2060,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
2067 script_index = BIOS_GET_FIELD(memclock_base_entry.flags1, 2060 script_index = BIOS_GET_FIELD(memclock_base_entry.flags1,
2068 VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX); 2061 VBIOS_MEMORY_CLOCK_BASE_ENTRY_11_FLAGS1_SCRIPT_INDEX);
2069 2062
2070 script_ptr = gm206_bios_read_u32(g, 2063 script_ptr = nvgpu_bios_read_u32(g,
2071 memclock_table_header.script_list_ptr + 2064 memclock_table_header.script_list_ptr +
2072 script_index * sizeof(u32)); 2065 script_index * sizeof(u32));
2073 2066
@@ -2107,7 +2100,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
2107 fb_fbpa_fbio_delay_priv_m(), 2100 fb_fbpa_fbio_delay_priv_m(),
2108 fb_fbpa_fbio_delay_priv_f(shadow_idx))); 2101 fb_fbpa_fbio_delay_priv_f(shadow_idx)));
2109 2102
2110 status = g->ops.bios.execute_script(g, script_ptr); 2103 status = nvgpu_bios_execute_script(g, script_ptr);
2111 if (status < 0) { 2104 if (status < 0) {
2112 gk20a_writel(g, fb_fbpa_fbio_delay_r(), 2105 gk20a_writel(g, fb_fbpa_fbio_delay_r(),
2113 old_fbio_delay); 2106 old_fbio_delay);
@@ -2121,7 +2114,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
2121 cmd_script_index = BIOS_GET_FIELD(memclock_base_entry.flags2, 2114 cmd_script_index = BIOS_GET_FIELD(memclock_base_entry.flags2,
2122 VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX); 2115 VBIOS_MEMORY_CLOCK_BASE_ENTRY_12_FLAGS2_CMD_SCRIPT_INDEX);
2123 2116
2124 cmd_script_ptr = gm206_bios_read_u32(g, 2117 cmd_script_ptr = nvgpu_bios_read_u32(g,
2125 memclock_table_header.cmd_script_list_ptr + 2118 memclock_table_header.cmd_script_list_ptr +
2126 cmd_script_index * sizeof(u32)); 2119 cmd_script_index * sizeof(u32));
2127 2120
@@ -2159,7 +2152,7 @@ static int mclk_get_memclk_table(struct gk20a *g)
2159 fb_fbpa_fbio_cmd_delay_cmd_priv_f( 2152 fb_fbpa_fbio_cmd_delay_cmd_priv_f(
2160 cmd_idx))); 2153 cmd_idx)));
2161 2154
2162 status = g->ops.bios.execute_script(g, cmd_script_ptr); 2155 status = nvgpu_bios_execute_script(g, cmd_script_ptr);
2163 if (status < 0) { 2156 if (status < 0) {
2164 gk20a_writel(g, fb_fbpa_fbio_cmd_delay_r(), 2157 gk20a_writel(g, fb_fbpa_fbio_cmd_delay_r(),
2165 old_fbio_cmd_delay); 2158 old_fbio_cmd_delay);
diff --git a/drivers/gpu/nvgpu/clk/clk_prog.c b/drivers/gpu/nvgpu/clk/clk_prog.c
index 38654b66..b4f6a464 100644
--- a/drivers/gpu/nvgpu/clk/clk_prog.c
+++ b/drivers/gpu/nvgpu/clk/clk_prog.c
@@ -11,11 +11,12 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "clk.h" 17#include "clk.h"
16#include "clk_prog.h" 18#include "clk_prog.h"
17#include "clk_vf_point.h" 19#include "clk_vf_point.h"
18#include "include/bios.h"
19#include "boardobj/boardobjgrp.h" 20#include "boardobj/boardobjgrp.h"
20#include "boardobj/boardobjgrp_e32.h" 21#include "boardobj/boardobjgrp_e32.h"
21#include "gm206/bios_gm206.h" 22#include "gm206/bios_gm206.h"
@@ -180,12 +181,7 @@ static u32 devinit_get_clk_prog_table(struct gk20a *g,
180 181
181 gk20a_dbg_info(""); 182 gk20a_dbg_info("");
182 183
183 if (!g->ops.bios.get_perf_table_ptrs) { 184 clkprogs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
184 status = -EINVAL;
185 goto done;
186 }
187
188 clkprogs_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
189 g->bios.clock_token, CLOCK_PROGRAMMING_TABLE); 185 g->bios.clock_token, CLOCK_PROGRAMMING_TABLE);
190 if (clkprogs_tbl_ptr == NULL) { 186 if (clkprogs_tbl_ptr == NULL) {
191 status = -EINVAL; 187 status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/clk/clk_vf_point.c b/drivers/gpu/nvgpu/clk/clk_vf_point.c
index 58eeb6c2..f4019f9d 100644
--- a/drivers/gpu/nvgpu/clk/clk_vf_point.c
+++ b/drivers/gpu/nvgpu/clk/clk_vf_point.c
@@ -14,10 +14,8 @@
14#include "gk20a/gk20a.h" 14#include "gk20a/gk20a.h"
15#include "clk.h" 15#include "clk.h"
16#include "clk_vf_point.h" 16#include "clk_vf_point.h"
17#include "include/bios.h"
18#include "boardobj/boardobjgrp.h" 17#include "boardobj/boardobjgrp.h"
19#include "boardobj/boardobjgrp_e32.h" 18#include "boardobj/boardobjgrp_e32.h"
20#include "gm206/bios_gm206.h"
21#include "ctrl/ctrlclk.h" 19#include "ctrl/ctrlclk.h"
22#include "ctrl/ctrlvolt.h" 20#include "ctrl/ctrlvolt.h"
23#include "gk20a/pmu_gk20a.h" 21#include "gk20a/pmu_gk20a.h"
diff --git a/drivers/gpu/nvgpu/clk/clk_vin.c b/drivers/gpu/nvgpu/clk/clk_vin.c
index 13358335..af388671 100644
--- a/drivers/gpu/nvgpu/clk/clk_vin.c
+++ b/drivers/gpu/nvgpu/clk/clk_vin.c
@@ -11,9 +11,9 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include "gk20a/gk20a.h" 14#include <nvgpu/bios.h>
15 15
16#include "include/bios.h" 16#include "gk20a/gk20a.h"
17 17
18#include "boardobj/boardobjgrp.h" 18#include "boardobj/boardobjgrp.h"
19#include "boardobj/boardobjgrp_e32.h" 19#include "boardobj/boardobjgrp_e32.h"
@@ -28,7 +28,6 @@
28#include "clk.h" 28#include "clk.h"
29#include "clk_vin.h" 29#include "clk_vin.h"
30 30
31
32#include <nvgpu/hw/gp106/hw_fuse_gp106.h> 31#include <nvgpu/hw/gp106/hw_fuse_gp106.h>
33 32
34static u32 devinit_get_vin_device_table(struct gk20a *g, 33static u32 devinit_get_vin_device_table(struct gk20a *g,
@@ -349,10 +348,7 @@ static u32 devinit_get_vin_device_table(struct gk20a *g,
349 348
350 gk20a_dbg_info(""); 349 gk20a_dbg_info("");
351 350
352 if (!g->ops.bios.get_perf_table_ptrs) 351 vin_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
353 return -EINVAL;
354
355 vin_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
356 g->bios.clock_token, VIN_TABLE); 352 g->bios.clock_token, VIN_TABLE);
357 if (vin_table_ptr == NULL) { 353 if (vin_table_ptr == NULL) {
358 status = -1; 354 status = -1;
diff --git a/drivers/gpu/nvgpu/common/vbios/bios.c b/drivers/gpu/nvgpu/common/vbios/bios.c
new file mode 100644
index 00000000..c31f9a29
--- /dev/null
+++ b/drivers/gpu/nvgpu/common/vbios/bios.c
@@ -0,0 +1,748 @@
1/*
2 * Copyright (c) 2015-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include <nvgpu/bios.h>
15#include <nvgpu/hw/gp106/hw_gc6_gp106.h>
16
17#include "gk20a/gk20a.h"
18
19#define BIT_HEADER_ID 0xb8ff
20#define BIT_HEADER_SIGNATURE 0x00544942
21#define PCI_EXP_ROM_SIG 0xaa55
22#define PCI_EXP_ROM_SIG_NV 0x4e56
23
24#define INIT_DONE 0x71
25#define INIT_RESUME 0x72
26#define INIT_CONDITION 0x75
27#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
28
29struct condition_entry {
30 u32 cond_addr;
31 u32 cond_mask;
32 u32 cond_compare;
33} __packed;
34
35static u16 nvgpu_bios_rdu16(struct gk20a *g, int offset)
36{
37 u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset];
38 return val;
39}
40
41static u32 nvgpu_bios_rdu32(struct gk20a *g, int offset)
42{
43 u32 val = (g->bios.data[offset+3] << 24) +
44 (g->bios.data[offset+2] << 16) +
45 (g->bios.data[offset+1] << 8) +
46 g->bios.data[offset];
47 return val;
48}
49
50struct bit {
51 u16 id;
52 u32 signature;
53 u16 bcd_version;
54 u8 header_size;
55 u8 token_size;
56 u8 token_entries;
57 u8 header_checksum;
58} __packed;
59
60#define TOKEN_ID_BIOSDATA 0x42
61#define TOKEN_ID_NVINIT_PTRS 0x49
62#define TOKEN_ID_FALCON_DATA 0x70
63#define TOKEN_ID_PERF_PTRS 0x50
64#define TOKEN_ID_CLOCK_PTRS 0x43
65#define TOKEN_ID_VIRT_PTRS 0x56
66#define TOKEN_ID_MEMORY_PTRS 0x4D
67
68
69union memory_ptrs {
70 struct {
71 u8 rsvd0[2];
72 u8 mem_strap_data_count;
73 u16 mem_strap_xlat_tbl_ptr;
74 u8 rsvd1[8];
75 } v1 __packed;
76 struct {
77 u8 mem_strap_data_count;
78 u16 mem_strap_xlat_tbl_ptr;
79 u8 rsvd[14];
80 } v2 __packed;
81};
82
83struct biosdata {
84 u32 version;
85 u8 oem_version;
86 u8 checksum;
87 u16 int15callbackspost;
88 u16 int16callbackssystem;
89 u16 boardid;
90 u16 framecount;
91 u8 biosmoddate[8];
92} __packed;
93
94struct nvinit_ptrs {
95 u16 initscript_table_ptr;
96 u16 macro_index_table_ptr;
97 u16 macro_table_ptr;
98 u16 condition_table_ptr;
99 u16 io_condition_table_ptr;
100 u16 io_flag_condition_table_ptr;
101 u16 init_function_table_ptr;
102 u16 vbios_private_table_ptr;
103 u16 data_arrays_table_ptr;
104 u16 pcie_settings_script_ptr;
105 u16 devinit_tables_ptr;
106 u16 devinit_tables_size;
107 u16 bootscripts_ptr;
108 u16 bootscripts_size;
109 u16 nvlink_config_data_ptr;
110} __packed;
111
112struct falcon_data_v2 {
113 u32 falcon_ucode_table_ptr;
114} __packed;
115
116struct falcon_ucode_table_hdr_v1 {
117 u8 version;
118 u8 header_size;
119 u8 entry_size;
120 u8 entry_count;
121 u8 desc_version;
122 u8 desc_size;
123} __packed;
124
125struct falcon_ucode_table_entry_v1 {
126 u8 application_id;
127 u8 target_id;
128 u32 desc_ptr;
129} __packed;
130
131#define TARGET_ID_PMU 0x01
132#define APPLICATION_ID_DEVINIT 0x04
133#define APPLICATION_ID_PRE_OS 0x01
134
135struct falcon_ucode_desc_v1 {
136 union {
137 u32 v_desc;
138 u32 stored_size;
139 } hdr_size;
140 u32 uncompressed_size;
141 u32 virtual_entry;
142 u32 interface_offset;
143 u32 imem_phys_base;
144 u32 imem_load_size;
145 u32 imem_virt_base;
146 u32 imem_sec_base;
147 u32 imem_sec_size;
148 u32 dmem_offset;
149 u32 dmem_phys_base;
150 u32 dmem_load_size;
151} __packed;
152
153struct application_interface_table_hdr_v1 {
154 u8 version;
155 u8 header_size;
156 u8 entry_size;
157 u8 entry_count;
158} __packed;
159
160struct application_interface_entry_v1 {
161 u32 id;
162 u32 dmem_offset;
163} __packed;
164
165#define APPINFO_ID_DEVINIT 0x01
166
167struct devinit_engine_interface {
168 u32 field0;
169 u32 field1;
170 u32 tables_phys_base;
171 u32 tables_virt_base;
172 u32 script_phys_base;
173 u32 script_virt_base;
174 u32 script_virt_entry;
175 u16 script_size;
176 u8 memory_strap_count;
177 u8 reserved;
178 u32 memory_information_table_virt_base;
179 u32 empty_script_virt_base;
180 u32 cond_table_virt_base;
181 u32 io_cond_table_virt_base;
182 u32 data_arrays_table_virt_base;
183 u32 gpio_assignment_table_virt_base;
184} __packed;
185
186struct pci_exp_rom {
187 u16 sig;
188 u8 reserved[0x16];
189 u16 pci_data_struct_ptr;
190 u32 size_of_block;
191} __packed;
192
193struct pci_data_struct {
194 u32 sig;
195 u16 vendor_id;
196 u16 device_id;
197 u16 device_list_ptr;
198 u16 pci_data_struct_len;
199 u8 pci_data_struct_rev;
200 u8 class_code[3];
201 u16 image_len;
202 u16 vendor_rom_rev;
203 u8 code_type;
204 u8 last_image;
205 u16 max_runtime_image_len;
206} __packed;
207
208struct pci_ext_data_struct {
209 u32 sig;
210 u16 nv_pci_data_ext_rev;
211 u16 nv_pci_data_ext_len;
212 u16 sub_image_len;
213 u8 priv_last_image;
214 u8 flags;
215} __packed;
216
217static void nvgpu_bios_parse_bit(struct gk20a *g, int offset);
218
219int nvgpu_bios_parse_rom(struct gk20a *g)
220{
221 int offset = 0;
222 int last = 0;
223 bool found = false;
224 unsigned int i;
225
226 while (!last) {
227 struct pci_exp_rom *pci_rom;
228 struct pci_data_struct *pci_data;
229 struct pci_ext_data_struct *pci_ext_data;
230
231 pci_rom = (struct pci_exp_rom *)&g->bios.data[offset];
232 gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x",
233 pci_rom->sig, pci_rom->pci_data_struct_ptr,
234 pci_rom->size_of_block);
235
236 if (pci_rom->sig != PCI_EXP_ROM_SIG &&
237 pci_rom->sig != PCI_EXP_ROM_SIG_NV) {
238 gk20a_err(g->dev, "invalid VBIOS signature");
239 return -EINVAL;
240 }
241
242 pci_data =
243 (struct pci_data_struct *)
244 &g->bios.data[offset + pci_rom->pci_data_struct_ptr];
245 gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x",
246 pci_data->sig, pci_data->pci_data_struct_len,
247 pci_data->image_len, pci_data->code_type,
248 pci_data->last_image,
249 pci_data->max_runtime_image_len);
250
251 if (pci_data->code_type == 0x3) {
252 pci_ext_data = (struct pci_ext_data_struct *)
253 &g->bios.data[(offset +
254 pci_rom->pci_data_struct_ptr +
255 pci_data->pci_data_struct_len +
256 0xf)
257 & ~0xf];
258 gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x",
259 pci_ext_data->sig,
260 pci_ext_data->nv_pci_data_ext_rev,
261 pci_ext_data->nv_pci_data_ext_len,
262 pci_ext_data->sub_image_len,
263 pci_ext_data->priv_last_image,
264 pci_ext_data->flags);
265
266 gk20a_dbg_fn("expansion rom offset %x",
267 pci_data->image_len * 512);
268 g->bios.expansion_rom_offset =
269 pci_data->image_len * 512;
270 offset += pci_ext_data->sub_image_len * 512;
271 last = pci_ext_data->priv_last_image;
272 } else {
273 offset += pci_data->image_len * 512;
274 last = pci_data->last_image;
275 }
276 }
277
278 gk20a_dbg_info("read bios");
279 for (i = 0; i < g->bios.size - 6; i++) {
280 if (nvgpu_bios_rdu16(g, i) == BIT_HEADER_ID &&
281 nvgpu_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) {
282 nvgpu_bios_parse_bit(g, i);
283 found = true;
284 }
285 }
286
287 if (!found)
288 return -EINVAL;
289 else
290 return 0;
291}
292
293static void nvgpu_bios_parse_biosdata(struct gk20a *g, int offset)
294{
295 struct biosdata biosdata;
296
297 memcpy(&biosdata, &g->bios.data[offset], sizeof(biosdata));
298 gk20a_dbg_fn("bios version %x, oem version %x",
299 biosdata.version,
300 biosdata.oem_version);
301
302 g->gpu_characteristics.vbios_version = biosdata.version;
303 g->gpu_characteristics.vbios_oem_version = biosdata.oem_version;
304}
305
306static void nvgpu_bios_parse_nvinit_ptrs(struct gk20a *g, int offset)
307{
308 struct nvinit_ptrs nvinit_ptrs;
309
310 memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs));
311 gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr,
312 nvinit_ptrs.devinit_tables_size);
313 gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr,
314 nvinit_ptrs.bootscripts_size);
315
316 g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr];
317 g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size;
318 g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr];
319 g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size;
320 g->bios.condition_table_ptr = nvinit_ptrs.condition_table_ptr;
321}
322
323static void nvgpu_bios_parse_memory_ptrs(struct gk20a *g, int offset, u8 version)
324{
325 union memory_ptrs memory_ptrs;
326
327 if ((version < 1) || (version > 2))
328 return;
329
330 memcpy(&memory_ptrs, &g->bios.data[offset], sizeof(memory_ptrs));
331
332 g->bios.mem_strap_data_count = (version > 1) ? memory_ptrs.v2.mem_strap_data_count :
333 memory_ptrs.v1.mem_strap_data_count;
334 g->bios.mem_strap_xlat_tbl_ptr = (version > 1) ? memory_ptrs.v2.mem_strap_xlat_tbl_ptr :
335 memory_ptrs.v1.mem_strap_xlat_tbl_ptr;
336}
337
338static void nvgpu_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
339{
340 struct devinit_engine_interface interface;
341
342 memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface));
343 gk20a_dbg_fn("devinit tables phys %x script phys %x size %d",
344 interface.tables_phys_base,
345 interface.script_phys_base,
346 interface.script_size);
347
348 g->bios.devinit_tables_phys_base = interface.tables_phys_base;
349 g->bios.devinit_script_phys_base = interface.script_phys_base;
350}
351
352static int nvgpu_bios_parse_appinfo_table(struct gk20a *g, int offset)
353{
354 struct application_interface_table_hdr_v1 hdr;
355 int i;
356
357 memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
358
359 gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d",
360 hdr.version, hdr.header_size,
361 hdr.entry_size, hdr.entry_count);
362
363 if (hdr.version != 1)
364 return 0;
365
366 offset += sizeof(hdr);
367 for (i = 0; i < hdr.entry_count; i++) {
368 struct application_interface_entry_v1 entry;
369
370 memcpy(&entry, &g->bios.data[offset], sizeof(entry));
371
372 gk20a_dbg_fn("appInfo id %d dmem_offset %d",
373 entry.id, entry.dmem_offset);
374
375 if (entry.id == APPINFO_ID_DEVINIT)
376 nvgpu_bios_parse_devinit_appinfo(g, entry.dmem_offset);
377
378 offset += hdr.entry_size;
379 }
380
381 return 0;
382}
383
384static int nvgpu_bios_parse_falcon_ucode_desc(struct gk20a *g,
385 struct nvgpu_bios_ucode *ucode, int offset)
386{
387 struct falcon_ucode_desc_v1 desc;
388
389 memcpy(&desc, &g->bios.data[offset], sizeof(desc));
390 gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d",
391 desc.hdr_size.stored_size, desc.uncompressed_size);
392 gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x",
393 desc.virtual_entry, desc.interface_offset);
394 gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x",
395 desc.imem_phys_base, desc.imem_load_size,
396 desc.imem_virt_base, desc.imem_sec_base,
397 desc.imem_sec_size);
398 gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d",
399 desc.dmem_offset, desc.dmem_phys_base,
400 desc.dmem_load_size);
401
402 if (desc.hdr_size.stored_size != desc.uncompressed_size) {
403 gk20a_dbg_info("does not match");
404 return -EINVAL;
405 }
406
407 ucode->code_entry_point = desc.virtual_entry;
408 ucode->bootloader = &g->bios.data[offset] + sizeof(desc);
409 ucode->bootloader_phys_base = desc.imem_phys_base;
410 ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size;
411 ucode->ucode = ucode->bootloader + ucode->bootloader_size;
412 ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size;
413 ucode->size = desc.imem_sec_size;
414 ucode->dmem = ucode->bootloader + desc.dmem_offset;
415 ucode->dmem_phys_base = desc.dmem_phys_base;
416 ucode->dmem_size = desc.dmem_load_size;
417
418 return nvgpu_bios_parse_appinfo_table(g,
419 offset + sizeof(desc) +
420 desc.dmem_offset + desc.interface_offset);
421}
422
423static int nvgpu_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
424{
425 struct falcon_ucode_table_hdr_v1 hdr;
426 int i;
427
428 memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
429 gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d",
430 hdr.version, hdr.header_size,
431 hdr.entry_size, hdr.entry_count,
432 hdr.desc_version, hdr.desc_size);
433
434 if (hdr.version != 1)
435 return -EINVAL;
436
437 offset += hdr.header_size;
438
439 for (i = 0; i < hdr.entry_count; i++) {
440 struct falcon_ucode_table_entry_v1 entry;
441
442 memcpy(&entry, &g->bios.data[offset], sizeof(entry));
443
444 gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x",
445 entry.application_id, entry.target_id,
446 entry.desc_ptr);
447
448 if (entry.target_id == TARGET_ID_PMU &&
449 entry.application_id == APPLICATION_ID_DEVINIT) {
450 int err;
451
452 err = nvgpu_bios_parse_falcon_ucode_desc(g,
453 &g->bios.devinit, entry.desc_ptr);
454 if (err)
455 err = nvgpu_bios_parse_falcon_ucode_desc(g,
456 &g->bios.devinit,
457 entry.desc_ptr +
458 g->bios.expansion_rom_offset);
459
460 if (err)
461 gk20a_err(dev_from_gk20a(g),
462 "could not parse devinit ucode desc");
463 } else if (entry.target_id == TARGET_ID_PMU &&
464 entry.application_id == APPLICATION_ID_PRE_OS) {
465 int err;
466
467 err = nvgpu_bios_parse_falcon_ucode_desc(g,
468 &g->bios.preos, entry.desc_ptr);
469 if (err)
470 err = nvgpu_bios_parse_falcon_ucode_desc(g,
471 &g->bios.preos,
472 entry.desc_ptr +
473 g->bios.expansion_rom_offset);
474
475 if (err)
476 gk20a_err(dev_from_gk20a(g),
477 "could not parse preos ucode desc");
478 }
479
480 offset += hdr.entry_size;
481 }
482
483 return 0;
484}
485
486static void nvgpu_bios_parse_falcon_data_v2(struct gk20a *g, int offset)
487{
488 struct falcon_data_v2 falcon_data;
489 int err;
490
491 memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data));
492 gk20a_dbg_fn("falcon ucode table ptr %x",
493 falcon_data.falcon_ucode_table_ptr);
494 err = nvgpu_bios_parse_falcon_ucode_table(g,
495 falcon_data.falcon_ucode_table_ptr);
496 if (err)
497 err = nvgpu_bios_parse_falcon_ucode_table(g,
498 falcon_data.falcon_ucode_table_ptr +
499 g->bios.expansion_rom_offset);
500
501 if (err)
502 gk20a_err(dev_from_gk20a(g),
503 "could not parse falcon ucode table");
504}
505
506void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
507 struct bit_token *ptoken, u8 table_id)
508{
509 u32 perf_table_id_offset = 0;
510 u8 *perf_table_ptr = NULL;
511 u8 data_size = 4;
512
513 if (ptoken != NULL) {
514
515 if (ptoken->token_id == TOKEN_ID_VIRT_PTRS) {
516 perf_table_id_offset = *((u16 *)&g->bios.data[
517 ptoken->data_ptr +
518 (table_id * PERF_PTRS_WIDTH_16)]);
519 data_size = PERF_PTRS_WIDTH_16;
520 } else {
521 perf_table_id_offset = *((u32 *)&g->bios.data[
522 ptoken->data_ptr +
523 (table_id * PERF_PTRS_WIDTH)]);
524 data_size = PERF_PTRS_WIDTH;
525 }
526 } else
527 return (void *)perf_table_ptr;
528
529 if (table_id < (ptoken->data_size/data_size)) {
530
531 gk20a_dbg_info("Perf_Tbl_ID-offset 0x%x Tbl_ID_Ptr-offset- 0x%x",
532 (ptoken->data_ptr +
533 (table_id * data_size)),
534 perf_table_id_offset);
535
536 if (perf_table_id_offset != 0) {
537 /* check is perf_table_id_offset is > 64k */
538 if (perf_table_id_offset & ~0xFFFF)
539 perf_table_ptr =
540 &g->bios.data[g->bios.expansion_rom_offset +
541 perf_table_id_offset];
542 else
543 perf_table_ptr =
544 &g->bios.data[perf_table_id_offset];
545 } else
546 gk20a_warn(g->dev, "PERF TABLE ID %d is NULL",
547 table_id);
548 } else
549 gk20a_warn(g->dev, "INVALID PERF TABLE ID - %d ", table_id);
550
551 return (void *)perf_table_ptr;
552}
553
554static void nvgpu_bios_parse_bit(struct gk20a *g, int offset)
555{
556 struct bit bit;
557 struct bit_token bit_token;
558 int i;
559
560 gk20a_dbg_fn("");
561 memcpy(&bit, &g->bios.data[offset], sizeof(bit));
562
563 gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature);
564 gk20a_dbg_info("tokens: %d entries * %d bytes",
565 bit.token_entries, bit.token_size);
566
567 offset += bit.header_size;
568 for (i = 0; i < bit.token_entries; i++) {
569 memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token));
570
571 gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d",
572 bit_token.token_id, bit_token.data_ptr,
573 bit_token.data_size, bit_token.data_version);
574
575 switch (bit_token.token_id) {
576 case TOKEN_ID_BIOSDATA:
577 nvgpu_bios_parse_biosdata(g, bit_token.data_ptr);
578 break;
579 case TOKEN_ID_NVINIT_PTRS:
580 nvgpu_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
581 break;
582 case TOKEN_ID_FALCON_DATA:
583 if (bit_token.data_version == 2)
584 nvgpu_bios_parse_falcon_data_v2(g,
585 bit_token.data_ptr);
586 break;
587 case TOKEN_ID_PERF_PTRS:
588 g->bios.perf_token =
589 (struct bit_token *)&g->bios.data[offset];
590 break;
591 case TOKEN_ID_CLOCK_PTRS:
592 g->bios.clock_token =
593 (struct bit_token *)&g->bios.data[offset];
594 break;
595 case TOKEN_ID_VIRT_PTRS:
596 g->bios.virt_token =
597 (struct bit_token *)&g->bios.data[offset];
598 break;
599 case TOKEN_ID_MEMORY_PTRS:
600 nvgpu_bios_parse_memory_ptrs(g, bit_token.data_ptr,
601 bit_token.data_version);
602 default:
603 break;
604 }
605
606 offset += bit.token_size;
607 }
608 gk20a_dbg_fn("done");
609}
610
611static u32 __nvgpu_bios_readbyte(struct gk20a *g, u32 offset)
612{
613 return (u32) g->bios.data[offset];
614}
615
616u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset)
617{
618 return (u8) __nvgpu_bios_readbyte(g, offset);
619}
620
621s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset)
622{
623 u32 val;
624 val = __nvgpu_bios_readbyte(g, offset);
625 val = val & 0x80 ? (val | ~0xff) : val;
626
627 return (s8) val;
628}
629
630u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset)
631{
632 u16 val;
633
634 val = __nvgpu_bios_readbyte(g, offset) |
635 (__nvgpu_bios_readbyte(g, offset+1) << 8);
636
637 return val;
638}
639
640u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset)
641{
642 u32 val;
643
644 val = __nvgpu_bios_readbyte(g, offset) |
645 (__nvgpu_bios_readbyte(g, offset+1) << 8) |
646 (__nvgpu_bios_readbyte(g, offset+2) << 16) |
647 (__nvgpu_bios_readbyte(g, offset+3) << 24);
648
649 return val;
650}
651
652static void nvgpu_bios_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
653 u32 reg, u32 stride, u32 count, u32 data_table_offset)
654{
655 u8 i;
656 u32 data, strap, index;
657
658 if (*condition) {
659
660 strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
661
662 index = g->bios.mem_strap_xlat_tbl_ptr ?
663 nvgpu_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
664 strap) : strap;
665
666 for (i = 0; i < count; i++) {
667 data = nvgpu_bios_read_u32(g, data_table_offset + ((i *
668 g->bios.mem_strap_data_count + index) *
669 sizeof(u32)));
670 gk20a_writel(g, reg, data);
671 reg += stride;
672 }
673 }
674}
675
676static void gp106_init_condition(struct gk20a *g, bool *condition,
677 u32 condition_id)
678{
679 struct condition_entry entry;
680
681 entry.cond_addr = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
682 sizeof(entry)*condition_id);
683 entry.cond_mask = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
684 sizeof(entry)*condition_id + 4);
685 entry.cond_compare = nvgpu_bios_read_u32(g, g->bios.condition_table_ptr +
686 sizeof(entry)*condition_id + 8);
687
688 if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
689 != entry.cond_compare) {
690 *condition = false;
691 }
692}
693
694int nvgpu_bios_execute_script(struct gk20a *g, u32 offset)
695{
696 u8 opcode;
697 u32 ip;
698 u32 operand[8];
699 bool condition, end;
700 int status = 0;
701
702 ip = offset;
703 condition = true;
704 end = false;
705
706 while (!end) {
707
708 opcode = nvgpu_bios_read_u8(g, ip++);
709
710 switch (opcode) {
711
712 case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
713 operand[0] = nvgpu_bios_read_u32(g, ip);
714 operand[1] = nvgpu_bios_read_u8(g, ip+4);
715 operand[2] = nvgpu_bios_read_u8(g, ip+5);
716 ip += 6;
717
718 nvgpu_bios_init_xmemsel_zm_nv_reg_array(g, &condition,
719 operand[0], operand[1], operand[2], ip);
720 ip += operand[2] * sizeof(u32) *
721 g->bios.mem_strap_data_count;
722 break;
723
724 case INIT_CONDITION:
725 operand[0] = nvgpu_bios_read_u8(g, ip);
726 ip++;
727
728 gp106_init_condition(g, &condition, operand[0]);
729 break;
730
731 case INIT_RESUME:
732 condition = true;
733 break;
734
735 case INIT_DONE:
736 end = true;
737 break;
738
739 default:
740 gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
741 end = true;
742 status = -EINVAL;
743 break;
744 }
745 }
746
747 return status;
748}
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index ee6586ae..91c82104 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -918,8 +918,8 @@ int gk20a_pm_finalize_poweron(struct device *dev)
918 g->gpu_reset_done = true; 918 g->gpu_reset_done = true;
919 } 919 }
920 920
921 if (g->ops.bios.init) 921 if (g->ops.bios_init)
922 err = g->ops.bios.init(g); 922 err = g->ops.bios_init(g);
923 if (err) 923 if (err)
924 goto done; 924 goto done;
925 925
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index 7f2383d9..b796b2cc 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -54,7 +54,6 @@ struct acr_desc;
54#include "cde_gk20a.h" 54#include "cde_gk20a.h"
55#include "debug_gk20a.h" 55#include "debug_gk20a.h"
56#include "sched_gk20a.h" 56#include "sched_gk20a.h"
57#include "gm206/bios_gm206.h"
58#ifdef CONFIG_ARCH_TEGRA_18x_SOC 57#ifdef CONFIG_ARCH_TEGRA_18x_SOC
59#include "clk/clk.h" 58#include "clk/clk.h"
60#include "clk/clk_arb.h" 59#include "clk/clk_arb.h"
@@ -62,7 +61,6 @@ struct acr_desc;
62#include "pmgr/pmgr.h" 61#include "pmgr/pmgr.h"
63#include "therm/thrm.h" 62#include "therm/thrm.h"
64#endif 63#endif
65#include "gm206/bios_gm206.h"
66 64
67#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0) 65#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 18, 0)
68#define WRITE_ONCE(x, val) \ 66#define WRITE_ONCE(x, val) \
@@ -751,12 +749,8 @@ struct gpu_ops {
751 int (*chip_init_gpu_characteristics)(struct gk20a *g); 749 int (*chip_init_gpu_characteristics)(struct gk20a *g);
752 int (*read_ptimer)(struct gk20a *g, u64 *value); 750 int (*read_ptimer)(struct gk20a *g, u64 *value);
753 751
754 struct { 752 int (*bios_init)(struct gk20a *g);
755 int (*init)(struct gk20a *g); 753
756 void *(*get_perf_table_ptrs)(struct gk20a *g,
757 struct bit_token *ptoken, u8 table_id);
758 int (*execute_script)(struct gk20a *g, u32 offset);
759 } bios;
760#if defined(CONFIG_GK20A_CYCLE_STATS) 754#if defined(CONFIG_GK20A_CYCLE_STATS)
761 struct { 755 struct {
762 int (*enable_snapshot)(struct channel_gk20a *ch, 756 int (*enable_snapshot)(struct channel_gk20a *ch,
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.c b/drivers/gpu/nvgpu/gm206/bios_gm206.c
index a5551f42..3d12b9ac 100644
--- a/drivers/gpu/nvgpu/gm206/bios_gm206.c
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.c
@@ -16,6 +16,8 @@
16#include <linux/firmware.h> 16#include <linux/firmware.h>
17#include <linux/pci.h> 17#include <linux/pci.h>
18 18
19#include <nvgpu/bios.h>
20
19#include "gk20a/gk20a.h" 21#include "gk20a/gk20a.h"
20#include "gm20b/fifo_gm20b.h" 22#include "gm20b/fifo_gm20b.h"
21#include "fifo_gm206.h" 23#include "fifo_gm206.h"
@@ -27,617 +29,12 @@
27#include <nvgpu/hw/gm206/hw_mc_gm206.h> 29#include <nvgpu/hw/gm206/hw_mc_gm206.h>
28#include <nvgpu/hw/gm206/hw_top_gm206.h> 30#include <nvgpu/hw/gm206/hw_top_gm206.h>
29 31
30#define BIT_HEADER_ID 0xb8ff
31#define BIT_HEADER_SIGNATURE 0x00544942
32#define BIOS_SIZE 0x40000
33#define PCI_EXP_ROM_SIG 0xaa55
34#define PCI_EXP_ROM_SIG_NV 0x4e56
35#define ROM_FILE_PAYLOAD_OFFSET 0xa00
36#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */ 32#define PMU_BOOT_TIMEOUT_DEFAULT 100 /* usec */
37#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */ 33#define PMU_BOOT_TIMEOUT_MAX 2000000 /* usec */
38#define BIOS_OVERLAY_NAME "bios-%04x.rom" 34#define BIOS_OVERLAY_NAME "bios-%04x.rom"
39#define BIOS_OVERLAY_NAME_FORMATTED "bios-xxxx.rom" 35#define BIOS_OVERLAY_NAME_FORMATTED "bios-xxxx.rom"
40 36#define ROM_FILE_PAYLOAD_OFFSET 0xa00
41static u16 gm206_bios_rdu16(struct gk20a *g, int offset) 37#define BIOS_SIZE 0x40000
42{
43 u16 val = (g->bios.data[offset+1] << 8) + g->bios.data[offset];
44 return val;
45}
46
47static u32 gm206_bios_rdu32(struct gk20a *g, int offset)
48{
49 u32 val = (g->bios.data[offset+3] << 24) +
50 (g->bios.data[offset+2] << 16) +
51 (g->bios.data[offset+1] << 8) +
52 g->bios.data[offset];
53 return val;
54}
55
56struct bit {
57 u16 id;
58 u32 signature;
59 u16 bcd_version;
60 u8 header_size;
61 u8 token_size;
62 u8 token_entries;
63 u8 header_checksum;
64} __packed;
65
66#define TOKEN_ID_BIOSDATA 0x42
67#define TOKEN_ID_NVINIT_PTRS 0x49
68#define TOKEN_ID_FALCON_DATA 0x70
69#define TOKEN_ID_PERF_PTRS 0x50
70#define TOKEN_ID_CLOCK_PTRS 0x43
71#define TOKEN_ID_VIRT_PTRS 0x56
72#define TOKEN_ID_MEMORY_PTRS 0x4D
73
74
75union memory_ptrs {
76 struct {
77 u8 rsvd0[2];
78 u8 mem_strap_data_count;
79 u16 mem_strap_xlat_tbl_ptr;
80 u8 rsvd1[8];
81 } v1 __packed;
82 struct {
83 u8 mem_strap_data_count;
84 u16 mem_strap_xlat_tbl_ptr;
85 u8 rsvd[14];
86 } v2 __packed;
87};
88
89struct biosdata {
90 u32 version;
91 u8 oem_version;
92 u8 checksum;
93 u16 int15callbackspost;
94 u16 int16callbackssystem;
95 u16 boardid;
96 u16 framecount;
97 u8 biosmoddate[8];
98} __packed;
99
100struct nvinit_ptrs {
101 u16 initscript_table_ptr;
102 u16 macro_index_table_ptr;
103 u16 macro_table_ptr;
104 u16 condition_table_ptr;
105 u16 io_condition_table_ptr;
106 u16 io_flag_condition_table_ptr;
107 u16 init_function_table_ptr;
108 u16 vbios_private_table_ptr;
109 u16 data_arrays_table_ptr;
110 u16 pcie_settings_script_ptr;
111 u16 devinit_tables_ptr;
112 u16 devinit_tables_size;
113 u16 bootscripts_ptr;
114 u16 bootscripts_size;
115 u16 nvlink_config_data_ptr;
116} __packed;
117
118struct falcon_data_v2 {
119 u32 falcon_ucode_table_ptr;
120} __packed;
121
122struct falcon_ucode_table_hdr_v1 {
123 u8 version;
124 u8 header_size;
125 u8 entry_size;
126 u8 entry_count;
127 u8 desc_version;
128 u8 desc_size;
129} __packed;
130
131struct falcon_ucode_table_entry_v1 {
132 u8 application_id;
133 u8 target_id;
134 u32 desc_ptr;
135} __packed;
136
137#define TARGET_ID_PMU 0x01
138#define APPLICATION_ID_DEVINIT 0x04
139#define APPLICATION_ID_PRE_OS 0x01
140
141struct falcon_ucode_desc_v1 {
142 union {
143 u32 v_desc;
144 u32 stored_size;
145 } hdr_size;
146 u32 uncompressed_size;
147 u32 virtual_entry;
148 u32 interface_offset;
149 u32 imem_phys_base;
150 u32 imem_load_size;
151 u32 imem_virt_base;
152 u32 imem_sec_base;
153 u32 imem_sec_size;
154 u32 dmem_offset;
155 u32 dmem_phys_base;
156 u32 dmem_load_size;
157} __packed;
158
159struct application_interface_table_hdr_v1 {
160 u8 version;
161 u8 header_size;
162 u8 entry_size;
163 u8 entry_count;
164} __packed;
165
166struct application_interface_entry_v1 {
167 u32 id;
168 u32 dmem_offset;
169} __packed;
170
171#define APPINFO_ID_DEVINIT 0x01
172
173struct devinit_engine_interface {
174 u32 field0;
175 u32 field1;
176 u32 tables_phys_base;
177 u32 tables_virt_base;
178 u32 script_phys_base;
179 u32 script_virt_base;
180 u32 script_virt_entry;
181 u16 script_size;
182 u8 memory_strap_count;
183 u8 reserved;
184 u32 memory_information_table_virt_base;
185 u32 empty_script_virt_base;
186 u32 cond_table_virt_base;
187 u32 io_cond_table_virt_base;
188 u32 data_arrays_table_virt_base;
189 u32 gpio_assignment_table_virt_base;
190} __packed;
191
192struct pci_exp_rom {
193 u16 sig;
194 u8 reserved[0x16];
195 u16 pci_data_struct_ptr;
196 u32 size_of_block;
197} __packed;
198
199struct pci_data_struct {
200 u32 sig;
201 u16 vendor_id;
202 u16 device_id;
203 u16 device_list_ptr;
204 u16 pci_data_struct_len;
205 u8 pci_data_struct_rev;
206 u8 class_code[3];
207 u16 image_len;
208 u16 vendor_rom_rev;
209 u8 code_type;
210 u8 last_image;
211 u16 max_runtime_image_len;
212} __packed;
213
214struct pci_ext_data_struct {
215 u32 sig;
216 u16 nv_pci_data_ext_rev;
217 u16 nv_pci_data_ext_len;
218 u16 sub_image_len;
219 u8 priv_last_image;
220 u8 flags;
221} __packed;
222
223static int gm206_bios_parse_rom(struct gk20a *g)
224{
225 int offset = 0;
226 int last = 0;
227
228 while (!last) {
229 struct pci_exp_rom *pci_rom;
230 struct pci_data_struct *pci_data;
231 struct pci_ext_data_struct *pci_ext_data;
232
233 pci_rom = (struct pci_exp_rom *)&g->bios.data[offset];
234 gk20a_dbg_fn("pci rom sig %04x ptr %04x block %x",
235 pci_rom->sig, pci_rom->pci_data_struct_ptr,
236 pci_rom->size_of_block);
237
238 if (pci_rom->sig != PCI_EXP_ROM_SIG &&
239 pci_rom->sig != PCI_EXP_ROM_SIG_NV) {
240 gk20a_err(g->dev, "invalid VBIOS signature");
241 return -EINVAL;
242 }
243
244 pci_data =
245 (struct pci_data_struct *)
246 &g->bios.data[offset + pci_rom->pci_data_struct_ptr];
247 gk20a_dbg_fn("pci data sig %08x len %d image len %x type %x last %d max %08x",
248 pci_data->sig, pci_data->pci_data_struct_len,
249 pci_data->image_len, pci_data->code_type,
250 pci_data->last_image,
251 pci_data->max_runtime_image_len);
252
253 if (pci_data->code_type == 0x3) {
254 pci_ext_data = (struct pci_ext_data_struct *)
255 &g->bios.data[(offset +
256 pci_rom->pci_data_struct_ptr +
257 pci_data->pci_data_struct_len +
258 0xf)
259 & ~0xf];
260 gk20a_dbg_fn("pci ext data sig %08x rev %x len %x sub_image_len %x priv_last %d flags %x",
261 pci_ext_data->sig,
262 pci_ext_data->nv_pci_data_ext_rev,
263 pci_ext_data->nv_pci_data_ext_len,
264 pci_ext_data->sub_image_len,
265 pci_ext_data->priv_last_image,
266 pci_ext_data->flags);
267
268 gk20a_dbg_fn("expansion rom offset %x",
269 pci_data->image_len * 512);
270 g->bios.expansion_rom_offset =
271 pci_data->image_len * 512;
272 offset += pci_ext_data->sub_image_len * 512;
273 last = pci_ext_data->priv_last_image;
274 } else {
275 offset += pci_data->image_len * 512;
276 last = pci_data->last_image;
277 }
278 }
279
280 return 0;
281}
282
283static void gm206_bios_parse_biosdata(struct gk20a *g, int offset)
284{
285 struct biosdata biosdata;
286
287 memcpy(&biosdata, &g->bios.data[offset], sizeof(biosdata));
288 gk20a_dbg_fn("bios version %x, oem version %x",
289 biosdata.version,
290 biosdata.oem_version);
291
292 g->gpu_characteristics.vbios_version = biosdata.version;
293 g->gpu_characteristics.vbios_oem_version = biosdata.oem_version;
294}
295
296static void gm206_bios_parse_nvinit_ptrs(struct gk20a *g, int offset)
297{
298 struct nvinit_ptrs nvinit_ptrs;
299
300 memcpy(&nvinit_ptrs, &g->bios.data[offset], sizeof(nvinit_ptrs));
301 gk20a_dbg_fn("devinit ptr %x size %d", nvinit_ptrs.devinit_tables_ptr,
302 nvinit_ptrs.devinit_tables_size);
303 gk20a_dbg_fn("bootscripts ptr %x size %d", nvinit_ptrs.bootscripts_ptr,
304 nvinit_ptrs.bootscripts_size);
305
306 g->bios.devinit_tables = &g->bios.data[nvinit_ptrs.devinit_tables_ptr];
307 g->bios.devinit_tables_size = nvinit_ptrs.devinit_tables_size;
308 g->bios.bootscripts = &g->bios.data[nvinit_ptrs.bootscripts_ptr];
309 g->bios.bootscripts_size = nvinit_ptrs.bootscripts_size;
310 g->bios.condition_table_ptr = nvinit_ptrs.condition_table_ptr;
311}
312
313static void gm206_bios_parse_memory_ptrs(struct gk20a *g, int offset, u8 version)
314{
315 union memory_ptrs memory_ptrs;
316
317 if ((version < 1) || (version > 2))
318 return;
319
320 memcpy(&memory_ptrs, &g->bios.data[offset], sizeof(memory_ptrs));
321
322 g->bios.mem_strap_data_count = (version > 1) ? memory_ptrs.v2.mem_strap_data_count :
323 memory_ptrs.v1.mem_strap_data_count;
324 g->bios.mem_strap_xlat_tbl_ptr = (version > 1) ? memory_ptrs.v2.mem_strap_xlat_tbl_ptr :
325 memory_ptrs.v1.mem_strap_xlat_tbl_ptr;
326}
327
328static void gm206_bios_parse_devinit_appinfo(struct gk20a *g, int dmem_offset)
329{
330 struct devinit_engine_interface interface;
331
332 memcpy(&interface, &g->bios.devinit.dmem[dmem_offset], sizeof(interface));
333 gk20a_dbg_fn("devinit tables phys %x script phys %x size %d",
334 interface.tables_phys_base,
335 interface.script_phys_base,
336 interface.script_size);
337
338 g->bios.devinit_tables_phys_base = interface.tables_phys_base;
339 g->bios.devinit_script_phys_base = interface.script_phys_base;
340}
341
342static int gm206_bios_parse_appinfo_table(struct gk20a *g, int offset)
343{
344 struct application_interface_table_hdr_v1 hdr;
345 int i;
346
347 memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
348
349 gk20a_dbg_fn("appInfoHdr ver %d size %d entrySize %d entryCount %d",
350 hdr.version, hdr.header_size,
351 hdr.entry_size, hdr.entry_count);
352
353 if (hdr.version != 1)
354 return 0;
355
356 offset += sizeof(hdr);
357 for (i = 0; i < hdr.entry_count; i++) {
358 struct application_interface_entry_v1 entry;
359
360 memcpy(&entry, &g->bios.data[offset], sizeof(entry));
361
362 gk20a_dbg_fn("appInfo id %d dmem_offset %d",
363 entry.id, entry.dmem_offset);
364
365 if (entry.id == APPINFO_ID_DEVINIT)
366 gm206_bios_parse_devinit_appinfo(g, entry.dmem_offset);
367
368 offset += hdr.entry_size;
369 }
370
371 return 0;
372}
373
374static int gm206_bios_parse_falcon_ucode_desc(struct gk20a *g,
375 struct nvgpu_bios_ucode *ucode, int offset)
376{
377 struct falcon_ucode_desc_v1 desc;
378
379 memcpy(&desc, &g->bios.data[offset], sizeof(desc));
380 gk20a_dbg_info("falcon ucode desc stored size %d uncompressed size %d",
381 desc.hdr_size.stored_size, desc.uncompressed_size);
382 gk20a_dbg_info("falcon ucode desc virtualEntry %x, interfaceOffset %x",
383 desc.virtual_entry, desc.interface_offset);
384 gk20a_dbg_info("falcon ucode IMEM phys base %x, load size %x virt base %x sec base %x sec size %x",
385 desc.imem_phys_base, desc.imem_load_size,
386 desc.imem_virt_base, desc.imem_sec_base,
387 desc.imem_sec_size);
388 gk20a_dbg_info("falcon ucode DMEM offset %d phys base %x, load size %d",
389 desc.dmem_offset, desc.dmem_phys_base,
390 desc.dmem_load_size);
391
392 if (desc.hdr_size.stored_size != desc.uncompressed_size) {
393 gk20a_dbg_info("does not match");
394 return -EINVAL;
395 }
396
397 ucode->code_entry_point = desc.virtual_entry;
398 ucode->bootloader = &g->bios.data[offset] + sizeof(desc);
399 ucode->bootloader_phys_base = desc.imem_phys_base;
400 ucode->bootloader_size = desc.imem_load_size - desc.imem_sec_size;
401 ucode->ucode = ucode->bootloader + ucode->bootloader_size;
402 ucode->phys_base = ucode->bootloader_phys_base + ucode->bootloader_size;
403 ucode->size = desc.imem_sec_size;
404 ucode->dmem = ucode->bootloader + desc.dmem_offset;
405 ucode->dmem_phys_base = desc.dmem_phys_base;
406 ucode->dmem_size = desc.dmem_load_size;
407
408 return gm206_bios_parse_appinfo_table(g,
409 offset + sizeof(desc) +
410 desc.dmem_offset + desc.interface_offset);
411}
412
413static int gm206_bios_parse_falcon_ucode_table(struct gk20a *g, int offset)
414{
415 struct falcon_ucode_table_hdr_v1 hdr;
416 int i;
417
418 memcpy(&hdr, &g->bios.data[offset], sizeof(hdr));
419 gk20a_dbg_fn("falcon ucode table ver %d size %d entrySize %d entryCount %d descVer %d descSize %d",
420 hdr.version, hdr.header_size,
421 hdr.entry_size, hdr.entry_count,
422 hdr.desc_version, hdr.desc_size);
423
424 if (hdr.version != 1)
425 return -EINVAL;
426
427 offset += hdr.header_size;
428
429 for (i = 0; i < hdr.entry_count; i++) {
430 struct falcon_ucode_table_entry_v1 entry;
431
432 memcpy(&entry, &g->bios.data[offset], sizeof(entry));
433
434 gk20a_dbg_fn("falcon ucode table entry appid %x targetId %x descPtr %x",
435 entry.application_id, entry.target_id,
436 entry.desc_ptr);
437
438 if (entry.target_id == TARGET_ID_PMU &&
439 entry.application_id == APPLICATION_ID_DEVINIT) {
440 int err;
441
442 err = gm206_bios_parse_falcon_ucode_desc(g,
443 &g->bios.devinit, entry.desc_ptr);
444 if (err)
445 err = gm206_bios_parse_falcon_ucode_desc(g,
446 &g->bios.devinit,
447 entry.desc_ptr +
448 g->bios.expansion_rom_offset);
449
450 if (err)
451 gk20a_err(dev_from_gk20a(g),
452 "could not parse devinit ucode desc");
453 } else if (entry.target_id == TARGET_ID_PMU &&
454 entry.application_id == APPLICATION_ID_PRE_OS) {
455 int err;
456
457 err = gm206_bios_parse_falcon_ucode_desc(g,
458 &g->bios.preos, entry.desc_ptr);
459 if (err)
460 err = gm206_bios_parse_falcon_ucode_desc(g,
461 &g->bios.preos,
462 entry.desc_ptr +
463 g->bios.expansion_rom_offset);
464
465 if (err)
466 gk20a_err(dev_from_gk20a(g),
467 "could not parse preos ucode desc");
468 }
469
470 offset += hdr.entry_size;
471 }
472
473 return 0;
474}
475
476static void gm206_bios_parse_falcon_data_v2(struct gk20a *g, int offset)
477{
478 struct falcon_data_v2 falcon_data;
479 int err;
480
481 memcpy(&falcon_data, &g->bios.data[offset], sizeof(falcon_data));
482 gk20a_dbg_fn("falcon ucode table ptr %x",
483 falcon_data.falcon_ucode_table_ptr);
484 err = gm206_bios_parse_falcon_ucode_table(g,
485 falcon_data.falcon_ucode_table_ptr);
486 if (err)
487 err = gm206_bios_parse_falcon_ucode_table(g,
488 falcon_data.falcon_ucode_table_ptr +
489 g->bios.expansion_rom_offset);
490
491 if (err)
492 gk20a_err(dev_from_gk20a(g),
493 "could not parse falcon ucode table");
494}
495
496static void *gm206_bios_get_perf_table_ptrs(struct gk20a *g,
497 struct bit_token *ptoken, u8 table_id)
498{
499 u32 perf_table_id_offset = 0;
500 u8 *perf_table_ptr = NULL;
501 u8 data_size = 4;
502
503 if (ptoken != NULL) {
504
505 if (ptoken->token_id == TOKEN_ID_VIRT_PTRS) {
506 perf_table_id_offset = *((u16 *)&g->bios.data[
507 ptoken->data_ptr +
508 (table_id * PERF_PTRS_WIDTH_16)]);
509 data_size = PERF_PTRS_WIDTH_16;
510 } else {
511 perf_table_id_offset = *((u32 *)&g->bios.data[
512 ptoken->data_ptr +
513 (table_id * PERF_PTRS_WIDTH)]);
514 data_size = PERF_PTRS_WIDTH;
515 }
516 } else
517 return (void *)perf_table_ptr;
518
519 if (table_id < (ptoken->data_size/data_size)) {
520
521 gk20a_dbg_info("Perf_Tbl_ID-offset 0x%x Tbl_ID_Ptr-offset- 0x%x",
522 (ptoken->data_ptr +
523 (table_id * data_size)),
524 perf_table_id_offset);
525
526 if (perf_table_id_offset != 0) {
527 /* check is perf_table_id_offset is > 64k */
528 if (perf_table_id_offset & ~0xFFFF)
529 perf_table_ptr =
530 &g->bios.data[g->bios.expansion_rom_offset +
531 perf_table_id_offset];
532 else
533 perf_table_ptr =
534 &g->bios.data[perf_table_id_offset];
535 } else
536 gk20a_warn(g->dev, "PERF TABLE ID %d is NULL",
537 table_id);
538 } else
539 gk20a_warn(g->dev, "INVALID PERF TABLE ID - %d ", table_id);
540
541 return (void *)perf_table_ptr;
542}
543
544static void gm206_bios_parse_bit(struct gk20a *g, int offset)
545{
546 struct bit bit;
547 struct bit_token bit_token;
548 int i;
549
550 gk20a_dbg_fn("");
551 memcpy(&bit, &g->bios.data[offset], sizeof(bit));
552
553 gk20a_dbg_info("BIT header: %04x %08x", bit.id, bit.signature);
554 gk20a_dbg_info("tokens: %d entries * %d bytes",
555 bit.token_entries, bit.token_size);
556
557 offset += bit.header_size;
558 for (i = 0; i < bit.token_entries; i++) {
559 memcpy(&bit_token, &g->bios.data[offset], sizeof(bit_token));
560
561 gk20a_dbg_info("BIT token id %d ptr %d size %d ver %d",
562 bit_token.token_id, bit_token.data_ptr,
563 bit_token.data_size, bit_token.data_version);
564
565 switch (bit_token.token_id) {
566 case TOKEN_ID_BIOSDATA:
567 gm206_bios_parse_biosdata(g, bit_token.data_ptr);
568 break;
569 case TOKEN_ID_NVINIT_PTRS:
570 gm206_bios_parse_nvinit_ptrs(g, bit_token.data_ptr);
571 break;
572 case TOKEN_ID_FALCON_DATA:
573 if (bit_token.data_version == 2)
574 gm206_bios_parse_falcon_data_v2(g,
575 bit_token.data_ptr);
576 break;
577 case TOKEN_ID_PERF_PTRS:
578 g->bios.perf_token =
579 (struct bit_token *)&g->bios.data[offset];
580 break;
581 case TOKEN_ID_CLOCK_PTRS:
582 g->bios.clock_token =
583 (struct bit_token *)&g->bios.data[offset];
584 break;
585 case TOKEN_ID_VIRT_PTRS:
586 g->bios.virt_token =
587 (struct bit_token *)&g->bios.data[offset];
588 break;
589 case TOKEN_ID_MEMORY_PTRS:
590 gm206_bios_parse_memory_ptrs(g, bit_token.data_ptr,
591 bit_token.data_version);
592 default:
593 break;
594 }
595
596 offset += bit.token_size;
597 }
598 gk20a_dbg_fn("done");
599}
600
601static u32 __gm206_bios_readbyte(struct gk20a *g, u32 offset)
602{
603 return (u32) g->bios.data[offset];
604}
605
606u8 gm206_bios_read_u8(struct gk20a *g, u32 offset)
607{
608 return (u8) __gm206_bios_readbyte(g, offset);
609}
610
611s8 gm206_bios_read_s8(struct gk20a *g, u32 offset)
612{
613 u32 val;
614 val = __gm206_bios_readbyte(g, offset);
615 val = val & 0x80 ? (val | ~0xff) : val;
616
617 return (s8) val;
618}
619
620u16 gm206_bios_read_u16(struct gk20a *g, u32 offset)
621{
622 u16 val;
623
624 val = __gm206_bios_readbyte(g, offset) |
625 (__gm206_bios_readbyte(g, offset+1) << 8);
626
627 return val;
628}
629
630u32 gm206_bios_read_u32(struct gk20a *g, u32 offset)
631{
632 u32 val;
633
634 val = __gm206_bios_readbyte(g, offset) |
635 (__gm206_bios_readbyte(g, offset+1) << 8) |
636 (__gm206_bios_readbyte(g, offset+2) << 16) |
637 (__gm206_bios_readbyte(g, offset+3) << 24);
638
639 return val;
640}
641 38
642static void upload_code(struct gk20a *g, u32 dst, 39static void upload_code(struct gk20a *g, u32 dst,
643 u8 *src, u32 size, u8 port, bool sec) 40 u8 *src, u32 size, u8 port, bool sec)
@@ -831,14 +228,13 @@ static int gm206_bios_preos(struct gk20a *g)
831 return err; 228 return err;
832} 229}
833 230
834static int gm206_bios_init(struct gk20a *g) 231int gm206_bios_init(struct gk20a *g)
835{ 232{
836 unsigned int i; 233 unsigned int i;
837 struct gk20a_platform *platform = dev_get_drvdata(g->dev); 234 struct gk20a_platform *platform = dev_get_drvdata(g->dev);
838 struct dentry *d; 235 struct dentry *d;
839 const struct firmware *bios_fw; 236 const struct firmware *bios_fw;
840 int err; 237 int err;
841 bool found = 0;
842 struct pci_dev *pdev = to_pci_dev(g->dev); 238 struct pci_dev *pdev = to_pci_dev(g->dev);
843 char rom_name[sizeof(BIOS_OVERLAY_NAME_FORMATTED)]; 239 char rom_name[sizeof(BIOS_OVERLAY_NAME_FORMATTED)];
844 240
@@ -880,24 +276,10 @@ static int gm206_bios_init(struct gk20a *g)
880 g->ops.xve.enable_shadow_rom(g); 276 g->ops.xve.enable_shadow_rom(g);
881 } 277 }
882 278
883 err = gm206_bios_parse_rom(g); 279 err = nvgpu_bios_parse_rom(g);
884 if (err) 280 if (err)
885 return err; 281 return err;
886 282
887 gk20a_dbg_info("read bios");
888 for (i = 0; i < g->bios.size - 6; i++) {
889 if (gm206_bios_rdu16(g, i) == BIT_HEADER_ID &&
890 gm206_bios_rdu32(g, i+2) == BIT_HEADER_SIGNATURE) {
891 gm206_bios_parse_bit(g, i);
892 found = true;
893 }
894 }
895
896 if (!found) {
897 gk20a_err(g->dev, "no valid VBIOS found");
898 return -EINVAL;
899 }
900
901 if (g->gpu_characteristics.vbios_version < 283 if (g->gpu_characteristics.vbios_version <
902 platform->vbios_min_version) { 284 platform->vbios_min_version) {
903 gk20a_err(g->dev, "unsupported VBIOS version %08x", 285 gk20a_err(g->dev, "unsupported VBIOS version %08x",
@@ -936,8 +318,7 @@ free_firmware:
936 return err; 318 return err;
937} 319}
938 320
939void gm206_init_bios(struct gpu_ops *gops) 321void gm206_init_bios_ops(struct gpu_ops *gops)
940{ 322{
941 gops->bios.init = gm206_bios_init; 323 gops->bios_init = gm206_bios_init;
942 gops->bios.get_perf_table_ptrs = gm206_bios_get_perf_table_ptrs;
943} 324}
diff --git a/drivers/gpu/nvgpu/gm206/bios_gm206.h b/drivers/gpu/nvgpu/gm206/bios_gm206.h
index 6fe19fb0..090c7d24 100644
--- a/drivers/gpu/nvgpu/gm206/bios_gm206.h
+++ b/drivers/gpu/nvgpu/gm206/bios_gm206.h
@@ -14,60 +14,10 @@
14#ifndef NVGPU_BIOS_GM206_H 14#ifndef NVGPU_BIOS_GM206_H
15#define NVGPU_BIOS_GM206_H 15#define NVGPU_BIOS_GM206_H
16 16
17#define PERF_PTRS_WIDTH 0x4 17struct gk20a;
18#define PERF_PTRS_WIDTH_16 0x2
19
20#define NV_PCFG 0x88000
21
22enum {
23 CLOCKS_TABLE = 2,
24 CLOCK_PROGRAMMING_TABLE,
25 FLL_TABLE,
26 VIN_TABLE,
27 FREQUENCY_CONTROLLER_TABLE
28};
29
30enum {
31 PERFORMANCE_TABLE = 0,
32 MEMORY_CLOCK_TABLE,
33 MEMORY_TWEAK_TABLE,
34 POWER_CONTROL_TABLE,
35 THERMAL_CONTROL_TABLE,
36 THERMAL_DEVICE_TABLE,
37 THERMAL_COOLERS_TABLE,
38 PERFORMANCE_SETTINGS_SCRIPT,
39 CONTINUOUS_VIRTUAL_BINNING_TABLE,
40 POWER_SENSORS_TABLE = 0xA,
41 POWER_CAPPING_TABLE = 0xB,
42 POWER_TOPOLOGY_TABLE = 0xF,
43 THERMAL_CHANNEL_TABLE = 0x12,
44 VOLTAGE_RAIL_TABLE = 26,
45 VOLTAGE_DEVICE_TABLE,
46 VOLTAGE_POLICY_TABLE,
47 LOWPOWER_TABLE,
48 LOWPOWER_GR_TABLE = 32,
49 LOWPOWER_MS_TABLE = 33,
50};
51
52enum {
53 VP_FIELD_TABLE = 0,
54 VP_FIELD_REGISTER,
55 VP_TRANSLATION_TABLE,
56};
57
58struct bit_token {
59 u8 token_id;
60 u8 data_version;
61 u16 data_size;
62 u16 data_ptr;
63} __packed;
64
65struct gpu_ops; 18struct gpu_ops;
66 19
67void gm206_init_bios(struct gpu_ops *gops); 20int gm206_bios_init(struct gk20a *g);
68u8 gm206_bios_read_u8(struct gk20a *g, u32 offset); 21void gm206_init_bios_ops(struct gpu_ops *gops);
69s8 gm206_bios_read_s8(struct gk20a *g, u32 offset);
70u16 gm206_bios_read_u16(struct gk20a *g, u32 offset);
71u32 gm206_bios_read_u32(struct gk20a *g, u32 offset);
72 22
73#endif 23#endif
diff --git a/drivers/gpu/nvgpu/gm206/hal_gm206.c b/drivers/gpu/nvgpu/gm206/hal_gm206.c
index 8ad5a397..e2b84d81 100644
--- a/drivers/gpu/nvgpu/gm206/hal_gm206.c
+++ b/drivers/gpu/nvgpu/gm206/hal_gm206.c
@@ -198,7 +198,7 @@ int gm206_init_hal(struct gk20a *g)
198#if defined(CONFIG_GK20A_CYCLE_STATS) 198#if defined(CONFIG_GK20A_CYCLE_STATS)
199 gk20a_init_css_ops(gops); 199 gk20a_init_css_ops(gops);
200#endif 200#endif
201 gm206_init_bios(gops); 201 gm206_init_bios_ops(gops);
202 switch(ver){ 202 switch(ver){
203 case GK20A_GPUID_GM206: 203 case GK20A_GPUID_GM206:
204 gops->name = "gm206"; 204 gops->name = "gm206";
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.c b/drivers/gpu/nvgpu/gp106/bios_gp106.c
deleted file mode 100644
index d3e565ca..00000000
--- a/drivers/gpu/nvgpu/gp106/bios_gp106.c
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#include "gk20a/gk20a.h"
15#include "gm206/bios_gm206.h"
16
17#include "bios_gp106.h"
18
19#include <nvgpu/hw/gp106/hw_gc6_gp106.h>
20
21static void gp106_init_xmemsel_zm_nv_reg_array(struct gk20a *g, bool *condition,
22 u32 reg, u32 stride, u32 count, u32 data_table_offset)
23{
24 u8 i;
25 u32 data, strap, index;
26
27 if (*condition) {
28
29 strap = gk20a_readl(g, gc6_sci_strap_r()) & 0xf;
30
31 index = g->bios.mem_strap_xlat_tbl_ptr ?
32 gm206_bios_read_u8(g, g->bios.mem_strap_xlat_tbl_ptr +
33 strap) : strap;
34
35 for (i = 0; i < count; i++) {
36 data = gm206_bios_read_u32(g, data_table_offset + ((i *
37 g->bios.mem_strap_data_count + index) *
38 sizeof(u32)));
39 gk20a_writel(g, reg, data);
40 reg += stride;
41 }
42 }
43}
44
45static void gp106_init_condition(struct gk20a *g, bool *condition,
46 u32 condition_id)
47{
48 struct condition_entry entry;
49
50 entry.cond_addr = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
51 sizeof(entry)*condition_id);
52 entry.cond_mask = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
53 sizeof(entry)*condition_id + 4);
54 entry.cond_compare = gm206_bios_read_u32(g, g->bios.condition_table_ptr +
55 sizeof(entry)*condition_id + 8);
56
57 if ((gk20a_readl(g, entry.cond_addr) & entry.cond_mask)
58 != entry.cond_compare) {
59 *condition = false;
60 }
61}
62
63static int gp106_execute_script(struct gk20a *g, u32 offset)
64{
65 u8 opcode;
66 u32 ip;
67 u32 operand[8];
68 bool condition, end;
69 int status = 0;
70
71 ip = offset;
72 condition = true;
73 end = false;
74
75 while (!end) {
76
77 opcode = gm206_bios_read_u8(g, ip++);
78
79 switch (opcode) {
80
81 case INIT_XMEMSEL_ZM_NV_REG_ARRAY:
82 operand[0] = gm206_bios_read_u32(g, ip);
83 operand[1] = gm206_bios_read_u8(g, ip+4);
84 operand[2] = gm206_bios_read_u8(g, ip+5);
85 ip += 6;
86
87 gp106_init_xmemsel_zm_nv_reg_array(g, &condition,
88 operand[0], operand[1], operand[2], ip);
89 ip += operand[2] * sizeof(u32) *
90 g->bios.mem_strap_data_count;
91 break;
92
93 case INIT_CONDITION:
94 operand[0] = gm206_bios_read_u8(g, ip);
95 ip++;
96
97 gp106_init_condition(g, &condition, operand[0]);
98 break;
99
100 case INIT_RESUME:
101 condition = true;
102 break;
103
104 case INIT_DONE:
105 end = true;
106 break;
107
108 default:
109 gk20a_err(dev_from_gk20a(g), "opcode: 0x%02x", opcode);
110 end = true;
111 status = -EINVAL;
112 break;
113 }
114 }
115
116 return status;
117}
118
119void gp106_init_bios(struct gpu_ops *gops)
120{
121 gm206_init_bios(gops);
122 gops->bios.execute_script = gp106_execute_script;
123}
diff --git a/drivers/gpu/nvgpu/gp106/bios_gp106.h b/drivers/gpu/nvgpu/gp106/bios_gp106.h
deleted file mode 100644
index f47d11ca..00000000
--- a/drivers/gpu/nvgpu/gp106/bios_gp106.h
+++ /dev/null
@@ -1,31 +0,0 @@
1/*
2 * Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 */
13
14#ifndef NVGPU_BIOS_GP106_H
15#define NVGPU_BIOS_GP106_H
16
17struct gpu_ops;
18
19#define INIT_DONE 0x71
20#define INIT_RESUME 0x72
21#define INIT_CONDITION 0x75
22#define INIT_XMEMSEL_ZM_NV_REG_ARRAY 0x8f
23
24struct condition_entry {
25 u32 cond_addr;
26 u32 cond_mask;
27 u32 cond_compare;
28} __packed;
29
30void gp106_init_bios(struct gpu_ops *gops);
31#endif
diff --git a/drivers/gpu/nvgpu/gp106/hal_gp106.c b/drivers/gpu/nvgpu/gp106/hal_gp106.c
index e3874c06..cece5dd6 100644
--- a/drivers/gpu/nvgpu/gp106/hal_gp106.c
+++ b/drivers/gpu/nvgpu/gp106/hal_gp106.c
@@ -39,7 +39,7 @@
39 39
40#include "gp106/clk_gp106.h" 40#include "gp106/clk_gp106.h"
41#include "gp106/clk_arb_gp106.h" 41#include "gp106/clk_arb_gp106.h"
42#include "gp106/bios_gp106.h" 42#include "gm206/bios_gm206.h"
43#include "gp106/therm_gp106.h" 43#include "gp106/therm_gp106.h"
44#include "gp106/xve_gp106.h" 44#include "gp106/xve_gp106.h"
45#include "gp106/fifo_gp106.h" 45#include "gp106/fifo_gp106.h"
@@ -245,7 +245,7 @@ int gp106_init_hal(struct gk20a *g)
245#if defined(CONFIG_GK20A_CYCLE_STATS) 245#if defined(CONFIG_GK20A_CYCLE_STATS)
246 gk20a_init_css_ops(gops); 246 gk20a_init_css_ops(gops);
247#endif 247#endif
248 gp106_init_bios(gops); 248 gm206_init_bios_ops(gops);
249 gp106_init_therm_ops(gops); 249 gp106_init_therm_ops(gops);
250 gp106_init_xve_ops(gops); 250 gp106_init_xve_ops(gops);
251 251
diff --git a/drivers/gpu/nvgpu/include/bios.h b/drivers/gpu/nvgpu/include/nvgpu/bios.h
index bcb24343..c6465313 100644
--- a/drivers/gpu/nvgpu/include/bios.h
+++ b/drivers/gpu/nvgpu/include/nvgpu/bios.h
@@ -1,7 +1,5 @@
1/* 1/*
2 * vbios tables support 2 * Copyright (c) 2014-2017, NVIDIA CORPORATION. All rights reserved.
3 *
4 * Copyright (c) 2016-2017, NVIDIA CORPORATION. All rights reserved.
5 * 3 *
6 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -13,10 +11,58 @@
13 * more details. 11 * more details.
14 */ 12 */
15 13
16#ifndef NVGPU_INCLUDE_BIOS_H 14#ifndef NVGPU_BIOS_H
17#define NVGPU_INCLUDE_BIOS_H 15#define NVGPU_BIOS_H
16
17#include <linux/types.h>
18
19struct gk20a;
20
21#define PERF_PTRS_WIDTH 0x4
22#define PERF_PTRS_WIDTH_16 0x2
23
24enum {
25 CLOCKS_TABLE = 2,
26 CLOCK_PROGRAMMING_TABLE,
27 FLL_TABLE,
28 VIN_TABLE,
29 FREQUENCY_CONTROLLER_TABLE
30};
18 31
19#include "gk20a/gk20a.h" 32enum {
33 PERFORMANCE_TABLE = 0,
34 MEMORY_CLOCK_TABLE,
35 MEMORY_TWEAK_TABLE,
36 POWER_CONTROL_TABLE,
37 THERMAL_CONTROL_TABLE,
38 THERMAL_DEVICE_TABLE,
39 THERMAL_COOLERS_TABLE,
40 PERFORMANCE_SETTINGS_SCRIPT,
41 CONTINUOUS_VIRTUAL_BINNING_TABLE,
42 POWER_SENSORS_TABLE = 0xA,
43 POWER_CAPPING_TABLE = 0xB,
44 POWER_TOPOLOGY_TABLE = 0xF,
45 THERMAL_CHANNEL_TABLE = 0x12,
46 VOLTAGE_RAIL_TABLE = 26,
47 VOLTAGE_DEVICE_TABLE,
48 VOLTAGE_POLICY_TABLE,
49 LOWPOWER_TABLE,
50 LOWPOWER_GR_TABLE = 32,
51 LOWPOWER_MS_TABLE = 33,
52};
53
54enum {
55 VP_FIELD_TABLE = 0,
56 VP_FIELD_REGISTER,
57 VP_TRANSLATION_TABLE,
58};
59
60struct bit_token {
61 u8 token_id;
62 u8 data_version;
63 u16 data_size;
64 u16 data_ptr;
65} __packed;
20 66
21#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT) 67#define BIOS_GET_FIELD(value, name) ((value & name##_MASK) >> name##_SHIFT)
22 68
@@ -988,5 +1034,13 @@ struct nvgpu_bios_lpwr_gr_table_1x_entry {
988 1034
989#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4) 1035#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_MASK GENMASK(4, 4)
990#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4 1036#define NV_VBIOS_LPWR_GR_FEATURE_MASK_GR_RPPG_SHIFT 4
1037int nvgpu_bios_parse_rom(struct gk20a *g);
1038u8 nvgpu_bios_read_u8(struct gk20a *g, u32 offset);
1039s8 nvgpu_bios_read_s8(struct gk20a *g, u32 offset);
1040u16 nvgpu_bios_read_u16(struct gk20a *g, u32 offset);
1041u32 nvgpu_bios_read_u32(struct gk20a *g, u32 offset);
1042void *nvgpu_bios_get_perf_table_ptrs(struct gk20a *g,
1043 struct bit_token *ptoken, u8 table_id);
1044int nvgpu_bios_execute_script(struct gk20a *g, u32 offset);
991 1045
992#endif 1046#endif
diff --git a/drivers/gpu/nvgpu/lpwr/lpwr.c b/drivers/gpu/nvgpu/lpwr/lpwr.c
index 1dc37cd2..9636891b 100644
--- a/drivers/gpu/nvgpu/lpwr/lpwr.c
+++ b/drivers/gpu/nvgpu/lpwr/lpwr.c
@@ -11,12 +11,13 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "gk20a/pmu_gk20a.h" 17#include "gk20a/pmu_gk20a.h"
16#include "gp106/pmu_gp106.h" 18#include "gp106/pmu_gp106.h"
17#include "gm206/bios_gm206.h" 19#include "gm206/bios_gm206.h"
18#include "pstate/pstate.h" 20#include "pstate/pstate.h"
19#include "include/bios.h"
20#include "perf/perf.h" 21#include "perf/perf.h"
21#include "lpwr.h" 22#include "lpwr.h"
22 23
@@ -30,13 +31,10 @@ static int get_lpwr_idx_table(struct gk20a *g)
30 struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 }; 31 struct nvgpu_bios_lpwr_idx_table_1x_header header = { 0 };
31 struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 }; 32 struct nvgpu_bios_lpwr_idx_table_1x_entry entry = { 0 };
32 33
33 if (g->ops.bios.get_perf_table_ptrs) { 34 lpwr_idx_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
34 lpwr_idx_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, 35 g->bios.perf_token, LOWPOWER_TABLE);
35 g->bios.perf_token, LOWPOWER_TABLE); 36 if (lpwr_idx_table_ptr == NULL)
36 if (lpwr_idx_table_ptr == NULL) 37 return -EINVAL;
37 return -EINVAL;
38 } else
39 return -EINVAL;
40 38
41 memcpy(&header, lpwr_idx_table_ptr, 39 memcpy(&header, lpwr_idx_table_ptr,
42 sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header)); 40 sizeof(struct nvgpu_bios_lpwr_idx_table_1x_header));
@@ -75,13 +73,10 @@ static int get_lpwr_gr_table(struct gk20a *g)
75 struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 }; 73 struct nvgpu_bios_lpwr_gr_table_1x_header header = { 0 };
76 struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 }; 74 struct nvgpu_bios_lpwr_gr_table_1x_entry entry = { 0 };
77 75
78 if (g->ops.bios.get_perf_table_ptrs) { 76 lpwr_gr_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
79 lpwr_gr_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, 77 g->bios.perf_token, LOWPOWER_GR_TABLE);
80 g->bios.perf_token, LOWPOWER_GR_TABLE); 78 if (lpwr_gr_table_ptr == NULL)
81 if (lpwr_gr_table_ptr == NULL) 79 return -EINVAL;
82 return -EINVAL;
83 } else
84 return -EINVAL;
85 80
86 memcpy(&header, lpwr_gr_table_ptr, 81 memcpy(&header, lpwr_gr_table_ptr,
87 sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header)); 82 sizeof(struct nvgpu_bios_lpwr_gr_table_1x_header));
@@ -122,13 +117,10 @@ static int get_lpwr_ms_table(struct gk20a *g)
122 struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 }; 117 struct nvgpu_bios_lpwr_ms_table_1x_header header = { 0 };
123 struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 }; 118 struct nvgpu_bios_lpwr_ms_table_1x_entry entry = { 0 };
124 119
125 if (g->ops.bios.get_perf_table_ptrs) { 120 lpwr_ms_table_ptr = (u32 *)nvgpu_bios_get_perf_table_ptrs(g,
126 lpwr_ms_table_ptr = (u32 *)g->ops.bios.get_perf_table_ptrs(g, 121 g->bios.perf_token, LOWPOWER_MS_TABLE);
127 g->bios.perf_token, LOWPOWER_MS_TABLE); 122 if (lpwr_ms_table_ptr == NULL)
128 if (lpwr_ms_table_ptr == NULL) 123 return -EINVAL;
129 return -EINVAL;
130 } else
131 return -EINVAL;
132 124
133 memcpy(&header, lpwr_ms_table_ptr, 125 memcpy(&header, lpwr_ms_table_ptr,
134 sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header)); 126 sizeof(struct nvgpu_bios_lpwr_ms_table_1x_header));
diff --git a/drivers/gpu/nvgpu/lpwr/rppg.c b/drivers/gpu/nvgpu/lpwr/rppg.c
index 3cc12840..e90fd7f9 100644
--- a/drivers/gpu/nvgpu/lpwr/rppg.c
+++ b/drivers/gpu/nvgpu/lpwr/rppg.c
@@ -16,8 +16,6 @@
16#include "gp106/pmu_gp106.h" 16#include "gp106/pmu_gp106.h"
17#include "gm206/bios_gm206.h" 17#include "gm206/bios_gm206.h"
18#include "pstate/pstate.h" 18#include "pstate/pstate.h"
19#include "include/bios.h"
20#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
21 19
22static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg, 20static void pmu_handle_rppg_init_msg(struct gk20a *g, struct pmu_msg *msg,
23 void *param, u32 handle, u32 status) 21 void *param, u32 handle, u32 status)
diff --git a/drivers/gpu/nvgpu/perf/vfe_equ.c b/drivers/gpu/nvgpu/perf/vfe_equ.c
index 3a5b9f45..f8a79a22 100644
--- a/drivers/gpu/nvgpu/perf/vfe_equ.c
+++ b/drivers/gpu/nvgpu/perf/vfe_equ.c
@@ -11,13 +11,13 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "perf.h" 17#include "perf.h"
16#include "vfe_equ.h" 18#include "vfe_equ.h"
17#include "include/bios.h"
18#include "boardobj/boardobjgrp.h" 19#include "boardobj/boardobjgrp.h"
19#include "boardobj/boardobjgrp_e255.h" 20#include "boardobj/boardobjgrp_e255.h"
20#include "gm206/bios_gm206.h"
21#include "ctrl/ctrlclk.h" 21#include "ctrl/ctrlclk.h"
22#include "ctrl/ctrlvolt.h" 22#include "ctrl/ctrlvolt.h"
23#include "gk20a/pmu_gk20a.h" 23#include "gk20a/pmu_gk20a.h"
@@ -147,10 +147,7 @@ static u32 devinit_get_vfe_equ_table(struct gk20a *g,
147 147
148 gk20a_dbg_info(""); 148 gk20a_dbg_info("");
149 149
150 if (!g->ops.bios.get_perf_table_ptrs) 150 vfeequs_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
151 return -EINVAL;
152
153 vfeequs_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
154 g->bios.perf_token, 151 g->bios.perf_token,
155 CONTINUOUS_VIRTUAL_BINNING_TABLE); 152 CONTINUOUS_VIRTUAL_BINNING_TABLE);
156 153
diff --git a/drivers/gpu/nvgpu/perf/vfe_var.c b/drivers/gpu/nvgpu/perf/vfe_var.c
index d1e1d76c..7170f502 100644
--- a/drivers/gpu/nvgpu/perf/vfe_var.c
+++ b/drivers/gpu/nvgpu/perf/vfe_var.c
@@ -11,13 +11,13 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "perf.h" 17#include "perf.h"
16#include "vfe_var.h" 18#include "vfe_var.h"
17#include "include/bios.h"
18#include "boardobj/boardobjgrp.h" 19#include "boardobj/boardobjgrp.h"
19#include "boardobj/boardobjgrp_e32.h" 20#include "boardobj/boardobjgrp_e32.h"
20#include "gm206/bios_gm206.h"
21#include "ctrl/ctrlclk.h" 21#include "ctrl/ctrlclk.h"
22#include "ctrl/ctrlvolt.h" 22#include "ctrl/ctrlvolt.h"
23#include "gk20a/pmu_gk20a.h" 23#include "gk20a/pmu_gk20a.h"
@@ -179,17 +179,14 @@ u32 dev_init_get_vfield_info(struct gk20a *g,
179 u8 *psegmentcount = NULL; 179 u8 *psegmentcount = NULL;
180 u32 status = 0; 180 u32 status = 0;
181 181
182 if (!g->ops.bios.get_perf_table_ptrs) 182 vfieldregtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
183 return -EINVAL;
184
185 vfieldregtableptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
186 g->bios.virt_token, VP_FIELD_REGISTER); 183 g->bios.virt_token, VP_FIELD_REGISTER);
187 if (vfieldregtableptr == NULL) { 184 if (vfieldregtableptr == NULL) {
188 status = -EINVAL; 185 status = -EINVAL;
189 goto done; 186 goto done;
190 } 187 }
191 188
192 vfieldtableptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, 189 vfieldtableptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
193 g->bios.virt_token, VP_FIELD_TABLE); 190 g->bios.virt_token, VP_FIELD_TABLE);
194 if (vfieldtableptr == NULL) { 191 if (vfieldtableptr == NULL) {
195 status = -EINVAL; 192 status = -EINVAL;
@@ -864,12 +861,7 @@ static u32 devinit_get_vfe_var_table(struct gk20a *g,
864 861
865 gk20a_dbg_info(""); 862 gk20a_dbg_info("");
866 863
867 if (!g->ops.bios.get_perf_table_ptrs) { 864 vfevars_tbl_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
868 status = -EINVAL;
869 goto done;
870 }
871
872 vfevars_tbl_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
873 g->bios.perf_token, 865 g->bios.perf_token,
874 CONTINUOUS_VIRTUAL_BINNING_TABLE); 866 CONTINUOUS_VIRTUAL_BINNING_TABLE);
875 if (vfevars_tbl_ptr == NULL) { 867 if (vfevars_tbl_ptr == NULL) {
diff --git a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
index 53241734..28fe943e 100644
--- a/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
+++ b/drivers/gpu/nvgpu/pmgr/pmgrpmu.c
@@ -13,7 +13,6 @@
13 13
14#include "gk20a/gk20a.h" 14#include "gk20a/gk20a.h"
15#include "pwrdev.h" 15#include "pwrdev.h"
16#include "include/bios.h"
17#include "boardobj/boardobjgrp.h" 16#include "boardobj/boardobjgrp.h"
18#include "boardobj/boardobjgrp_e32.h" 17#include "boardobj/boardobjgrp_e32.h"
19#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> 18#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
diff --git a/drivers/gpu/nvgpu/pmgr/pwrdev.c b/drivers/gpu/nvgpu/pmgr/pwrdev.c
index e831126b..0f87ad26 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrdev.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrdev.c
@@ -11,9 +11,10 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "pwrdev.h" 17#include "pwrdev.h"
16#include "include/bios.h"
17#include "boardobj/boardobjgrp.h" 18#include "boardobj/boardobjgrp.h"
18#include "boardobj/boardobjgrp_e32.h" 19#include "boardobj/boardobjgrp_e32.h"
19#include "gm206/bios_gm206.h" 20#include "gm206/bios_gm206.h"
@@ -138,10 +139,7 @@ static u32 devinit_get_pwr_device_table(struct gk20a *g,
138 139
139 gk20a_dbg_info(""); 140 gk20a_dbg_info("");
140 141
141 if (!g->ops.bios.get_perf_table_ptrs) 142 pwr_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
142 return -EINVAL;
143
144 pwr_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
145 g->bios.perf_token, POWER_SENSORS_TABLE); 143 g->bios.perf_token, POWER_SENSORS_TABLE);
146 if (pwr_device_table_ptr == NULL) { 144 if (pwr_device_table_ptr == NULL) {
147 status = -EINVAL; 145 status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
index ab2460eb..685aa71a 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrmonitor.c
@@ -11,9 +11,10 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "pwrdev.h" 17#include "pwrdev.h"
16#include "include/bios.h"
17#include "boardobj/boardobjgrp.h" 18#include "boardobj/boardobjgrp.h"
18#include "boardobj/boardobjgrp_e32.h" 19#include "boardobj/boardobjgrp_e32.h"
19#include "gm206/bios_gm206.h" 20#include "gm206/bios_gm206.h"
@@ -185,10 +186,7 @@ static u32 devinit_get_pwr_topology_table(struct gk20a *g,
185 186
186 gk20a_dbg_info(""); 187 gk20a_dbg_info("");
187 188
188 if (!g->ops.bios.get_perf_table_ptrs) 189 pwr_topology_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
189 return -EINVAL;
190
191 pwr_topology_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
192 g->bios.perf_token, POWER_TOPOLOGY_TABLE); 190 g->bios.perf_token, POWER_TOPOLOGY_TABLE);
193 if (pwr_topology_table_ptr == NULL) { 191 if (pwr_topology_table_ptr == NULL) {
194 status = -EINVAL; 192 status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
index d19f9a1c..4c007337 100644
--- a/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
+++ b/drivers/gpu/nvgpu/pmgr/pwrpolicy.c
@@ -11,9 +11,10 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "pwrpolicy.h" 17#include "pwrpolicy.h"
16#include "include/bios.h"
17#include "boardobj/boardobjgrp.h" 18#include "boardobj/boardobjgrp.h"
18#include "boardobj/boardobjgrp_e32.h" 19#include "boardobj/boardobjgrp_e32.h"
19#include "gm206/bios_gm206.h" 20#include "gm206/bios_gm206.h"
@@ -521,10 +522,7 @@ static u32 devinit_get_pwr_policy_table(struct gk20a *g,
521 522
522 gk20a_dbg_info(""); 523 gk20a_dbg_info("");
523 524
524 if (!g->ops.bios.get_perf_table_ptrs) 525 ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
525 return -EINVAL;
526
527 ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
528 g->bios.perf_token, POWER_CAPPING_TABLE); 526 g->bios.perf_token, POWER_CAPPING_TABLE);
529 if (ptr == NULL) { 527 if (ptr == NULL) {
530 status = -EINVAL; 528 status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/pstate/pstate.c b/drivers/gpu/nvgpu/pstate/pstate.c
index 82e809bb..feb8cca8 100644
--- a/drivers/gpu/nvgpu/pstate/pstate.c
+++ b/drivers/gpu/nvgpu/pstate/pstate.c
@@ -13,11 +13,12 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#include <nvgpu/bios.h>
17
16#include "gk20a/gk20a.h" 18#include "gk20a/gk20a.h"
17#include "clk/clk.h" 19#include "clk/clk.h"
18#include "perf/perf.h" 20#include "perf/perf.h"
19#include "pmgr/pmgr.h" 21#include "pmgr/pmgr.h"
20#include "include/bios.h"
21#include "pstate/pstate.h" 22#include "pstate/pstate.h"
22#include "therm/thrm.h" 23#include "therm/thrm.h"
23 24
@@ -342,11 +343,9 @@ static int pstate_sw_setup(struct gk20a *g)
342 goto done; 343 goto done;
343 } 344 }
344 345
345 if (g->ops.bios.get_perf_table_ptrs) { 346 hdr = (struct vbios_pstate_header_5x *)
346 hdr = (struct vbios_pstate_header_5x *) 347 nvgpu_bios_get_perf_table_ptrs(g,
347 g->ops.bios.get_perf_table_ptrs(g, 348 g->bios.perf_token, PERFORMANCE_TABLE);
348 g->bios.perf_token, PERFORMANCE_TABLE);
349 }
350 349
351 if (!hdr) { 350 if (!hdr) {
352 gk20a_err(dev_from_gk20a(g), 351 gk20a_err(dev_from_gk20a(g),
diff --git a/drivers/gpu/nvgpu/therm/thrmchannel.c b/drivers/gpu/nvgpu/therm/thrmchannel.c
index f253a196..a09a4599 100644
--- a/drivers/gpu/nvgpu/therm/thrmchannel.c
+++ b/drivers/gpu/nvgpu/therm/thrmchannel.c
@@ -11,9 +11,10 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "thrmchannel.h" 17#include "thrmchannel.h"
16#include "include/bios.h"
17#include "boardobj/boardobjgrp.h" 18#include "boardobj/boardobjgrp.h"
18#include "boardobj/boardobjgrp_e32.h" 19#include "boardobj/boardobjgrp_e32.h"
19#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> 20#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
@@ -130,10 +131,7 @@ static u32 devinit_get_therm_channel_table(struct gk20a *g,
130 131
131 gk20a_dbg_info(""); 132 gk20a_dbg_info("");
132 133
133 if (!g->ops.bios.get_perf_table_ptrs) 134 therm_channel_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
134 return -EINVAL;
135
136 therm_channel_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
137 g->bios.perf_token, THERMAL_CHANNEL_TABLE); 135 g->bios.perf_token, THERMAL_CHANNEL_TABLE);
138 if (therm_channel_table_ptr == NULL) { 136 if (therm_channel_table_ptr == NULL) {
139 status = -EINVAL; 137 status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/therm/thrmdev.c b/drivers/gpu/nvgpu/therm/thrmdev.c
index 3ff199e7..199343e0 100644
--- a/drivers/gpu/nvgpu/therm/thrmdev.c
+++ b/drivers/gpu/nvgpu/therm/thrmdev.c
@@ -11,9 +11,10 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "thrmdev.h" 17#include "thrmdev.h"
16#include "include/bios.h"
17#include "boardobj/boardobjgrp.h" 18#include "boardobj/boardobjgrp.h"
18#include "boardobj/boardobjgrp_e32.h" 19#include "boardobj/boardobjgrp_e32.h"
19#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> 20#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
@@ -80,10 +81,7 @@ static u32 devinit_get_therm_device_table(struct gk20a *g,
80 81
81 gk20a_dbg_info(""); 82 gk20a_dbg_info("");
82 83
83 if (!g->ops.bios.get_perf_table_ptrs) 84 therm_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
84 return -EINVAL;
85
86 therm_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g,
87 g->bios.perf_token, THERMAL_DEVICE_TABLE); 85 g->bios.perf_token, THERMAL_DEVICE_TABLE);
88 if (therm_device_table_ptr == NULL) { 86 if (therm_device_table_ptr == NULL) {
89 status = -EINVAL; 87 status = -EINVAL;
diff --git a/drivers/gpu/nvgpu/therm/thrmpmu.c b/drivers/gpu/nvgpu/therm/thrmpmu.c
index a06d3b92..50df55c0 100644
--- a/drivers/gpu/nvgpu/therm/thrmpmu.c
+++ b/drivers/gpu/nvgpu/therm/thrmpmu.c
@@ -12,7 +12,6 @@
12 */ 12 */
13 13
14#include "gk20a/gk20a.h" 14#include "gk20a/gk20a.h"
15#include "include/bios.h"
16#include "boardobj/boardobjgrp.h" 15#include "boardobj/boardobjgrp.h"
17#include "boardobj/boardobjgrp_e32.h" 16#include "boardobj/boardobjgrp_e32.h"
18#include "thrmpmu.h" 17#include "thrmpmu.h"
diff --git a/drivers/gpu/nvgpu/volt/volt_dev.c b/drivers/gpu/nvgpu/volt/volt_dev.c
index ebc140ef..4807f023 100644
--- a/drivers/gpu/nvgpu/volt/volt_dev.c
+++ b/drivers/gpu/nvgpu/volt/volt_dev.c
@@ -14,17 +14,17 @@
14#include <linux/sort.h> 14#include <linux/sort.h>
15 15
16#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
17#include "include/bios.h"
18#include "boardobj/boardobjgrp.h" 17#include "boardobj/boardobjgrp.h"
19#include "boardobj/boardobjgrp_e32.h" 18#include "boardobj/boardobjgrp_e32.h"
20#include "gm206/bios_gm206.h" 19#include "gm206/bios_gm206.h"
21#include "ctrl/ctrlvolt.h" 20#include "ctrl/ctrlvolt.h"
22#include "gk20a/pmu_gk20a.h" 21#include "gk20a/pmu_gk20a.h"
23 22
24#include "include/bios.h"
25#include "volt.h" 23#include "volt.h"
26#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> 24#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
27 25
26#include <nvgpu/bios.h>
27
28#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0 28#define VOLT_DEV_PWM_VOLTAGE_STEPS_INVALID 0
29#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1 29#define VOLT_DEV_PWM_VOLTAGE_STEPS_DEFAULT 1
30 30
@@ -363,14 +363,9 @@ static u32 volt_get_volt_devices_table(struct gk20a *g,
363 u8 entry_idx; 363 u8 entry_idx;
364 u8 *entry_offset; 364 u8 *entry_offset;
365 365
366 if (g->ops.bios.get_perf_table_ptrs) { 366 volt_device_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
367 volt_device_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, 367 g->bios.perf_token, VOLTAGE_DEVICE_TABLE);
368 g->bios.perf_token, VOLTAGE_DEVICE_TABLE); 368 if (volt_device_table_ptr == NULL) {
369 if (volt_device_table_ptr == NULL) {
370 status = -EINVAL;
371 goto done;
372 }
373 } else {
374 status = -EINVAL; 369 status = -EINVAL;
375 goto done; 370 goto done;
376 } 371 }
diff --git a/drivers/gpu/nvgpu/volt/volt_pmu.c b/drivers/gpu/nvgpu/volt/volt_pmu.c
index 488e67a3..f8167000 100644
--- a/drivers/gpu/nvgpu/volt/volt_pmu.c
+++ b/drivers/gpu/nvgpu/volt/volt_pmu.c
@@ -12,7 +12,6 @@
12 */ 12 */
13 13
14#include "gk20a/gk20a.h" 14#include "gk20a/gk20a.h"
15#include "include/bios.h"
16#include "boardobj/boardobjgrp.h" 15#include "boardobj/boardobjgrp.h"
17#include "boardobj/boardobjgrp_e32.h" 16#include "boardobj/boardobjgrp_e32.h"
18#include "gm206/bios_gm206.h" 17#include "gm206/bios_gm206.h"
@@ -20,7 +19,6 @@
20#include "ctrl/ctrlperf.h" 19#include "ctrl/ctrlperf.h"
21#include "gk20a/pmu_gk20a.h" 20#include "gk20a/pmu_gk20a.h"
22 21
23#include "include/bios.h"
24#include "volt.h" 22#include "volt.h"
25#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h> 23#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
26 24
diff --git a/drivers/gpu/nvgpu/volt/volt_policy.c b/drivers/gpu/nvgpu/volt/volt_policy.c
index e943e771..239b908e 100644
--- a/drivers/gpu/nvgpu/volt/volt_policy.c
+++ b/drivers/gpu/nvgpu/volt/volt_policy.c
@@ -11,16 +11,15 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "include/bios.h"
16#include "boardobj/boardobjgrp.h" 17#include "boardobj/boardobjgrp.h"
17#include "boardobj/boardobjgrp_e32.h" 18#include "boardobj/boardobjgrp_e32.h"
18#include "gm206/bios_gm206.h" 19#include "gm206/bios_gm206.h"
19#include "ctrl/ctrlvolt.h" 20#include "ctrl/ctrlvolt.h"
20#include "gk20a/pmu_gk20a.h" 21#include "gk20a/pmu_gk20a.h"
21 22
22#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
23#include "include/bios.h"
24#include "volt.h" 23#include "volt.h"
25 24
26static u32 volt_policy_pmu_data_init_super(struct gk20a *g, 25static u32 volt_policy_pmu_data_init_super(struct gk20a *g,
@@ -170,15 +169,10 @@ static u32 volt_get_volt_policy_table(struct gk20a *g,
170 struct voltage_policy_split_rail split_rail; 169 struct voltage_policy_split_rail split_rail;
171 } policy_type_data; 170 } policy_type_data;
172 171
173 if (g->ops.bios.get_perf_table_ptrs) { 172 voltage_policy_table_ptr =
174 voltage_policy_table_ptr = 173 (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
175 (u8 *)g->ops.bios.get_perf_table_ptrs(g, 174 g->bios.perf_token, VOLTAGE_POLICY_TABLE);
176 g->bios.perf_token, VOLTAGE_POLICY_TABLE); 175 if (voltage_policy_table_ptr == NULL) {
177 if (voltage_policy_table_ptr == NULL) {
178 status = -EINVAL;
179 goto done;
180 }
181 } else {
182 status = -EINVAL; 176 status = -EINVAL;
183 goto done; 177 goto done;
184 } 178 }
diff --git a/drivers/gpu/nvgpu/volt/volt_rail.c b/drivers/gpu/nvgpu/volt/volt_rail.c
index 6d606228..aaad86a5 100644
--- a/drivers/gpu/nvgpu/volt/volt_rail.c
+++ b/drivers/gpu/nvgpu/volt/volt_rail.c
@@ -11,16 +11,15 @@
11 * more details. 11 * more details.
12 */ 12 */
13 13
14#include <nvgpu/bios.h>
15
14#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
15#include "include/bios.h"
16#include "boardobj/boardobjgrp.h" 17#include "boardobj/boardobjgrp.h"
17#include "boardobj/boardobjgrp_e32.h" 18#include "boardobj/boardobjgrp_e32.h"
18#include "gm206/bios_gm206.h" 19#include "gm206/bios_gm206.h"
19#include "ctrl/ctrlvolt.h" 20#include "ctrl/ctrlvolt.h"
20#include "gk20a/pmu_gk20a.h" 21#include "gk20a/pmu_gk20a.h"
21 22
22#include <nvgpu/pmuif/nvgpu_gpmu_cmdif.h>
23#include "include/bios.h"
24#include "volt.h" 23#include "volt.h"
25 24
26u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain) 25u8 volt_rail_volt_domain_convert_to_idx(struct gk20a *g, u8 volt_domain)
@@ -241,14 +240,9 @@ static u32 volt_get_volt_rail_table(struct gk20a *g,
241 struct voltage_rail volt_rail; 240 struct voltage_rail volt_rail;
242 } rail_type_data; 241 } rail_type_data;
243 242
244 if (g->ops.bios.get_perf_table_ptrs) { 243 volt_rail_table_ptr = (u8 *)nvgpu_bios_get_perf_table_ptrs(g,
245 volt_rail_table_ptr = (u8 *)g->ops.bios.get_perf_table_ptrs(g, 244 g->bios.perf_token, VOLTAGE_RAIL_TABLE);
246 g->bios.perf_token, VOLTAGE_RAIL_TABLE); 245 if (volt_rail_table_ptr == NULL) {
247 if (volt_rail_table_ptr == NULL) {
248 status = -EINVAL;
249 goto done;
250 }
251 } else {
252 status = -EINVAL; 246 status = -EINVAL;
253 goto done; 247 goto done;
254 } 248 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-02 20:59:16 -0400