diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-03-01 18:24:17 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-20 19:39:49 -0400 |
commit | 50f371f891c889c782187036c31132fa94c573ac (patch) | |
tree | bb4be977c782d5a3c2db1e39c0690117871b43dd /drivers/gpu | |
parent | 38d90b60922e6de6b795694d3e3cdf66d4ddae5f (diff) |
gpu: nvgpu: add fifo ops for intr_0_error_mask
This change is required to support t19x mmu fault
Change-Id: I3953dcf02c71ace606ba81896e56ea98683eb2ca
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: http://git-master/r/1313482
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu')
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | 50 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | 3 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gk20a/gk20a.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 1 |
4 files changed, 41 insertions, 14 deletions
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c index edc0f13d..b52e5310 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c | |||
@@ -725,6 +725,33 @@ clean_up_runlist: | |||
725 | 725 | ||
726 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 | 726 | #define GRFIFO_TIMEOUT_CHECK_PERIOD_US 100000 |
727 | 727 | ||
728 | u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g) | ||
729 | { | ||
730 | u32 intr_0_error_mask = | ||
731 | fifo_intr_0_bind_error_pending_f() | | ||
732 | fifo_intr_0_sched_error_pending_f() | | ||
733 | fifo_intr_0_chsw_error_pending_f() | | ||
734 | fifo_intr_0_fb_flush_timeout_pending_f() | | ||
735 | fifo_intr_0_dropped_mmu_fault_pending_f() | | ||
736 | fifo_intr_0_mmu_fault_pending_f() | | ||
737 | fifo_intr_0_lb_error_pending_f() | | ||
738 | fifo_intr_0_pio_error_pending_f(); | ||
739 | |||
740 | return intr_0_error_mask; | ||
741 | } | ||
742 | |||
743 | static u32 gk20a_fifo_intr_0_en_mask(struct gk20a *g) | ||
744 | { | ||
745 | u32 intr_0_en_mask; | ||
746 | |||
747 | intr_0_en_mask = g->ops.fifo.intr_0_error_mask(g); | ||
748 | |||
749 | intr_0_en_mask |= fifo_intr_0_runlist_event_pending_f() | | ||
750 | fifo_intr_0_pbdma_intr_pending_f(); | ||
751 | |||
752 | return intr_0_en_mask; | ||
753 | } | ||
754 | |||
728 | int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | 755 | int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) |
729 | { | 756 | { |
730 | u32 intr_stall; | 757 | u32 intr_stall; |
@@ -756,7 +783,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g) | |||
756 | 783 | ||
757 | /* enable pfifo interrupt */ | 784 | /* enable pfifo interrupt */ |
758 | gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); | 785 | gk20a_writel(g, fifo_intr_0_r(), 0xFFFFFFFF); |
759 | gk20a_writel(g, fifo_intr_en_0_r(), 0x7FFFFFFF); | 786 | gk20a_writel(g, fifo_intr_en_0_r(), gk20a_fifo_intr_0_en_mask(g)); |
760 | gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); | 787 | gk20a_writel(g, fifo_intr_en_1_r(), 0x80000000); |
761 | 788 | ||
762 | /* enable pbdma interrupt */ | 789 | /* enable pbdma interrupt */ |
@@ -2128,8 +2155,9 @@ static u32 fifo_error_isr(struct gk20a *g, u32 fifo_intr) | |||
2128 | } | 2155 | } |
2129 | 2156 | ||
2130 | if (fifo_intr & fifo_intr_0_mmu_fault_pending_f()) { | 2157 | if (fifo_intr & fifo_intr_0_mmu_fault_pending_f()) { |
2131 | print_channel_reset_log = | 2158 | print_channel_reset_log |= |
2132 | gk20a_fifo_handle_mmu_fault(g, 0, ~(u32)0, false); | 2159 | gk20a_fifo_handle_mmu_fault(g, 0, |
2160 | ~(u32)0, false); | ||
2133 | handled |= fifo_intr_0_mmu_fault_pending_f(); | 2161 | handled |= fifo_intr_0_mmu_fault_pending_f(); |
2134 | } | 2162 | } |
2135 | 2163 | ||
@@ -2355,18 +2383,11 @@ static u32 fifo_pbdma_isr(struct gk20a *g, u32 fifo_intr) | |||
2355 | 2383 | ||
2356 | void gk20a_fifo_isr(struct gk20a *g) | 2384 | void gk20a_fifo_isr(struct gk20a *g) |
2357 | { | 2385 | { |
2358 | u32 error_intr_mask = | 2386 | u32 error_intr_mask; |
2359 | fifo_intr_0_bind_error_pending_f() | | ||
2360 | fifo_intr_0_sched_error_pending_f() | | ||
2361 | fifo_intr_0_chsw_error_pending_f() | | ||
2362 | fifo_intr_0_fb_flush_timeout_pending_f() | | ||
2363 | fifo_intr_0_dropped_mmu_fault_pending_f() | | ||
2364 | fifo_intr_0_mmu_fault_pending_f() | | ||
2365 | fifo_intr_0_lb_error_pending_f() | | ||
2366 | fifo_intr_0_pio_error_pending_f(); | ||
2367 | |||
2368 | u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r()); | ||
2369 | u32 clear_intr = 0; | 2387 | u32 clear_intr = 0; |
2388 | u32 fifo_intr = gk20a_readl(g, fifo_intr_0_r()); | ||
2389 | |||
2390 | error_intr_mask = g->ops.fifo.intr_0_error_mask(g); | ||
2370 | 2391 | ||
2371 | if (g->fifo.sw_ready) { | 2392 | if (g->fifo.sw_ready) { |
2372 | /* note we're not actually in an "isr", but rather | 2393 | /* note we're not actually in an "isr", but rather |
@@ -3780,4 +3801,5 @@ void gk20a_init_fifo(struct gpu_ops *gops) | |||
3780 | gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; | 3801 | gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; |
3781 | gops->fifo.dump_eng_status = gk20a_dump_eng_status; | 3802 | gops->fifo.dump_eng_status = gk20a_dump_eng_status; |
3782 | gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc; | 3803 | gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc; |
3804 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; | ||
3783 | } | 3805 | } |
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h index 30d0caba..2de5e2d6 100644 --- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.h | |||
@@ -313,6 +313,7 @@ void gk20a_get_ch_runlist_entry(struct channel_gk20a *ch, u32 *runlist); | |||
313 | 313 | ||
314 | u32 gk20a_userd_gp_get(struct gk20a *g, struct channel_gk20a *c); | 314 | u32 gk20a_userd_gp_get(struct gk20a *g, struct channel_gk20a *c); |
315 | void gk20a_userd_gp_put(struct gk20a *g, struct channel_gk20a *c); | 315 | void gk20a_userd_gp_put(struct gk20a *g, struct channel_gk20a *c); |
316 | |||
316 | bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); | 317 | bool gk20a_is_fault_engine_subid_gpc(struct gk20a *g, u32 engine_subid); |
317 | #ifdef CONFIG_DEBUG_FS | 318 | #ifdef CONFIG_DEBUG_FS |
318 | struct fifo_profile_gk20a *gk20a_fifo_profile_acquire(struct gk20a *g); | 319 | struct fifo_profile_gk20a *gk20a_fifo_profile_acquire(struct gk20a *g); |
@@ -333,4 +334,6 @@ const char *gk20a_decode_pbdma_chan_eng_ctx_status(u32 index); | |||
333 | 334 | ||
334 | struct channel_gk20a *gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr); | 335 | struct channel_gk20a *gk20a_refch_from_inst_ptr(struct gk20a *g, u64 inst_ptr); |
335 | 336 | ||
337 | u32 gk20a_fifo_intr_0_error_mask(struct gk20a *g); | ||
338 | |||
336 | #endif /*__GR_GK20A_H__*/ | 339 | #endif /*__GR_GK20A_H__*/ |
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h index 73123fa9..a4f0799a 100644 --- a/drivers/gpu/nvgpu/gk20a/gk20a.h +++ b/drivers/gpu/nvgpu/gk20a/gk20a.h | |||
@@ -450,6 +450,7 @@ struct gpu_ops { | |||
450 | void (*dump_channel_status_ramfc)(struct gk20a *g, | 450 | void (*dump_channel_status_ramfc)(struct gk20a *g, |
451 | struct gk20a_debug_output *o, u32 hw_chid, | 451 | struct gk20a_debug_output *o, u32 hw_chid, |
452 | struct ch_state *ch_state); | 452 | struct ch_state *ch_state); |
453 | u32 (*intr_0_error_mask)(struct gk20a *g); | ||
453 | } fifo; | 454 | } fifo; |
454 | struct pmu_v { | 455 | struct pmu_v { |
455 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ | 456 | /*used for change of enum zbc update cmd id from ver 0 to ver1*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 27ddc968..bf0fb018 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -174,4 +174,5 @@ void gm20b_init_fifo(struct gpu_ops *gops) | |||
174 | gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; | 174 | gops->fifo.dump_pbdma_status = gk20a_dump_pbdma_status; |
175 | gops->fifo.dump_eng_status = gk20a_dump_eng_status; | 175 | gops->fifo.dump_eng_status = gk20a_dump_eng_status; |
176 | gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc; | 176 | gops->fifo.dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc; |
177 | gops->fifo.intr_0_error_mask = gk20a_fifo_intr_0_error_mask; | ||
177 | } | 178 | } |