gpu: nvgpu: Remove MC accesses from gk20a.c

Clean up gk20a.c by removing direct accesses to MC and moving the
accesses to happen via MC HAL.

The chip detection logic has to violate the HAL and call gk20a
version directly, because HAL ops cannot be set up before chip has
been identified.

Change-Id: I4cdd0ef3fcf7d3b561a3fca4247a8356fe8d18e1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1321576
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

11 files changed, 96 insertions, 67 deletions

diff --git a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
index 4b8baad5..a1d348a4 100644
--- a/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fb_gk20a.c
@@ -30,10 +30,10 @@ void fb_gk20a_reset(struct gk20a *g)
 
         gk20a_dbg_info("reset gk20a fb");
 
-        gk20a_reset(g, mc_enable_pfb_enabled_f()
-                        | mc_enable_l2_enabled_f()
-                        | mc_enable_xbar_enabled_f()
-                        | mc_enable_hub_enabled_f());
+        g->ops.mc.reset(g, mc_enable_pfb_enabled_f() |
+                        mc_enable_l2_enabled_f() |
+                        mc_enable_xbar_enabled_f() |
+                        mc_enable_hub_enabled_f());
 
         val = gk20a_readl(g, mc_elpg_enable_r());
         val |= mc_elpg_enable_xbar_enabled_f()
diff --git a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
index 8f7a2e22..6c4f12df 100644
--- a/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/fifo_gk20a.c
@@ -766,7 +766,7 @@ int gk20a_init_fifo_reset_enable_hw(struct gk20a *g)
 
         gk20a_dbg_fn("");
         /* enable pmc pfifo */
-        gk20a_reset(g, mc_enable_pfifo_enabled_f());
+        g->ops.mc.reset(g, mc_enable_pfifo_enabled_f());
 
         if (g->ops.clock_gating.slcg_ce2_load_gating_prod)
                 g->ops.clock_gating.slcg_ce2_load_gating_prod(g,
@@ -1249,7 +1249,7 @@ void gk20a_fifo_reset_engine(struct gk20a *g, u32 engine_id)
         }
         if ((engine_enum == ENGINE_GRCE_GK20A) ||
                 (engine_enum == ENGINE_ASYNC_CE_GK20A)) {
-                        gk20a_reset(g, engine_info->reset_mask);
+                        g->ops.mc.reset(g, engine_info->reset_mask);
         }
 }
 
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.c b/drivers/gpu/nvgpu/gk20a/gk20a.c
index 694f0e93..e77986be 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.c
@@ -54,6 +54,7 @@
 #include "gk20a_scale.h"
 #include "ctxsw_trace_gk20a.h"
 #include "dbg_gpu_gk20a.h"
+#include "mc_gk20a.h"
 #include "hal.h"
 #include "vgpu/vgpu.h"
 #include "pci.h"
@@ -70,7 +71,6 @@
 #include "nvgpu_gpuid_t19x.h"
 #endif
 
-#include <nvgpu/hw/gk20a/hw_mc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_top_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_ltc_gk20a.h>
 #include <nvgpu/hw/gk20a/hw_fb_gk20a.h>
@@ -263,7 +263,7 @@ static const struct file_operations gk20a_sched_ops = {
 
 void __nvgpu_check_gpu_state(struct gk20a *g)
 {
-        u32 boot_0 = readl(g->regs + mc_boot_0_r());
+        u32 boot_0 = g->ops.mc.boot_0(g, NULL, NULL, NULL);
 
         if (boot_0 == 0xffffffff) {
                 pr_err("nvgpu: GPU has disappeared from bus!!\n");
@@ -474,18 +474,12 @@ done:
 static int gk20a_detect_chip(struct gk20a *g)
 {
         struct nvgpu_gpu_characteristics *gpu = &g->gpu_characteristics;
-        u32 mc_boot_0_value;
+        u32 val;
 
         if (gpu->arch)
                 return 0;
 
-        mc_boot_0_value = gk20a_readl(g, mc_boot_0_r());
-        gpu->arch = mc_boot_0_architecture_v(mc_boot_0_value) <<
-                NVGPU_GPU_ARCHITECTURE_SHIFT;
-        gpu->impl = mc_boot_0_implementation_v(mc_boot_0_value);
-        gpu->rev =
-                (mc_boot_0_major_revision_v(mc_boot_0_value) << 4) |
-                mc_boot_0_minor_revision_v(mc_boot_0_value);
+        val = gk20a_mc_boot_0(g, &gpu->arch, &gpu->impl, &gpu->rev);
 
         gk20a_dbg_info("arch: %x, impl: %x, rev: %x\n",
                         g->gpu_characteristics.arch,
@@ -1513,45 +1507,6 @@ fail:
         up_read(&g->busy_lock);
 }
 
-void gk20a_disable(struct gk20a *g, u32 units)
-{
-        u32 pmc;
-
-        gk20a_dbg(gpu_dbg_info, "pmc disable: %08x\n", units);
-
-        nvgpu_spinlock_acquire(&g->mc_enable_lock);
-        pmc = gk20a_readl(g, mc_enable_r());
-        pmc &= ~units;
-        gk20a_writel(g, mc_enable_r(), pmc);
-        nvgpu_spinlock_release(&g->mc_enable_lock);
-}
-
-void gk20a_enable(struct gk20a *g, u32 units)
-{
-        u32 pmc;
-
-        gk20a_dbg(gpu_dbg_info, "pmc enable: %08x\n", units);
-
-        nvgpu_spinlock_acquire(&g->mc_enable_lock);
-        pmc = gk20a_readl(g, mc_enable_r());
-        pmc |= units;
-        gk20a_writel(g, mc_enable_r(), pmc);
-        gk20a_readl(g, mc_enable_r());
-        nvgpu_spinlock_release(&g->mc_enable_lock);
-
-        udelay(20);
-}
-
-void gk20a_reset(struct gk20a *g, u32 units)
-{
-        gk20a_disable(g, units);
-        if (units & gk20a_fifo_get_all_ce_engine_reset_mask(g))
-                udelay(500);
-        else
-                udelay(20);
-        gk20a_enable(g, units);
-}
-
 #ifdef CONFIG_PM
 /**
  * __gk20a_do_idle() - force the GPU to idle and railgate
diff --git a/drivers/gpu/nvgpu/gk20a/gk20a.h b/drivers/gpu/nvgpu/gk20a/gk20a.h
index f4ca5649..4e1c4ff4 100644
--- a/drivers/gpu/nvgpu/gk20a/gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/gk20a.h
@@ -748,6 +748,10 @@ struct gpu_ops {
                 void (*isr_thread_nonstall)(struct gk20a *g, u32 intr);
                 void (*isr_nonstall_cb)(struct work_struct *work);
                 u32 intr_mask_restore[4];
+                void (*enable)(struct gk20a *g, u32 units);
+                void (*disable)(struct gk20a *g, u32 units);
+                void (*reset)(struct gk20a *g, u32 units);
+                u32 (*boot_0)(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
         } mc;
         struct {
                 void (*show_dump)(struct gk20a *g,
@@ -1406,9 +1410,6 @@ void gk20a_busy_noresume(struct device *dev);
 void gk20a_idle_nosuspend(struct device *dev);
 int __must_check gk20a_busy(struct gk20a *g);
 void gk20a_idle(struct gk20a *g);
-void gk20a_disable(struct gk20a *g, u32 units);
-void gk20a_enable(struct gk20a *g, u32 units);
-void gk20a_reset(struct gk20a *g, u32 units);
 int gk20a_do_idle(void);
 int gk20a_do_unidle(void);
 int __gk20a_do_idle(struct device *dev, bool force_reset);
diff --git a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
index 5121d6e9..63ae1da1 100644
--- a/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/gr_gk20a.c
@@ -4970,10 +4970,10 @@ static int gk20a_init_gr_prepare(struct gk20a *g)
         }
 
         /* reset gr engine */
-        gk20a_reset(g, mc_enable_pgraph_enabled_f()
-                        | mc_enable_blg_enabled_f()
-                        | mc_enable_perfmon_enabled_f()
-                        | ce_reset_mask);
+        g->ops.mc.reset(g, mc_enable_pgraph_enabled_f() |
+                        mc_enable_blg_enabled_f() |
+                        mc_enable_perfmon_enabled_f() |
+                        ce_reset_mask);
 
         gr_gk20a_load_gating_prod(g);
 
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
index e51c4a29..3d6919c5 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.c
@@ -14,6 +14,7 @@
  */
 
 #include <linux/types.h>
+#include <linux/delay.h>
 #include <trace/events/gk20a.h>
 
 #include "gk20a.h"
@@ -248,6 +249,63 @@ void mc_gk20a_intr_unit_config(struct gk20a *g, bool enable,
         }
 }
 
+void gk20a_mc_disable(struct gk20a *g, u32 units)
+{
+        u32 pmc;
+
+        gk20a_dbg(gpu_dbg_info, "pmc disable: %08x\n", units);
+
+        nvgpu_spinlock_acquire(&g->mc_enable_lock);
+        pmc = gk20a_readl(g, mc_enable_r());
+        pmc &= ~units;
+        gk20a_writel(g, mc_enable_r(), pmc);
+        nvgpu_spinlock_release(&g->mc_enable_lock);
+}
+
+void gk20a_mc_enable(struct gk20a *g, u32 units)
+{
+        u32 pmc;
+
+        gk20a_dbg(gpu_dbg_info, "pmc enable: %08x\n", units);
+
+        nvgpu_spinlock_acquire(&g->mc_enable_lock);
+        pmc = gk20a_readl(g, mc_enable_r());
+        pmc |= units;
+        gk20a_writel(g, mc_enable_r(), pmc);
+        gk20a_readl(g, mc_enable_r());
+        nvgpu_spinlock_release(&g->mc_enable_lock);
+
+        udelay(20);
+}
+
+void gk20a_mc_reset(struct gk20a *g, u32 units)
+{
+        g->ops.mc.disable(g, units);
+        if (units & gk20a_fifo_get_all_ce_engine_reset_mask(g))
+                udelay(500);
+        else
+                udelay(20);
+        g->ops.mc.enable(g, units);
+}
+
+u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev)
+{
+        u32 val = gk20a_readl(g, mc_boot_0_r());
+
+        if (arch)
+                *arch = mc_boot_0_architecture_v(val) <<
+                        NVGPU_GPU_ARCHITECTURE_SHIFT;
+
+        if (impl)
+                *impl = mc_boot_0_implementation_v(val);
+
+        if (rev)
+                *rev = (mc_boot_0_major_revision_v(val) << 4) |
+                        mc_boot_0_minor_revision_v(val);
+
+        return val;
+}
+
 void gk20a_init_mc(struct gpu_ops *gops)
 {
         gops->mc.intr_enable = mc_gk20a_intr_enable;
@@ -257,4 +315,8 @@ void gk20a_init_mc(struct gpu_ops *gops)
         gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall;
         gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall;
         gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb;
+        gops->mc.enable = gk20a_mc_enable;
+        gops->mc.disable = gk20a_mc_disable;
+        gops->mc.reset = gk20a_mc_reset;
+        gops->mc.boot_0 = gk20a_mc_boot_0;
 }
diff --git a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
index 1aad1a0b..9c70eba1 100644
--- a/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
+++ b/drivers/gpu/nvgpu/gk20a/mc_gk20a.h
@@ -24,4 +24,8 @@ irqreturn_t mc_gk20a_isr_nonstall(struct gk20a *g);
 irqreturn_t mc_gk20a_intr_thread_stall(struct gk20a *g);
 void mc_gk20a_intr_thread_nonstall(struct gk20a *g, u32 intr);
 void mc_gk20a_nonstall_cb(struct work_struct *work);
+void gk20a_mc_enable(struct gk20a *g, u32 units);
+void gk20a_mc_disable(struct gk20a *g, u32 units);
+void gk20a_mc_reset(struct gk20a *g, u32 units);
+u32 gk20a_mc_boot_0(struct gk20a *g, u32 *arch, u32 *impl, u32 *rev);
 #endif
diff --git a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
index a240ccf1..993cef7b 100644
--- a/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/pmu_gk20a.c
@@ -2380,7 +2380,7 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
         if (enable) {
                 int retries = PMU_MEM_SCRUBBING_TIMEOUT_MAX /
                               PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT;
-                gk20a_enable(g, mc_enable_pwr_enabled_f());
+                g->ops.mc.enable(g, mc_enable_pwr_enabled_f());
 
                 if (g->ops.clock_gating.slcg_pmu_load_gating_prod)
                         g->ops.clock_gating.slcg_pmu_load_gating_prod(g,
@@ -2401,12 +2401,12 @@ int pmu_enable_hw(struct pmu_gk20a *pmu, bool enable)
                         udelay(PMU_MEM_SCRUBBING_TIMEOUT_DEFAULT);
                 } while (--retries || !tegra_platform_is_silicon());
 
-                gk20a_disable(g, mc_enable_pwr_enabled_f());
+                g->ops.mc.disable(g, mc_enable_pwr_enabled_f());
                 gk20a_err(dev_from_gk20a(g), "Falcon mem scrubbing timeout");
 
                 return -ETIMEDOUT;
         } else {
-                gk20a_disable(g, mc_enable_pwr_enabled_f());
+                g->ops.mc.disable(g, mc_enable_pwr_enabled_f());
                 return 0;
         }
 }
diff --git a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
index a44df1e8..752ee121 100644
--- a/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
+++ b/drivers/gpu/nvgpu/gk20a/priv_ring_gk20a.c
@@ -50,7 +50,7 @@ static void gk20a_reset_priv_ring(struct gk20a *g)
 {
         u32 val;
 
-        gk20a_reset(g, mc_enable_priv_ring_enabled_f());
+        g->ops.mc.reset(g, mc_enable_priv_ring_enabled_f());
 
         val = gk20a_readl(g, pri_ringstation_sys_decode_config_r());
         val = set_field(val,
diff --git a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
index c8a42cd7..7d0d052d 100644
--- a/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mc_gm20b.c
@@ -28,4 +28,8 @@ void gm20b_init_mc(struct gpu_ops *gops)
         gops->mc.isr_thread_stall = mc_gk20a_intr_thread_stall;
         gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall;
         gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb;
+        gops->mc.enable = gk20a_mc_enable;
+        gops->mc.disable = gk20a_mc_disable;
+        gops->mc.reset = gk20a_mc_reset;
+        gops->mc.boot_0 = gk20a_mc_boot_0;
 }
diff --git a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
index 547169ed..4b0cbc1c 100644
--- a/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
+++ b/drivers/gpu/nvgpu/gp10b/mc_gp10b.c
@@ -184,5 +184,8 @@ void gp10b_init_mc(struct gpu_ops *gops)
         gops->mc.isr_thread_stall = mc_gp10b_intr_thread_stall;
         gops->mc.isr_thread_nonstall = mc_gk20a_intr_thread_nonstall;
         gops->mc.isr_nonstall_cb = mc_gk20a_nonstall_cb;
-
+        gops->mc.enable = gk20a_mc_enable;
+        gops->mc.disable = gk20a_mc_disable;
+        gops->mc.reset = gk20a_mc_reset;
+        gops->mc.boot_0 = gk20a_mc_boot_0;
 }